Modules
	Exported_macros

Macros
#define	ADC_ISR_ADRDY_Pos (0U)

#define	ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos)

#define	ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk

#define	ADC_ISR_EOSMP_Pos (1U)

#define	ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos)

#define	ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk

#define	ADC_ISR_EOC_Pos (2U)

#define	ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos)

#define	ADC_ISR_EOC ADC_ISR_EOC_Msk

#define	ADC_ISR_EOS_Pos (3U)

#define	ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos)

#define	ADC_ISR_EOS ADC_ISR_EOS_Msk

#define	ADC_ISR_OVR_Pos (4U)

#define	ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos)

#define	ADC_ISR_OVR ADC_ISR_OVR_Msk

#define	ADC_ISR_AWD1_Pos (7U)

#define	ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos)

#define	ADC_ISR_AWD1 ADC_ISR_AWD1_Msk

#define	ADC_ISR_AWD2_Pos (8U)

#define	ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos)

#define	ADC_ISR_AWD2 ADC_ISR_AWD2_Msk

#define	ADC_ISR_AWD3_Pos (9U)

#define	ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos)

#define	ADC_ISR_AWD3 ADC_ISR_AWD3_Msk

#define	ADC_ISR_EOCAL_Pos (11U)

#define	ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos)

#define	ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk

#define	ADC_ISR_CCRDY_Pos (13U)

#define	ADC_ISR_CCRDY_Msk (0x1UL << ADC_ISR_CCRDY_Pos)

#define	ADC_ISR_CCRDY ADC_ISR_CCRDY_Msk

#define	ADC_ISR_EOSEQ (ADC_ISR_EOS)

#define	ADC_IER_ADRDYIE_Pos (0U)

#define	ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos)

#define	ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk

#define	ADC_IER_EOSMPIE_Pos (1U)

#define	ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos)

#define	ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk

#define	ADC_IER_EOCIE_Pos (2U)

#define	ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos)

#define	ADC_IER_EOCIE ADC_IER_EOCIE_Msk

#define	ADC_IER_EOSIE_Pos (3U)

#define	ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos)

#define	ADC_IER_EOSIE ADC_IER_EOSIE_Msk

#define	ADC_IER_OVRIE_Pos (4U)

#define	ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos)

#define	ADC_IER_OVRIE ADC_IER_OVRIE_Msk

#define	ADC_IER_AWD1IE_Pos (7U)

#define	ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos)

#define	ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk

#define	ADC_IER_AWD2IE_Pos (8U)

#define	ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos)

#define	ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk

#define	ADC_IER_AWD3IE_Pos (9U)

#define	ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos)

#define	ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk

#define	ADC_IER_EOCALIE_Pos (11U)

#define	ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos)

#define	ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk

#define	ADC_IER_CCRDYIE_Pos (13U)

#define	ADC_IER_CCRDYIE_Msk (0x1UL << ADC_IER_CCRDYIE_Pos)

#define	ADC_IER_CCRDYIE ADC_IER_CCRDYIE_Msk

#define	ADC_IER_EOSEQIE (ADC_IER_EOSIE)

#define	ADC_CR_ADEN_Pos (0U)

#define	ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos)

#define	ADC_CR_ADEN ADC_CR_ADEN_Msk

#define	ADC_CR_ADDIS_Pos (1U)

#define	ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos)

#define	ADC_CR_ADDIS ADC_CR_ADDIS_Msk

#define	ADC_CR_ADSTART_Pos (2U)

#define	ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos)

#define	ADC_CR_ADSTART ADC_CR_ADSTART_Msk

#define	ADC_CR_ADSTP_Pos (4U)

#define	ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos)

#define	ADC_CR_ADSTP ADC_CR_ADSTP_Msk

#define	ADC_CR_ADVREGEN_Pos (28U)

#define	ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos)

#define	ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk

#define	ADC_CR_ADCAL_Pos (31U)

#define	ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos)

#define	ADC_CR_ADCAL ADC_CR_ADCAL_Msk

#define	ADC_CFGR1_DMAEN_Pos (0U)

#define	ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos)

#define	ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk

#define	ADC_CFGR1_DMACFG_Pos (1U)

#define	ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos)

#define	ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk

#define	ADC_CFGR1_SCANDIR_Pos (2U)

#define	ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos)

#define	ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk

#define	ADC_CFGR1_RES_Pos (3U)

#define	ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos)

#define	ADC_CFGR1_RES ADC_CFGR1_RES_Msk

#define	ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos)

#define	ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos)

#define	ADC_CFGR1_ALIGN_Pos (5U)

#define	ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos)

#define	ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk

#define	ADC_CFGR1_EXTSEL_Pos (6U)

#define	ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos)

#define	ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk

#define	ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos)

#define	ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos)

#define	ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos)

#define	ADC_CFGR1_EXTEN_Pos (10U)

#define	ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos)

#define	ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk

#define	ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos)

#define	ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos)

#define	ADC_CFGR1_OVRMOD_Pos (12U)

#define	ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos)

#define	ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk

#define	ADC_CFGR1_CONT_Pos (13U)

#define	ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos)

#define	ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk

#define	ADC_CFGR1_WAIT_Pos (14U)

#define	ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos)

#define	ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk

#define	ADC_CFGR1_AUTOFF_Pos (15U)

#define	ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos)

#define	ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk

#define	ADC_CFGR1_DISCEN_Pos (16U)

#define	ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos)

#define	ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk

#define	ADC_CFGR1_CHSELRMOD_Pos (21U)

#define	ADC_CFGR1_CHSELRMOD_Msk (0x1UL << ADC_CFGR1_CHSELRMOD_Pos)

#define	ADC_CFGR1_CHSELRMOD ADC_CFGR1_CHSELRMOD_Msk

#define	ADC_CFGR1_AWD1SGL_Pos (22U)

#define	ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos)

#define	ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk

#define	ADC_CFGR1_AWD1EN_Pos (23U)

#define	ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos)

#define	ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk

#define	ADC_CFGR1_AWD1CH_Pos (26U)

#define	ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos)

#define	ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk

#define	ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos)

#define	ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos)

#define	ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos)

#define	ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos)

#define	ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos)

#define	ADC_CFGR1_AUTDLY (ADC_CFGR1_WAIT)

#define	ADC_CFGR2_OVSE_Pos (0U)

#define	ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos)

#define	ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk

#define	ADC_CFGR2_OVSR_Pos (2U)

#define	ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos)

#define	ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk

#define	ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos)

#define	ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos)

#define	ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos)

#define	ADC_CFGR2_OVSS_Pos (5U)

#define	ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos)

#define	ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk

#define	ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos)

#define	ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos)

#define	ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos)

#define	ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos)

#define	ADC_CFGR2_TOVS_Pos (9U)

#define	ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos)

#define	ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk

#define	ADC_CFGR2_LFTRIG_Pos (29U)

#define	ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos)

#define	ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk

#define	ADC_CFGR2_CKMODE_Pos (30U)

#define	ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos)

#define	ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk

#define	ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos)

#define	ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos)

#define	ADC_SMPR_SMP1_Pos (0U)

#define	ADC_SMPR_SMP1_Msk (0x7UL << ADC_SMPR_SMP1_Pos)

#define	ADC_SMPR_SMP1 ADC_SMPR_SMP1_Msk

#define	ADC_SMPR_SMP1_0 (0x1UL << ADC_SMPR_SMP1_Pos)

#define	ADC_SMPR_SMP1_1 (0x2UL << ADC_SMPR_SMP1_Pos)

#define	ADC_SMPR_SMP1_2 (0x4UL << ADC_SMPR_SMP1_Pos)

#define	ADC_SMPR_SMP2_Pos (4U)

#define	ADC_SMPR_SMP2_Msk (0x7UL << ADC_SMPR_SMP2_Pos)

#define	ADC_SMPR_SMP2 ADC_SMPR_SMP2_Msk

#define	ADC_SMPR_SMP2_0 (0x1UL << ADC_SMPR_SMP2_Pos)

#define	ADC_SMPR_SMP2_1 (0x2UL << ADC_SMPR_SMP2_Pos)

#define	ADC_SMPR_SMP2_2 (0x4UL << ADC_SMPR_SMP2_Pos)

#define	ADC_SMPR_SMPSEL_Pos (8U)

#define	ADC_SMPR_SMPSEL_Msk (0x7FFFFUL << ADC_SMPR_SMPSEL_Pos)

#define	ADC_SMPR_SMPSEL ADC_SMPR_SMPSEL_Msk

#define	ADC_SMPR_SMPSEL0_Pos (8U)

#define	ADC_SMPR_SMPSEL0_Msk (0x1UL << ADC_SMPR_SMPSEL0_Pos)

#define	ADC_SMPR_SMPSEL0 ADC_SMPR_SMPSEL0_Msk

#define	ADC_SMPR_SMPSEL1_Pos (9U)

#define	ADC_SMPR_SMPSEL1_Msk (0x1UL << ADC_SMPR_SMPSEL1_Pos)

#define	ADC_SMPR_SMPSEL1 ADC_SMPR_SMPSEL1_Msk

#define	ADC_SMPR_SMPSEL2_Pos (10U)

#define	ADC_SMPR_SMPSEL2_Msk (0x1UL << ADC_SMPR_SMPSEL2_Pos)

#define	ADC_SMPR_SMPSEL2 ADC_SMPR_SMPSEL2_Msk

#define	ADC_SMPR_SMPSEL3_Pos (11U)

#define	ADC_SMPR_SMPSEL3_Msk (0x1UL << ADC_SMPR_SMPSEL3_Pos)

#define	ADC_SMPR_SMPSEL3 ADC_SMPR_SMPSEL3_Msk

#define	ADC_SMPR_SMPSEL4_Pos (12U)

#define	ADC_SMPR_SMPSEL4_Msk (0x1UL << ADC_SMPR_SMPSEL4_Pos)

#define	ADC_SMPR_SMPSEL4 ADC_SMPR_SMPSEL4_Msk

#define	ADC_SMPR_SMPSEL5_Pos (13U)

#define	ADC_SMPR_SMPSEL5_Msk (0x1UL << ADC_SMPR_SMPSEL5_Pos)

#define	ADC_SMPR_SMPSEL5 ADC_SMPR_SMPSEL5_Msk

#define	ADC_SMPR_SMPSEL6_Pos (14U)

#define	ADC_SMPR_SMPSEL6_Msk (0x1UL << ADC_SMPR_SMPSEL6_Pos)

#define	ADC_SMPR_SMPSEL6 ADC_SMPR_SMPSEL6_Msk

#define	ADC_SMPR_SMPSEL7_Pos (15U)

#define	ADC_SMPR_SMPSEL7_Msk (0x1UL << ADC_SMPR_SMPSEL7_Pos)

#define	ADC_SMPR_SMPSEL7 ADC_SMPR_SMPSEL7_Msk

#define	ADC_SMPR_SMPSEL8_Pos (16U)

#define	ADC_SMPR_SMPSEL8_Msk (0x1UL << ADC_SMPR_SMPSEL8_Pos)

#define	ADC_SMPR_SMPSEL8 ADC_SMPR_SMPSEL8_Msk

#define	ADC_SMPR_SMPSEL9_Pos (17U)

#define	ADC_SMPR_SMPSEL9_Msk (0x1UL << ADC_SMPR_SMPSEL9_Pos)

#define	ADC_SMPR_SMPSEL9 ADC_SMPR_SMPSEL9_Msk

#define	ADC_SMPR_SMPSEL10_Pos (18U)

#define	ADC_SMPR_SMPSEL10_Msk (0x1UL << ADC_SMPR_SMPSEL10_Pos)

#define	ADC_SMPR_SMPSEL10 ADC_SMPR_SMPSEL10_Msk

#define	ADC_SMPR_SMPSEL11_Pos (19U)

#define	ADC_SMPR_SMPSEL11_Msk (0x1UL << ADC_SMPR_SMPSEL11_Pos)

#define	ADC_SMPR_SMPSEL11 ADC_SMPR_SMPSEL11_Msk

#define	ADC_SMPR_SMPSEL12_Pos (20U)

#define	ADC_SMPR_SMPSEL12_Msk (0x1UL << ADC_SMPR_SMPSEL12_Pos)

#define	ADC_SMPR_SMPSEL12 ADC_SMPR_SMPSEL12_Msk

#define	ADC_SMPR_SMPSEL13_Pos (21U)

#define	ADC_SMPR_SMPSEL13_Msk (0x1UL << ADC_SMPR_SMPSEL13_Pos)

#define	ADC_SMPR_SMPSEL13 ADC_SMPR_SMPSEL13_Msk

#define	ADC_SMPR_SMPSEL14_Pos (22U)

#define	ADC_SMPR_SMPSEL14_Msk (0x1UL << ADC_SMPR_SMPSEL14_Pos)

#define	ADC_SMPR_SMPSEL14 ADC_SMPR_SMPSEL14_Msk

#define	ADC_SMPR_SMPSEL15_Pos (23U)

#define	ADC_SMPR_SMPSEL15_Msk (0x1UL << ADC_SMPR_SMPSEL15_Pos)

#define	ADC_SMPR_SMPSEL15 ADC_SMPR_SMPSEL15_Msk

#define	ADC_SMPR_SMPSEL16_Pos (24U)

#define	ADC_SMPR_SMPSEL16_Msk (0x1UL << ADC_SMPR_SMPSEL16_Pos)

#define	ADC_SMPR_SMPSEL16 ADC_SMPR_SMPSEL16_Msk

#define	ADC_SMPR_SMPSEL17_Pos (25U)

#define	ADC_SMPR_SMPSEL17_Msk (0x1UL << ADC_SMPR_SMPSEL17_Pos)

#define	ADC_SMPR_SMPSEL17 ADC_SMPR_SMPSEL17_Msk

#define	ADC_SMPR_SMPSEL18_Pos (26U)

#define	ADC_SMPR_SMPSEL18_Msk (0x1UL << ADC_SMPR_SMPSEL18_Pos)

#define	ADC_SMPR_SMPSEL18 ADC_SMPR_SMPSEL18_Msk

#define	ADC_AWD1TR_LT1_Pos (0U)

#define	ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos)

#define	ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk

#define	ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos)

#define	ADC_AWD1TR_LT1_1 (0x002UL << ADC_AWD1TR_LT1_Pos)

#define	ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos)

#define	ADC_AWD1TR_LT1_3 (0x008UL << ADC_AWD1TR_LT1_Pos)

#define	ADC_AWD1TR_LT1_4 (0x010UL << ADC_AWD1TR_LT1_Pos)

#define	ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos)

#define	ADC_AWD1TR_LT1_6 (0x040UL << ADC_AWD1TR_LT1_Pos)

#define	ADC_AWD1TR_LT1_7 (0x080UL << ADC_AWD1TR_LT1_Pos)

#define	ADC_AWD1TR_LT1_8 (0x100UL << ADC_AWD1TR_LT1_Pos)

#define	ADC_AWD1TR_LT1_9 (0x200UL << ADC_AWD1TR_LT1_Pos)

#define	ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos)

#define	ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos)

#define	ADC_AWD1TR_HT1_Pos (16U)

#define	ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos)

#define	ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk

#define	ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos)

#define	ADC_AWD1TR_HT1_1 (0x002UL << ADC_AWD1TR_HT1_Pos)

#define	ADC_AWD1TR_HT1_2 (0x004UL << ADC_AWD1TR_HT1_Pos)

#define	ADC_AWD1TR_HT1_3 (0x008UL << ADC_AWD1TR_HT1_Pos)

#define	ADC_AWD1TR_HT1_4 (0x010UL << ADC_AWD1TR_HT1_Pos)

#define	ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos)

#define	ADC_AWD1TR_HT1_6 (0x040UL << ADC_AWD1TR_HT1_Pos)

#define	ADC_AWD1TR_HT1_7 (0x080UL << ADC_AWD1TR_HT1_Pos)

#define	ADC_AWD1TR_HT1_8 (0x100UL << ADC_AWD1TR_HT1_Pos)

#define	ADC_AWD1TR_HT1_9 (0x200UL << ADC_AWD1TR_HT1_Pos)

#define	ADC_AWD1TR_HT1_10 (0x400UL << ADC_AWD1TR_HT1_Pos)

#define	ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos)

#define	ADC_TR1_LT1 ADC_AWD1TR_LT1

#define	ADC_TR1_LT1_0 ADC_AWD1TR_LT1_0

#define	ADC_TR1_LT1_1 ADC_AWD1TR_LT1_1

#define	ADC_TR1_LT1_2 ADC_AWD1TR_LT1_2

#define	ADC_TR1_LT1_3 ADC_AWD1TR_LT1_3

#define	ADC_TR1_LT1_4 ADC_AWD1TR_LT1_4

#define	ADC_TR1_LT1_5 ADC_AWD1TR_LT1_5

#define	ADC_TR1_LT1_6 ADC_AWD1TR_LT1_6

#define	ADC_TR1_LT1_7 ADC_AWD1TR_LT1_7

#define	ADC_TR1_LT1_8 ADC_AWD1TR_LT1_8

#define	ADC_TR1_LT1_9 ADC_AWD1TR_LT1_9

#define	ADC_TR1_LT1_10 ADC_AWD1TR_LT1_10

#define	ADC_TR1_LT1_11 ADC_AWD1TR_LT1_11

#define	ADC_TR1_HT1 ADC_AWD1TR_HT1

#define	ADC_TR1_HT1_0 ADC_AWD1TR_HT1_0

#define	ADC_TR1_HT1_1 ADC_AWD1TR_HT1_1

#define	ADC_TR1_HT1_2 ADC_AWD1TR_HT1_2

#define	ADC_TR1_HT1_3 ADC_AWD1TR_HT1_3

#define	ADC_TR1_HT1_4 ADC_AWD1TR_HT1_4

#define	ADC_TR1_HT1_5 ADC_AWD1TR_HT1_5

#define	ADC_TR1_HT1_6 ADC_AWD1TR_HT1_6

#define	ADC_TR1_HT1_7 ADC_AWD1TR_HT1_7

#define	ADC_TR1_HT1_8 ADC_AWD1TR_HT1_8

#define	ADC_TR1_HT1_9 ADC_AWD1TR_HT1_9

#define	ADC_TR1_HT1_10 ADC_AWD1TR_HT1_10

#define	ADC_TR1_HT1_11 ADC_AWD1TR_HT1_11

#define	ADC_AWD2TR_LT2_Pos (0U)

#define	ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos)

#define	ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk

#define	ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos)

#define	ADC_AWD2TR_LT2_1 (0x002UL << ADC_AWD2TR_LT2_Pos)

#define	ADC_AWD2TR_LT2_2 (0x004UL << ADC_AWD2TR_LT2_Pos)

#define	ADC_AWD2TR_LT2_3 (0x008UL << ADC_AWD2TR_LT2_Pos)

#define	ADC_AWD2TR_LT2_4 (0x010UL << ADC_AWD2TR_LT2_Pos)

#define	ADC_AWD2TR_LT2_5 (0x020UL << ADC_AWD2TR_LT2_Pos)

#define	ADC_AWD2TR_LT2_6 (0x040UL << ADC_AWD2TR_LT2_Pos)

#define	ADC_AWD2TR_LT2_7 (0x080UL << ADC_AWD2TR_LT2_Pos)

#define	ADC_AWD2TR_LT2_8 (0x100UL << ADC_AWD2TR_LT2_Pos)

#define	ADC_AWD2TR_LT2_9 (0x200UL << ADC_AWD2TR_LT2_Pos)

#define	ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos)

#define	ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos)

#define	ADC_AWD2TR_HT2_Pos (16U)

#define	ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos)

#define	ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk

#define	ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos)

#define	ADC_AWD2TR_HT2_1 (0x002UL << ADC_AWD2TR_HT2_Pos)

#define	ADC_AWD2TR_HT2_2 (0x004UL << ADC_AWD2TR_HT2_Pos)

#define	ADC_AWD2TR_HT2_3 (0x008UL << ADC_AWD2TR_HT2_Pos)

#define	ADC_AWD2TR_HT2_4 (0x010UL << ADC_AWD2TR_HT2_Pos)

#define	ADC_AWD2TR_HT2_5 (0x020UL << ADC_AWD2TR_HT2_Pos)

#define	ADC_AWD2TR_HT2_6 (0x040UL << ADC_AWD2TR_HT2_Pos)

#define	ADC_AWD2TR_HT2_7 (0x080UL << ADC_AWD2TR_HT2_Pos)

#define	ADC_AWD2TR_HT2_8 (0x100UL << ADC_AWD2TR_HT2_Pos)

#define	ADC_AWD2TR_HT2_9 (0x200UL << ADC_AWD2TR_HT2_Pos)

#define	ADC_AWD2TR_HT2_10 (0x400UL << ADC_AWD2TR_HT2_Pos)

#define	ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos)

#define	ADC_TR2_LT2 ADC_AWD2TR_LT2

#define	ADC_TR2_LT2_0 ADC_AWD2TR_LT2_0

#define	ADC_TR2_LT2_1 ADC_AWD2TR_LT2_1

#define	ADC_TR2_LT2_2 ADC_AWD2TR_LT2_2

#define	ADC_TR2_LT2_3 ADC_AWD2TR_LT2_3

#define	ADC_TR2_LT2_4 ADC_AWD2TR_LT2_4

#define	ADC_TR2_LT2_5 ADC_AWD2TR_LT2_5

#define	ADC_TR2_LT2_6 ADC_AWD2TR_LT2_6

#define	ADC_TR2_LT2_7 ADC_AWD2TR_LT2_7

#define	ADC_TR2_LT2_8 ADC_AWD2TR_LT2_8

#define	ADC_TR2_LT2_9 ADC_AWD2TR_LT2_9

#define	ADC_TR2_LT2_10 ADC_AWD2TR_LT2_10

#define	ADC_TR2_LT2_11 ADC_AWD2TR_LT2_11

#define	ADC_TR2_HT2 ADC_AWD2TR_HT2

#define	ADC_TR2_HT2_0 ADC_AWD2TR_HT2_0

#define	ADC_TR2_HT2_1 ADC_AWD2TR_HT2_1

#define	ADC_TR2_HT2_2 ADC_AWD2TR_HT2_2

#define	ADC_TR2_HT2_3 ADC_AWD2TR_HT2_3

#define	ADC_TR2_HT2_4 ADC_AWD2TR_HT2_4

#define	ADC_TR2_HT2_5 ADC_AWD2TR_HT2_5

#define	ADC_TR2_HT2_6 ADC_AWD2TR_HT2_6

#define	ADC_TR2_HT2_7 ADC_AWD2TR_HT2_7

#define	ADC_TR2_HT2_8 ADC_AWD2TR_HT2_8

#define	ADC_TR2_HT2_9 ADC_AWD2TR_HT2_9

#define	ADC_TR2_HT2_10 ADC_AWD2TR_HT2_10

#define	ADC_TR2_HT2_11 ADC_AWD2TR_HT2_11

#define	ADC_CHSELR_CHSEL_Pos (0U)

#define	ADC_CHSELR_CHSEL_Msk (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos)

#define	ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk

#define	ADC_CHSELR_CHSEL18_Pos (18U)

#define	ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos)

#define	ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk

#define	ADC_CHSELR_CHSEL17_Pos (17U)

#define	ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos)

#define	ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk

#define	ADC_CHSELR_CHSEL16_Pos (16U)

#define	ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos)

#define	ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk

#define	ADC_CHSELR_CHSEL15_Pos (15U)

#define	ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos)

#define	ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk

#define	ADC_CHSELR_CHSEL14_Pos (14U)

#define	ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos)

#define	ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk

#define	ADC_CHSELR_CHSEL13_Pos (13U)

#define	ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos)

#define	ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk

#define	ADC_CHSELR_CHSEL12_Pos (12U)

#define	ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos)

#define	ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk

#define	ADC_CHSELR_CHSEL11_Pos (11U)

#define	ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos)

#define	ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk

#define	ADC_CHSELR_CHSEL10_Pos (10U)

#define	ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos)

#define	ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk

#define	ADC_CHSELR_CHSEL9_Pos (9U)

#define	ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos)

#define	ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk

#define	ADC_CHSELR_CHSEL8_Pos (8U)

#define	ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos)

#define	ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk

#define	ADC_CHSELR_CHSEL7_Pos (7U)

#define	ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos)

#define	ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk

#define	ADC_CHSELR_CHSEL6_Pos (6U)

#define	ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos)

#define	ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk

#define	ADC_CHSELR_CHSEL5_Pos (5U)

#define	ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos)

#define	ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk

#define	ADC_CHSELR_CHSEL4_Pos (4U)

#define	ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos)

#define	ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk

#define	ADC_CHSELR_CHSEL3_Pos (3U)

#define	ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos)

#define	ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk

#define	ADC_CHSELR_CHSEL2_Pos (2U)

#define	ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos)

#define	ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk

#define	ADC_CHSELR_CHSEL1_Pos (1U)

#define	ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos)

#define	ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk

#define	ADC_CHSELR_CHSEL0_Pos (0U)

#define	ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos)

#define	ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk

#define	ADC_CHSELR_SQ_ALL_Pos (0U)

#define	ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos)

#define	ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk

#define	ADC_CHSELR_SQ8_Pos (28U)

#define	ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos)

#define	ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk

#define	ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos)

#define	ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos)

#define	ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos)

#define	ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos)

#define	ADC_CHSELR_SQ7_Pos (24U)

#define	ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos)

#define	ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk

#define	ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos)

#define	ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos)

#define	ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos)

#define	ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos)

#define	ADC_CHSELR_SQ6_Pos (20U)

#define	ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos)

#define	ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk

#define	ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos)

#define	ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos)

#define	ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos)

#define	ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos)

#define	ADC_CHSELR_SQ5_Pos (16U)

#define	ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos)

#define	ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk

#define	ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos)

#define	ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos)

#define	ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos)

#define	ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos)

#define	ADC_CHSELR_SQ4_Pos (12U)

#define	ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos)

#define	ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk

#define	ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos)

#define	ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos)

#define	ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos)

#define	ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos)

#define	ADC_CHSELR_SQ3_Pos (8U)

#define	ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos)

#define	ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk

#define	ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos)

#define	ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos)

#define	ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos)

#define	ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos)

#define	ADC_CHSELR_SQ2_Pos (4U)

#define	ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos)

#define	ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk

#define	ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos)

#define	ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos)

#define	ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos)

#define	ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos)

#define	ADC_CHSELR_SQ1_Pos (0U)

#define	ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos)

#define	ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk

#define	ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos)

#define	ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos)

#define	ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos)

#define	ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos)

#define	ADC_AWD3TR_LT3_Pos (0U)

#define	ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos)

#define	ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk

#define	ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos)

#define	ADC_AWD3TR_LT3_1 (0x002UL << ADC_AWD3TR_LT3_Pos)

#define	ADC_AWD3TR_LT3_2 (0x004UL << ADC_AWD3TR_LT3_Pos)

#define	ADC_AWD3TR_LT3_3 (0x008UL << ADC_AWD3TR_LT3_Pos)

#define	ADC_AWD3TR_LT3_4 (0x010UL << ADC_AWD3TR_LT3_Pos)

#define	ADC_AWD3TR_LT3_5 (0x020UL << ADC_AWD3TR_LT3_Pos)

#define	ADC_AWD3TR_LT3_6 (0x040UL << ADC_AWD3TR_LT3_Pos)

#define	ADC_AWD3TR_LT3_7 (0x080UL << ADC_AWD3TR_LT3_Pos)

#define	ADC_AWD3TR_LT3_8 (0x100UL << ADC_AWD3TR_LT3_Pos)

#define	ADC_AWD3TR_LT3_9 (0x200UL << ADC_AWD3TR_LT3_Pos)

#define	ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos)

#define	ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos)

#define	ADC_AWD3TR_HT3_Pos (16U)

#define	ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos)

#define	ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk

#define	ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos)

#define	ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos)

#define	ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos)

#define	ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos)

#define	ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos)

#define	ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos)

#define	ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos)

#define	ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos)

#define	ADC_AWD3TR_HT3_8 (0x100UL << ADC_AWD3TR_HT3_Pos)

#define	ADC_AWD3TR_HT3_9 (0x200UL << ADC_AWD3TR_HT3_Pos)

#define	ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos)

#define	ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos)

#define	ADC_TR3_LT3 ADC_AWD3TR_LT3

#define	ADC_TR3_LT3_0 ADC_AWD3TR_LT3_0

#define	ADC_TR3_LT3_1 ADC_AWD3TR_LT3_1

#define	ADC_TR3_LT3_2 ADC_AWD3TR_LT3_2

#define	ADC_TR3_LT3_3 ADC_AWD3TR_LT3_3

#define	ADC_TR3_LT3_4 ADC_AWD3TR_LT3_4

#define	ADC_TR3_LT3_5 ADC_AWD3TR_LT3_5

#define	ADC_TR3_LT3_6 ADC_AWD3TR_LT3_6

#define	ADC_TR3_LT3_7 ADC_AWD3TR_LT3_7

#define	ADC_TR3_LT3_8 ADC_AWD3TR_LT3_8

#define	ADC_TR3_LT3_9 ADC_AWD3TR_LT3_9

#define	ADC_TR3_LT3_10 ADC_AWD3TR_LT3_10

#define	ADC_TR3_LT3_11 ADC_AWD3TR_LT3_11

#define	ADC_TR3_HT3 ADC_AWD3TR_HT3

#define	ADC_TR3_HT3_0 ADC_AWD3TR_HT3_0

#define	ADC_TR3_HT3_1 ADC_AWD3TR_HT3_1

#define	ADC_TR3_HT3_2 ADC_AWD3TR_HT3_2

#define	ADC_TR3_HT3_3 ADC_AWD3TR_HT3_3

#define	ADC_TR3_HT3_4 ADC_AWD3TR_HT3_4

#define	ADC_TR3_HT3_5 ADC_AWD3TR_HT3_5

#define	ADC_TR3_HT3_6 ADC_AWD3TR_HT3_6

#define	ADC_TR3_HT3_7 ADC_AWD3TR_HT3_7

#define	ADC_TR3_HT3_8 ADC_AWD3TR_HT3_8

#define	ADC_TR3_HT3_9 ADC_AWD3TR_HT3_9

#define	ADC_TR3_HT3_10 ADC_AWD3TR_HT3_10

#define	ADC_TR3_HT3_11 ADC_AWD3TR_HT3_11

#define	ADC_DR_DATA_Pos (0U)

#define	ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos)

#define	ADC_DR_DATA ADC_DR_DATA_Msk

#define	ADC_DR_DATA_0 (0x0001UL << ADC_DR_DATA_Pos)

#define	ADC_DR_DATA_1 (0x0002UL << ADC_DR_DATA_Pos)

#define	ADC_DR_DATA_2 (0x0004UL << ADC_DR_DATA_Pos)

#define	ADC_DR_DATA_3 (0x0008UL << ADC_DR_DATA_Pos)

#define	ADC_DR_DATA_4 (0x0010UL << ADC_DR_DATA_Pos)

#define	ADC_DR_DATA_5 (0x0020UL << ADC_DR_DATA_Pos)

#define	ADC_DR_DATA_6 (0x0040UL << ADC_DR_DATA_Pos)

#define	ADC_DR_DATA_7 (0x0080UL << ADC_DR_DATA_Pos)

#define	ADC_DR_DATA_8 (0x0100UL << ADC_DR_DATA_Pos)

#define	ADC_DR_DATA_9 (0x0200UL << ADC_DR_DATA_Pos)

#define	ADC_DR_DATA_10 (0x0400UL << ADC_DR_DATA_Pos)

#define	ADC_DR_DATA_11 (0x0800UL << ADC_DR_DATA_Pos)

#define	ADC_DR_DATA_12 (0x1000UL << ADC_DR_DATA_Pos)

#define	ADC_DR_DATA_13 (0x2000UL << ADC_DR_DATA_Pos)

#define	ADC_DR_DATA_14 (0x4000UL << ADC_DR_DATA_Pos)

#define	ADC_DR_DATA_15 (0x8000UL << ADC_DR_DATA_Pos)

#define	ADC_AWD2CR_AWD2CH_Pos (0U)

#define	ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk

#define	ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD3CR_AWD3CH_Pos (0U)

#define	ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk

#define	ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_CALFACT_CALFACT_Pos (0U)

#define	ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos)

#define	ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk

#define	ADC_CALFACT_CALFACT_0 (0x01UL << ADC_CALFACT_CALFACT_Pos)

#define	ADC_CALFACT_CALFACT_1 (0x02UL << ADC_CALFACT_CALFACT_Pos)

#define	ADC_CALFACT_CALFACT_2 (0x04UL << ADC_CALFACT_CALFACT_Pos)

#define	ADC_CALFACT_CALFACT_3 (0x08UL << ADC_CALFACT_CALFACT_Pos)

#define	ADC_CALFACT_CALFACT_4 (0x10UL << ADC_CALFACT_CALFACT_Pos)

#define	ADC_CALFACT_CALFACT_5 (0x20UL << ADC_CALFACT_CALFACT_Pos)

#define	ADC_CALFACT_CALFACT_6 (0x40UL << ADC_CALFACT_CALFACT_Pos)

#define	ADC_CCR_PRESC_Pos (18U)

#define	ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos)

#define	ADC_CCR_PRESC ADC_CCR_PRESC_Msk

#define	ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos)

#define	ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos)

#define	ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos)

#define	ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos)

#define	ADC_CCR_VREFEN_Pos (22U)

#define	ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos)

#define	ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk

#define	ADC_CCR_TSEN_Pos (23U)

#define	ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos)

#define	ADC_CCR_TSEN ADC_CCR_TSEN_Msk

#define	ADC_CCR_VBATEN_Pos (24U)

#define	ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos)

#define	ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk

#define	ADC_CCR_LFMEN_Pos (25U)

#define	ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos)

#define	ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk

#define	CRC_DR_DR_Pos (0U)

#define	CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos)

#define	CRC_DR_DR CRC_DR_DR_Msk

#define	CRC_IDR_IDR_Pos (0U)

#define	CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)

#define	CRC_IDR_IDR CRC_IDR_IDR_Msk

#define	CRC_CR_RESET_Pos (0U)

#define	CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos)

#define	CRC_CR_RESET CRC_CR_RESET_Msk

#define	CRC_CR_POLYSIZE_Pos (3U)

#define	CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos)

#define	CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk

#define	CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos)

#define	CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos)

#define	CRC_CR_REV_IN_Pos (5U)

#define	CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos)

#define	CRC_CR_REV_IN CRC_CR_REV_IN_Msk

#define	CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos)

#define	CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos)

#define	CRC_CR_REV_OUT_Pos (7U)

#define	CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos)

#define	CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk

#define	CRC_INIT_INIT_Pos (0U)

#define	CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)

#define	CRC_INIT_INIT CRC_INIT_INIT_Msk

#define	CRC_POL_POL_Pos (0U)

#define	CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos)

#define	CRC_POL_POL CRC_POL_POL_Msk

#define	DMA_ISR_GIF1_Pos (0U)

#define	DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos)

#define	DMA_ISR_GIF1 DMA_ISR_GIF1_Msk

#define	DMA_ISR_TCIF1_Pos (1U)

#define	DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos)

#define	DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk

#define	DMA_ISR_HTIF1_Pos (2U)

#define	DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos)

#define	DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk

#define	DMA_ISR_TEIF1_Pos (3U)

#define	DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos)

#define	DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk

#define	DMA_ISR_GIF2_Pos (4U)

#define	DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos)

#define	DMA_ISR_GIF2 DMA_ISR_GIF2_Msk

#define	DMA_ISR_TCIF2_Pos (5U)

#define	DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos)

#define	DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk

#define	DMA_ISR_HTIF2_Pos (6U)

#define	DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos)

#define	DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk

#define	DMA_ISR_TEIF2_Pos (7U)

#define	DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos)

#define	DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk

#define	DMA_ISR_GIF3_Pos (8U)

#define	DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos)

#define	DMA_ISR_GIF3 DMA_ISR_GIF3_Msk

#define	DMA_ISR_TCIF3_Pos (9U)

#define	DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos)

#define	DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk

#define	DMA_ISR_HTIF3_Pos (10U)

#define	DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos)

#define	DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk

#define	DMA_ISR_TEIF3_Pos (11U)

#define	DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos)

#define	DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk

#define	DMA_ISR_GIF4_Pos (12U)

#define	DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos)

#define	DMA_ISR_GIF4 DMA_ISR_GIF4_Msk

#define	DMA_ISR_TCIF4_Pos (13U)

#define	DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos)

#define	DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk

#define	DMA_ISR_HTIF4_Pos (14U)

#define	DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos)

#define	DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk

#define	DMA_ISR_TEIF4_Pos (15U)

#define	DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos)

#define	DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk

#define	DMA_ISR_GIF5_Pos (16U)

#define	DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos)

#define	DMA_ISR_GIF5 DMA_ISR_GIF5_Msk

#define	DMA_ISR_TCIF5_Pos (17U)

#define	DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos)

#define	DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk

#define	DMA_ISR_HTIF5_Pos (18U)

#define	DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos)

#define	DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk

#define	DMA_ISR_TEIF5_Pos (19U)

#define	DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos)

#define	DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk

#define	DMA_ISR_GIF6_Pos (20U)

#define	DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos)

#define	DMA_ISR_GIF6 DMA_ISR_GIF6_Msk

#define	DMA_ISR_TCIF6_Pos (21U)

#define	DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos)

#define	DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk

#define	DMA_ISR_HTIF6_Pos (22U)

#define	DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos)

#define	DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk

#define	DMA_ISR_TEIF6_Pos (23U)

#define	DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos)

#define	DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk

#define	DMA_ISR_GIF7_Pos (24U)

#define	DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos)

#define	DMA_ISR_GIF7 DMA_ISR_GIF7_Msk

#define	DMA_ISR_TCIF7_Pos (25U)

#define	DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos)

#define	DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk

#define	DMA_ISR_HTIF7_Pos (26U)

#define	DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos)

#define	DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk

#define	DMA_ISR_TEIF7_Pos (27U)

#define	DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos)

#define	DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk

#define	DMA_IFCR_CGIF1_Pos (0U)

#define	DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos)

#define	DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk

#define	DMA_IFCR_CTCIF1_Pos (1U)

#define	DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos)

#define	DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk

#define	DMA_IFCR_CHTIF1_Pos (2U)

#define	DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos)

#define	DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk

#define	DMA_IFCR_CTEIF1_Pos (3U)

#define	DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos)

#define	DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk

#define	DMA_IFCR_CGIF2_Pos (4U)

#define	DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos)

#define	DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk

#define	DMA_IFCR_CTCIF2_Pos (5U)

#define	DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos)

#define	DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk

#define	DMA_IFCR_CHTIF2_Pos (6U)

#define	DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos)

#define	DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk

#define	DMA_IFCR_CTEIF2_Pos (7U)

#define	DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos)

#define	DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk

#define	DMA_IFCR_CGIF3_Pos (8U)

#define	DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos)

#define	DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk

#define	DMA_IFCR_CTCIF3_Pos (9U)

#define	DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos)

#define	DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk

#define	DMA_IFCR_CHTIF3_Pos (10U)

#define	DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos)

#define	DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk

#define	DMA_IFCR_CTEIF3_Pos (11U)

#define	DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos)

#define	DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk

#define	DMA_IFCR_CGIF4_Pos (12U)

#define	DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos)

#define	DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk

#define	DMA_IFCR_CTCIF4_Pos (13U)

#define	DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos)

#define	DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk

#define	DMA_IFCR_CHTIF4_Pos (14U)

#define	DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos)

#define	DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk

#define	DMA_IFCR_CTEIF4_Pos (15U)

#define	DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos)

#define	DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk

#define	DMA_IFCR_CGIF5_Pos (16U)

#define	DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos)

#define	DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk

#define	DMA_IFCR_CTCIF5_Pos (17U)

#define	DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos)

#define	DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk

#define	DMA_IFCR_CHTIF5_Pos (18U)

#define	DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos)

#define	DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk

#define	DMA_IFCR_CTEIF5_Pos (19U)

#define	DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos)

#define	DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk

#define	DMA_IFCR_CGIF6_Pos (20U)

#define	DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos)

#define	DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk

#define	DMA_IFCR_CTCIF6_Pos (21U)

#define	DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos)

#define	DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk

#define	DMA_IFCR_CHTIF6_Pos (22U)

#define	DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos)

#define	DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk

#define	DMA_IFCR_CTEIF6_Pos (23U)

#define	DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos)

#define	DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk

#define	DMA_IFCR_CGIF7_Pos (24U)

#define	DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos)

#define	DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk

#define	DMA_IFCR_CTCIF7_Pos (25U)

#define	DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos)

#define	DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk

#define	DMA_IFCR_CHTIF7_Pos (26U)

#define	DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos)

#define	DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk

#define	DMA_IFCR_CTEIF7_Pos (27U)

#define	DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos)

#define	DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk

#define	DMA_CCR_EN_Pos (0U)

#define	DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos)

#define	DMA_CCR_EN DMA_CCR_EN_Msk

#define	DMA_CCR_TCIE_Pos (1U)

#define	DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos)

#define	DMA_CCR_TCIE DMA_CCR_TCIE_Msk

#define	DMA_CCR_HTIE_Pos (2U)

#define	DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos)

#define	DMA_CCR_HTIE DMA_CCR_HTIE_Msk

#define	DMA_CCR_TEIE_Pos (3U)

#define	DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos)

#define	DMA_CCR_TEIE DMA_CCR_TEIE_Msk

#define	DMA_CCR_DIR_Pos (4U)

#define	DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos)

#define	DMA_CCR_DIR DMA_CCR_DIR_Msk

#define	DMA_CCR_CIRC_Pos (5U)

#define	DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos)

#define	DMA_CCR_CIRC DMA_CCR_CIRC_Msk

#define	DMA_CCR_PINC_Pos (6U)

#define	DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos)

#define	DMA_CCR_PINC DMA_CCR_PINC_Msk

#define	DMA_CCR_MINC_Pos (7U)

#define	DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos)

#define	DMA_CCR_MINC DMA_CCR_MINC_Msk

#define	DMA_CCR_PSIZE_Pos (8U)

#define	DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos)

#define	DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk

#define	DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos)

#define	DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos)

#define	DMA_CCR_MSIZE_Pos (10U)

#define	DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos)

#define	DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk

#define	DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos)

#define	DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos)

#define	DMA_CCR_PL_Pos (12U)

#define	DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos)

#define	DMA_CCR_PL DMA_CCR_PL_Msk

#define	DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos)

#define	DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos)

#define	DMA_CCR_MEM2MEM_Pos (14U)

#define	DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos)

#define	DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk

#define	DMA_CNDTR_NDT_Pos (0U)

#define	DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos)

#define	DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk

#define	DMA_CPAR_PA_Pos (0U)

#define	DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)

#define	DMA_CPAR_PA DMA_CPAR_PA_Msk

#define	DMA_CMAR_MA_Pos (0U)

#define	DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)

#define	DMA_CMAR_MA DMA_CMAR_MA_Msk

#define	DMAMUX_CxCR_DMAREQ_ID_Pos (0U)

#define	DMAMUX_CxCR_DMAREQ_ID_Msk (0x3FUL << DMAMUX_CxCR_DMAREQ_ID_Pos)

#define	DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk

#define	DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)

#define	DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)

#define	DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)

#define	DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)

#define	DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)

#define	DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)

#define	DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)

#define	DMAMUX_CxCR_SOIE_Pos (8U)

#define	DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos)

#define	DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk

#define	DMAMUX_CxCR_EGE_Pos (9U)

#define	DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos)

#define	DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk

#define	DMAMUX_CxCR_SE_Pos (16U)

#define	DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos)

#define	DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk

#define	DMAMUX_CxCR_SPOL_Pos (17U)

#define	DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos)

#define	DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk

#define	DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos)

#define	DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos)

#define	DMAMUX_CxCR_NBREQ_Pos (19U)

#define	DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)

#define	DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk

#define	DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos)

#define	DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos)

#define	DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos)

#define	DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos)

#define	DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos)

#define	DMAMUX_CxCR_SYNC_ID_Pos (24U)

#define	DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)

#define	DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk

#define	DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)

#define	DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)

#define	DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)

#define	DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)

#define	DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)

#define	DMAMUX_CSR_SOF0_Pos (0U)

#define	DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos)

#define	DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk

#define	DMAMUX_CSR_SOF1_Pos (1U)

#define	DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos)

#define	DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk

#define	DMAMUX_CSR_SOF2_Pos (2U)

#define	DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos)

#define	DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk

#define	DMAMUX_CSR_SOF3_Pos (3U)

#define	DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos)

#define	DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk

#define	DMAMUX_CSR_SOF4_Pos (4U)

#define	DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos)

#define	DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk

#define	DMAMUX_CSR_SOF5_Pos (5U)

#define	DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos)

#define	DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk

#define	DMAMUX_CSR_SOF6_Pos (6U)

#define	DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos)

#define	DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk

#define	DMAMUX_CFR_CSOF0_Pos (0U)

#define	DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos)

#define	DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk

#define	DMAMUX_CFR_CSOF1_Pos (1U)

#define	DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos)

#define	DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk

#define	DMAMUX_CFR_CSOF2_Pos (2U)

#define	DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos)

#define	DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk

#define	DMAMUX_CFR_CSOF3_Pos (3U)

#define	DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos)

#define	DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk

#define	DMAMUX_CFR_CSOF4_Pos (4U)

#define	DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos)

#define	DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk

#define	DMAMUX_CFR_CSOF5_Pos (5U)

#define	DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos)

#define	DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk

#define	DMAMUX_CFR_CSOF6_Pos (6U)

#define	DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos)

#define	DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk

#define	DMAMUX_RGxCR_SIG_ID_Pos (0U)

#define	DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)

#define	DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk

#define	DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)

#define	DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)

#define	DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)

#define	DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)

#define	DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)

#define	DMAMUX_RGxCR_OIE_Pos (8U)

#define	DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos)

#define	DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk

#define	DMAMUX_RGxCR_GE_Pos (16U)

#define	DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos)

#define	DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk

#define	DMAMUX_RGxCR_GPOL_Pos (17U)

#define	DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos)

#define	DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk

#define	DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos)

#define	DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos)

#define	DMAMUX_RGxCR_GNBREQ_Pos (19U)

#define	DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)

#define	DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk

#define	DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)

#define	DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)

#define	DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)

#define	DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)

#define	DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)

#define	DMAMUX_RGSR_OF0_Pos (0U)

#define	DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos)

#define	DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk

#define	DMAMUX_RGSR_OF1_Pos (1U)

#define	DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos)

#define	DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk

#define	DMAMUX_RGSR_OF2_Pos (2U)

#define	DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos)

#define	DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk

#define	DMAMUX_RGSR_OF3_Pos (3U)

#define	DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos)

#define	DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk

#define	DMAMUX_RGCFR_COF0_Pos (0U)

#define	DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos)

#define	DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk

#define	DMAMUX_RGCFR_COF1_Pos (1U)

#define	DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos)

#define	DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk

#define	DMAMUX_RGCFR_COF2_Pos (2U)

#define	DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos)

#define	DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk

#define	DMAMUX_RGCFR_COF3_Pos (3U)

#define	DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos)

#define	DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk

#define	EXTI_RTSR1_RT0_Pos (0U)

#define	EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos)

#define	EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk

#define	EXTI_RTSR1_RT1_Pos (1U)

#define	EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos)

#define	EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk

#define	EXTI_RTSR1_RT2_Pos (2U)

#define	EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos)

#define	EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk

#define	EXTI_RTSR1_RT3_Pos (3U)

#define	EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos)

#define	EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk

#define	EXTI_RTSR1_RT4_Pos (4U)

#define	EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos)

#define	EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk

#define	EXTI_RTSR1_RT5_Pos (5U)

#define	EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos)

#define	EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk

#define	EXTI_RTSR1_RT6_Pos (6U)

#define	EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos)

#define	EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk

#define	EXTI_RTSR1_RT7_Pos (7U)

#define	EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos)

#define	EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk

#define	EXTI_RTSR1_RT8_Pos (8U)

#define	EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos)

#define	EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk

#define	EXTI_RTSR1_RT9_Pos (9U)

#define	EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos)

#define	EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk

#define	EXTI_RTSR1_RT10_Pos (10U)

#define	EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos)

#define	EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk

#define	EXTI_RTSR1_RT11_Pos (11U)

#define	EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos)

#define	EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk

#define	EXTI_RTSR1_RT12_Pos (12U)

#define	EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos)

#define	EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk

#define	EXTI_RTSR1_RT13_Pos (13U)

#define	EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos)

#define	EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk

#define	EXTI_RTSR1_RT14_Pos (14U)

#define	EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos)

#define	EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk

#define	EXTI_RTSR1_RT15_Pos (15U)

#define	EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos)

#define	EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk

#define	EXTI_FTSR1_FT0_Pos (0U)

#define	EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos)

#define	EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk

#define	EXTI_FTSR1_FT1_Pos (1U)

#define	EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos)

#define	EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk

#define	EXTI_FTSR1_FT2_Pos (2U)

#define	EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos)

#define	EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk

#define	EXTI_FTSR1_FT3_Pos (3U)

#define	EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos)

#define	EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk

#define	EXTI_FTSR1_FT4_Pos (4U)

#define	EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos)

#define	EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk

#define	EXTI_FTSR1_FT5_Pos (5U)

#define	EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos)

#define	EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk

#define	EXTI_FTSR1_FT6_Pos (6U)

#define	EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos)

#define	EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk

#define	EXTI_FTSR1_FT7_Pos (7U)

#define	EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos)

#define	EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk

#define	EXTI_FTSR1_FT8_Pos (8U)

#define	EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos)

#define	EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk

#define	EXTI_FTSR1_FT9_Pos (9U)

#define	EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos)

#define	EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk

#define	EXTI_FTSR1_FT10_Pos (10U)

#define	EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos)

#define	EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk

#define	EXTI_FTSR1_FT11_Pos (11U)

#define	EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos)

#define	EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk

#define	EXTI_FTSR1_FT12_Pos (12U)

#define	EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos)

#define	EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk

#define	EXTI_FTSR1_FT13_Pos (13U)

#define	EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos)

#define	EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk

#define	EXTI_FTSR1_FT14_Pos (14U)

#define	EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos)

#define	EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk

#define	EXTI_FTSR1_FT15_Pos (15U)

#define	EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos)

#define	EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk

#define	EXTI_SWIER1_SWI0_Pos (0U)

#define	EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos)

#define	EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk

#define	EXTI_SWIER1_SWI1_Pos (1U)

#define	EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos)

#define	EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk

#define	EXTI_SWIER1_SWI2_Pos (2U)

#define	EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos)

#define	EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk

#define	EXTI_SWIER1_SWI3_Pos (3U)

#define	EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos)

#define	EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk

#define	EXTI_SWIER1_SWI4_Pos (4U)

#define	EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos)

#define	EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk

#define	EXTI_SWIER1_SWI5_Pos (5U)

#define	EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos)

#define	EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk

#define	EXTI_SWIER1_SWI6_Pos (6U)

#define	EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos)

#define	EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk

#define	EXTI_SWIER1_SWI7_Pos (7U)

#define	EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos)

#define	EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk

#define	EXTI_SWIER1_SWI8_Pos (8U)

#define	EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos)

#define	EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk

#define	EXTI_SWIER1_SWI9_Pos (9U)

#define	EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos)

#define	EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk

#define	EXTI_SWIER1_SWI10_Pos (10U)

#define	EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos)

#define	EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk

#define	EXTI_SWIER1_SWI11_Pos (11U)

#define	EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos)

#define	EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk

#define	EXTI_SWIER1_SWI12_Pos (12U)

#define	EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos)

#define	EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk

#define	EXTI_SWIER1_SWI13_Pos (13U)

#define	EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos)

#define	EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk

#define	EXTI_SWIER1_SWI14_Pos (14U)

#define	EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos)

#define	EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk

#define	EXTI_SWIER1_SWI15_Pos (15U)

#define	EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos)

#define	EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk

#define	EXTI_RPR1_RPIF0_Pos (0U)

#define	EXTI_RPR1_RPIF0_Msk (0x1UL << EXTI_RPR1_RPIF0_Pos)

#define	EXTI_RPR1_RPIF0 EXTI_RPR1_RPIF0_Msk

#define	EXTI_RPR1_RPIF1_Pos (1U)

#define	EXTI_RPR1_RPIF1_Msk (0x1UL << EXTI_RPR1_RPIF1_Pos)

#define	EXTI_RPR1_RPIF1 EXTI_RPR1_RPIF1_Msk

#define	EXTI_RPR1_RPIF2_Pos (2U)

#define	EXTI_RPR1_RPIF2_Msk (0x1UL << EXTI_RPR1_RPIF2_Pos)

#define	EXTI_RPR1_RPIF2 EXTI_RPR1_RPIF2_Msk

#define	EXTI_RPR1_RPIF3_Pos (3U)

#define	EXTI_RPR1_RPIF3_Msk (0x1UL << EXTI_RPR1_RPIF3_Pos)

#define	EXTI_RPR1_RPIF3 EXTI_RPR1_RPIF3_Msk

#define	EXTI_RPR1_RPIF4_Pos (4U)

#define	EXTI_RPR1_RPIF4_Msk (0x1UL << EXTI_RPR1_RPIF4_Pos)

#define	EXTI_RPR1_RPIF4 EXTI_RPR1_RPIF4_Msk

#define	EXTI_RPR1_RPIF5_Pos (5U)

#define	EXTI_RPR1_RPIF5_Msk (0x1UL << EXTI_RPR1_RPIF5_Pos)

#define	EXTI_RPR1_RPIF5 EXTI_RPR1_RPIF5_Msk

#define	EXTI_RPR1_RPIF6_Pos (6U)

#define	EXTI_RPR1_RPIF6_Msk (0x1UL << EXTI_RPR1_RPIF6_Pos)

#define	EXTI_RPR1_RPIF6 EXTI_RPR1_RPIF6_Msk

#define	EXTI_RPR1_RPIF7_Pos (7U)

#define	EXTI_RPR1_RPIF7_Msk (0x1UL << EXTI_RPR1_RPIF7_Pos)

#define	EXTI_RPR1_RPIF7 EXTI_RPR1_RPIF7_Msk

#define	EXTI_RPR1_RPIF8_Pos (8U)

#define	EXTI_RPR1_RPIF8_Msk (0x1UL << EXTI_RPR1_RPIF8_Pos)

#define	EXTI_RPR1_RPIF8 EXTI_RPR1_RPIF8_Msk

#define	EXTI_RPR1_RPIF9_Pos (9U)

#define	EXTI_RPR1_RPIF9_Msk (0x1UL << EXTI_RPR1_RPIF9_Pos)

#define	EXTI_RPR1_RPIF9 EXTI_RPR1_RPIF9_Msk

#define	EXTI_RPR1_RPIF10_Pos (10U)

#define	EXTI_RPR1_RPIF10_Msk (0x1UL << EXTI_RPR1_RPIF10_Pos)

#define	EXTI_RPR1_RPIF10 EXTI_RPR1_RPIF10_Msk

#define	EXTI_RPR1_RPIF11_Pos (11U)

#define	EXTI_RPR1_RPIF11_Msk (0x1UL << EXTI_RPR1_RPIF11_Pos)

#define	EXTI_RPR1_RPIF11 EXTI_RPR1_RPIF11_Msk

#define	EXTI_RPR1_RPIF12_Pos (12U)

#define	EXTI_RPR1_RPIF12_Msk (0x1UL << EXTI_RPR1_RPIF12_Pos)

#define	EXTI_RPR1_RPIF12 EXTI_RPR1_RPIF12_Msk

#define	EXTI_RPR1_RPIF13_Pos (13U)

#define	EXTI_RPR1_RPIF13_Msk (0x1UL << EXTI_RPR1_RPIF13_Pos)

#define	EXTI_RPR1_RPIF13 EXTI_RPR1_RPIF13_Msk

#define	EXTI_RPR1_RPIF14_Pos (14U)

#define	EXTI_RPR1_RPIF14_Msk (0x1UL << EXTI_RPR1_RPIF14_Pos)

#define	EXTI_RPR1_RPIF14 EXTI_RPR1_RPIF14_Msk

#define	EXTI_RPR1_RPIF15_Pos (15U)

#define	EXTI_RPR1_RPIF15_Msk (0x1UL << EXTI_RPR1_RPIF15_Pos)

#define	EXTI_RPR1_RPIF15 EXTI_RPR1_RPIF15_Msk

#define	EXTI_FPR1_FPIF0_Pos (0U)

#define	EXTI_FPR1_FPIF0_Msk (0x1UL << EXTI_FPR1_FPIF0_Pos)

#define	EXTI_FPR1_FPIF0 EXTI_FPR1_FPIF0_Msk

#define	EXTI_FPR1_FPIF1_Pos (1U)

#define	EXTI_FPR1_FPIF1_Msk (0x1UL << EXTI_FPR1_FPIF1_Pos)

#define	EXTI_FPR1_FPIF1 EXTI_FPR1_FPIF1_Msk

#define	EXTI_FPR1_FPIF2_Pos (2U)

#define	EXTI_FPR1_FPIF2_Msk (0x1UL << EXTI_FPR1_FPIF2_Pos)

#define	EXTI_FPR1_FPIF2 EXTI_FPR1_FPIF2_Msk

#define	EXTI_FPR1_FPIF3_Pos (3U)

#define	EXTI_FPR1_FPIF3_Msk (0x1UL << EXTI_FPR1_FPIF3_Pos)

#define	EXTI_FPR1_FPIF3 EXTI_FPR1_FPIF3_Msk

#define	EXTI_FPR1_FPIF4_Pos (4U)

#define	EXTI_FPR1_FPIF4_Msk (0x1UL << EXTI_FPR1_FPIF4_Pos)

#define	EXTI_FPR1_FPIF4 EXTI_FPR1_FPIF4_Msk

#define	EXTI_FPR1_FPIF5_Pos (5U)

#define	EXTI_FPR1_FPIF5_Msk (0x1UL << EXTI_FPR1_FPIF5_Pos)

#define	EXTI_FPR1_FPIF5 EXTI_FPR1_FPIF5_Msk

#define	EXTI_FPR1_FPIF6_Pos (6U)

#define	EXTI_FPR1_FPIF6_Msk (0x1UL << EXTI_FPR1_FPIF6_Pos)

#define	EXTI_FPR1_FPIF6 EXTI_FPR1_FPIF6_Msk

#define	EXTI_FPR1_FPIF7_Pos (7U)

#define	EXTI_FPR1_FPIF7_Msk (0x1UL << EXTI_FPR1_FPIF7_Pos)

#define	EXTI_FPR1_FPIF7 EXTI_FPR1_FPIF7_Msk

#define	EXTI_FPR1_FPIF8_Pos (8U)

#define	EXTI_FPR1_FPIF8_Msk (0x1UL << EXTI_FPR1_FPIF8_Pos)

#define	EXTI_FPR1_FPIF8 EXTI_FPR1_FPIF8_Msk

#define	EXTI_FPR1_FPIF9_Pos (9U)

#define	EXTI_FPR1_FPIF9_Msk (0x1UL << EXTI_FPR1_FPIF9_Pos)

#define	EXTI_FPR1_FPIF9 EXTI_FPR1_FPIF9_Msk

#define	EXTI_FPR1_FPIF10_Pos (10U)

#define	EXTI_FPR1_FPIF10_Msk (0x1UL << EXTI_FPR1_FPIF10_Pos)

#define	EXTI_FPR1_FPIF10 EXTI_FPR1_FPIF10_Msk

#define	EXTI_FPR1_FPIF11_Pos (11U)

#define	EXTI_FPR1_FPIF11_Msk (0x1UL << EXTI_FPR1_FPIF11_Pos)

#define	EXTI_FPR1_FPIF11 EXTI_FPR1_FPIF11_Msk

#define	EXTI_FPR1_FPIF12_Pos (12U)

#define	EXTI_FPR1_FPIF12_Msk (0x1UL << EXTI_FPR1_FPIF12_Pos)

#define	EXTI_FPR1_FPIF12 EXTI_FPR1_FPIF12_Msk

#define	EXTI_FPR1_FPIF13_Pos (13U)

#define	EXTI_FPR1_FPIF13_Msk (0x1UL << EXTI_FPR1_FPIF13_Pos)

#define	EXTI_FPR1_FPIF13 EXTI_FPR1_FPIF13_Msk

#define	EXTI_FPR1_FPIF14_Pos (14U)

#define	EXTI_FPR1_FPIF14_Msk (0x1UL << EXTI_FPR1_FPIF14_Pos)

#define	EXTI_FPR1_FPIF14 EXTI_FPR1_FPIF14_Msk

#define	EXTI_FPR1_FPIF15_Pos (15U)

#define	EXTI_FPR1_FPIF15_Msk (0x1UL << EXTI_FPR1_FPIF15_Pos)

#define	EXTI_FPR1_FPIF15 EXTI_FPR1_FPIF15_Msk

#define	EXTI_EXTICR1_EXTI0_Pos (0U)

#define	EXTI_EXTICR1_EXTI0_Msk (0x7UL << EXTI_EXTICR1_EXTI0_Pos)

#define	EXTI_EXTICR1_EXTI0 EXTI_EXTICR1_EXTI0_Msk

#define	EXTI_EXTICR1_EXTI0_0 (0x1UL << EXTI_EXTICR1_EXTI0_Pos)

#define	EXTI_EXTICR1_EXTI0_1 (0x2UL << EXTI_EXTICR1_EXTI0_Pos)

#define	EXTI_EXTICR1_EXTI0_2 (0x4UL << EXTI_EXTICR1_EXTI0_Pos)

#define	EXTI_EXTICR1_EXTI1_Pos (8U)

#define	EXTI_EXTICR1_EXTI1_Msk (0x7UL << EXTI_EXTICR1_EXTI1_Pos)

#define	EXTI_EXTICR1_EXTI1 EXTI_EXTICR1_EXTI1_Msk

#define	EXTI_EXTICR1_EXTI1_0 (0x1UL << EXTI_EXTICR1_EXTI1_Pos)

#define	EXTI_EXTICR1_EXTI1_1 (0x2UL << EXTI_EXTICR1_EXTI1_Pos)

#define	EXTI_EXTICR1_EXTI1_2 (0x4UL << EXTI_EXTICR1_EXTI1_Pos)

#define	EXTI_EXTICR1_EXTI2_Pos (16U)

#define	EXTI_EXTICR1_EXTI2_Msk (0x7UL << EXTI_EXTICR1_EXTI2_Pos)

#define	EXTI_EXTICR1_EXTI2 EXTI_EXTICR1_EXTI2_Msk

#define	EXTI_EXTICR1_EXTI2_0 (0x1UL << EXTI_EXTICR1_EXTI2_Pos)

#define	EXTI_EXTICR1_EXTI2_1 (0x2UL << EXTI_EXTICR1_EXTI2_Pos)

#define	EXTI_EXTICR1_EXTI2_2 (0x4UL << EXTI_EXTICR1_EXTI2_Pos)

#define	EXTI_EXTICR1_EXTI3_Pos (24U)

#define	EXTI_EXTICR1_EXTI3_Msk (0x7UL << EXTI_EXTICR1_EXTI3_Pos)

#define	EXTI_EXTICR1_EXTI3 EXTI_EXTICR1_EXTI3_Msk

#define	EXTI_EXTICR1_EXTI3_0 (0x1UL << EXTI_EXTICR1_EXTI3_Pos)

#define	EXTI_EXTICR1_EXTI3_1 (0x2UL << EXTI_EXTICR1_EXTI3_Pos)

#define	EXTI_EXTICR1_EXTI3_2 (0x4UL << EXTI_EXTICR1_EXTI3_Pos)

#define	EXTI_EXTICR2_EXTI4_Pos (0U)

#define	EXTI_EXTICR2_EXTI4_Msk (0x7UL << EXTI_EXTICR2_EXTI4_Pos)

#define	EXTI_EXTICR2_EXTI4 EXTI_EXTICR2_EXTI4_Msk

#define	EXTI_EXTICR2_EXTI4_0 (0x1UL << EXTI_EXTICR2_EXTI4_Pos)

#define	EXTI_EXTICR2_EXTI4_1 (0x2UL << EXTI_EXTICR2_EXTI4_Pos)

#define	EXTI_EXTICR2_EXTI4_2 (0x4UL << EXTI_EXTICR2_EXTI4_Pos)

#define	EXTI_EXTICR2_EXTI5_Pos (8U)

#define	EXTI_EXTICR2_EXTI5_Msk (0x7UL << EXTI_EXTICR2_EXTI5_Pos)

#define	EXTI_EXTICR2_EXTI5 EXTI_EXTICR2_EXTI5_Msk

#define	EXTI_EXTICR2_EXTI5_0 (0x1UL << EXTI_EXTICR2_EXTI5_Pos)

#define	EXTI_EXTICR2_EXTI5_1 (0x2UL << EXTI_EXTICR2_EXTI5_Pos)

#define	EXTI_EXTICR2_EXTI5_2 (0x4UL << EXTI_EXTICR2_EXTI5_Pos)

#define	EXTI_EXTICR2_EXTI6_Pos (16U)

#define	EXTI_EXTICR2_EXTI6_Msk (0x7UL << EXTI_EXTICR2_EXTI6_Pos)

#define	EXTI_EXTICR2_EXTI6 EXTI_EXTICR2_EXTI6_Msk

#define	EXTI_EXTICR2_EXTI6_0 (0x1UL << EXTI_EXTICR2_EXTI6_Pos)

#define	EXTI_EXTICR2_EXTI6_1 (0x2UL << EXTI_EXTICR2_EXTI6_Pos)

#define	EXTI_EXTICR2_EXTI6_2 (0x4UL << EXTI_EXTICR2_EXTI6_Pos)

#define	EXTI_EXTICR2_EXTI7_Pos (24U)

#define	EXTI_EXTICR2_EXTI7_Msk (0x7UL << EXTI_EXTICR2_EXTI7_Pos)

#define	EXTI_EXTICR2_EXTI7 EXTI_EXTICR2_EXTI7_Msk

#define	EXTI_EXTICR2_EXTI7_0 (0x1UL << EXTI_EXTICR2_EXTI7_Pos)

#define	EXTI_EXTICR2_EXTI7_1 (0x2UL << EXTI_EXTICR2_EXTI7_Pos)

#define	EXTI_EXTICR2_EXTI7_2 (0x4UL << EXTI_EXTICR2_EXTI7_Pos)

#define	EXTI_EXTICR3_EXTI8_Pos (0U)

#define	EXTI_EXTICR3_EXTI8_Msk (0x7UL << EXTI_EXTICR3_EXTI8_Pos)

#define	EXTI_EXTICR3_EXTI8 EXTI_EXTICR3_EXTI8_Msk

#define	EXTI_EXTICR3_EXTI8_0 (0x1UL << EXTI_EXTICR3_EXTI8_Pos)

#define	EXTI_EXTICR3_EXTI8_1 (0x2UL << EXTI_EXTICR3_EXTI8_Pos)

#define	EXTI_EXTICR3_EXTI8_2 (0x4UL << EXTI_EXTICR3_EXTI8_Pos)

#define	EXTI_EXTICR3_EXTI9_Pos (8U)

#define	EXTI_EXTICR3_EXTI9_Msk (0x7UL << EXTI_EXTICR3_EXTI9_Pos)

#define	EXTI_EXTICR3_EXTI9 EXTI_EXTICR3_EXTI9_Msk

#define	EXTI_EXTICR3_EXTI9_0 (0x1UL << EXTI_EXTICR3_EXTI9_Pos)

#define	EXTI_EXTICR3_EXTI9_1 (0x2UL << EXTI_EXTICR3_EXTI9_Pos)

#define	EXTI_EXTICR3_EXTI9_2 (0x4UL << EXTI_EXTICR3_EXTI9_Pos)

#define	EXTI_EXTICR3_EXTI10_Pos (16U)

#define	EXTI_EXTICR3_EXTI10_Msk (0x7UL << EXTI_EXTICR3_EXTI10_Pos)

#define	EXTI_EXTICR3_EXTI10 EXTI_EXTICR3_EXTI10_Msk

#define	EXTI_EXTICR3_EXTI10_0 (0x1UL << EXTI_EXTICR3_EXTI10_Pos)

#define	EXTI_EXTICR3_EXTI10_1 (0x2UL << EXTI_EXTICR3_EXTI10_Pos)

#define	EXTI_EXTICR3_EXTI10_2 (0x4UL << EXTI_EXTICR3_EXTI10_Pos)

#define	EXTI_EXTICR3_EXTI11_Pos (24U)

#define	EXTI_EXTICR3_EXTI11_Msk (0x7UL << EXTI_EXTICR3_EXTI11_Pos)

#define	EXTI_EXTICR3_EXTI11 EXTI_EXTICR3_EXTI11_Msk

#define	EXTI_EXTICR3_EXTI11_0 (0x1UL << EXTI_EXTICR3_EXTI11_Pos)

#define	EXTI_EXTICR3_EXTI11_1 (0x2UL << EXTI_EXTICR3_EXTI11_Pos)

#define	EXTI_EXTICR3_EXTI11_2 (0x4UL << EXTI_EXTICR3_EXTI11_Pos)

#define	EXTI_EXTICR4_EXTI12_Pos (0U)

#define	EXTI_EXTICR4_EXTI12_Msk (0x7UL << EXTI_EXTICR4_EXTI12_Pos)

#define	EXTI_EXTICR4_EXTI12 EXTI_EXTICR4_EXTI12_Msk

#define	EXTI_EXTICR4_EXTI12_0 (0x1UL << EXTI_EXTICR4_EXTI12_Pos)

#define	EXTI_EXTICR4_EXTI12_1 (0x2UL << EXTI_EXTICR4_EXTI12_Pos)

#define	EXTI_EXTICR4_EXTI12_2 (0x4UL << EXTI_EXTICR4_EXTI12_Pos)

#define	EXTI_EXTICR4_EXTI13_Pos (8U)

#define	EXTI_EXTICR4_EXTI13_Msk (0x7UL << EXTI_EXTICR4_EXTI13_Pos)

#define	EXTI_EXTICR4_EXTI13 EXTI_EXTICR4_EXTI13_Msk

#define	EXTI_EXTICR4_EXTI13_0 (0x1UL << EXTI_EXTICR4_EXTI13_Pos)

#define	EXTI_EXTICR4_EXTI13_1 (0x2UL << EXTI_EXTICR4_EXTI13_Pos)

#define	EXTI_EXTICR4_EXTI13_2 (0x4UL << EXTI_EXTICR4_EXTI13_Pos)

#define	EXTI_EXTICR4_EXTI14_Pos (16U)

#define	EXTI_EXTICR4_EXTI14_Msk (0x7UL << EXTI_EXTICR4_EXTI14_Pos)

#define	EXTI_EXTICR4_EXTI14 EXTI_EXTICR4_EXTI14_Msk

#define	EXTI_EXTICR4_EXTI14_0 (0x1UL << EXTI_EXTICR4_EXTI14_Pos)

#define	EXTI_EXTICR4_EXTI14_1 (0x2UL << EXTI_EXTICR4_EXTI14_Pos)

#define	EXTI_EXTICR4_EXTI14_2 (0x4UL << EXTI_EXTICR4_EXTI14_Pos)

#define	EXTI_EXTICR4_EXTI15_Pos (24U)

#define	EXTI_EXTICR4_EXTI15_Msk (0x7UL << EXTI_EXTICR4_EXTI15_Pos)

#define	EXTI_EXTICR4_EXTI15 EXTI_EXTICR4_EXTI15_Msk

#define	EXTI_EXTICR4_EXTI15_0 (0x1UL << EXTI_EXTICR4_EXTI15_Pos)

#define	EXTI_EXTICR4_EXTI15_1 (0x2UL << EXTI_EXTICR4_EXTI15_Pos)

#define	EXTI_EXTICR4_EXTI15_2 (0x4UL << EXTI_EXTICR4_EXTI15_Pos)

#define	EXTI_IMR1_IM0_Pos (0U)

#define	EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos)

#define	EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk

#define	EXTI_IMR1_IM1_Pos (1U)

#define	EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos)

#define	EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk

#define	EXTI_IMR1_IM2_Pos (2U)

#define	EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos)

#define	EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk

#define	EXTI_IMR1_IM3_Pos (3U)

#define	EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos)

#define	EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk

#define	EXTI_IMR1_IM4_Pos (4U)

#define	EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos)

#define	EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk

#define	EXTI_IMR1_IM5_Pos (5U)

#define	EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos)

#define	EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk

#define	EXTI_IMR1_IM6_Pos (6U)

#define	EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos)

#define	EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk

#define	EXTI_IMR1_IM7_Pos (7U)

#define	EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos)

#define	EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk

#define	EXTI_IMR1_IM8_Pos (8U)

#define	EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos)

#define	EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk

#define	EXTI_IMR1_IM9_Pos (9U)

#define	EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos)

#define	EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk

#define	EXTI_IMR1_IM10_Pos (10U)

#define	EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos)

#define	EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk

#define	EXTI_IMR1_IM11_Pos (11U)

#define	EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos)

#define	EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk

#define	EXTI_IMR1_IM12_Pos (12U)

#define	EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos)

#define	EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk

#define	EXTI_IMR1_IM13_Pos (13U)

#define	EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos)

#define	EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk

#define	EXTI_IMR1_IM14_Pos (14U)

#define	EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos)

#define	EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk

#define	EXTI_IMR1_IM15_Pos (15U)

#define	EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos)

#define	EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk

#define	EXTI_IMR1_IM19_Pos (19U)

#define	EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos)

#define	EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk

#define	EXTI_IMR1_IM21_Pos (21U)

#define	EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos)

#define	EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk

#define	EXTI_IMR1_IM23_Pos (23U)

#define	EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos)

#define	EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk

#define	EXTI_IMR1_IM25_Pos (25U)

#define	EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos)

#define	EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk

#define	EXTI_IMR1_IM31_Pos (31U)

#define	EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos)

#define	EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk

#define	EXTI_IMR1_IM_Pos (0U)

#define	EXTI_IMR1_IM_Msk (0x82A8FFFFUL << EXTI_IMR1_IM_Pos)

#define	EXTI_IMR1_IM EXTI_IMR1_IM_Msk

#define	EXTI_EMR1_EM0_Pos (0U)

#define	EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos)

#define	EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk

#define	EXTI_EMR1_EM1_Pos (1U)

#define	EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos)

#define	EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk

#define	EXTI_EMR1_EM2_Pos (2U)

#define	EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos)

#define	EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk

#define	EXTI_EMR1_EM3_Pos (3U)

#define	EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos)

#define	EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk

#define	EXTI_EMR1_EM4_Pos (4U)

#define	EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos)

#define	EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk

#define	EXTI_EMR1_EM5_Pos (5U)

#define	EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos)

#define	EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk

#define	EXTI_EMR1_EM6_Pos (6U)

#define	EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos)

#define	EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk

#define	EXTI_EMR1_EM7_Pos (7U)

#define	EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos)

#define	EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk

#define	EXTI_EMR1_EM8_Pos (8U)

#define	EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos)

#define	EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk

#define	EXTI_EMR1_EM9_Pos (9U)

#define	EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos)

#define	EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk

#define	EXTI_EMR1_EM10_Pos (10U)

#define	EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos)

#define	EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk

#define	EXTI_EMR1_EM11_Pos (11U)

#define	EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos)

#define	EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk

#define	EXTI_EMR1_EM12_Pos (12U)

#define	EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos)

#define	EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk

#define	EXTI_EMR1_EM13_Pos (13U)

#define	EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos)

#define	EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk

#define	EXTI_EMR1_EM14_Pos (14U)

#define	EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos)

#define	EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk

#define	EXTI_EMR1_EM15_Pos (15U)

#define	EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos)

#define	EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk

#define	EXTI_EMR1_EM19_Pos (19U)

#define	EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos)

#define	EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk

#define	EXTI_EMR1_EM21_Pos (21U)

#define	EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos)

#define	EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk

#define	EXTI_EMR1_EM23_Pos (23U)

#define	EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos)

#define	EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk

#define	EXTI_EMR1_EM25_Pos (25U)

#define	EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos)

#define	EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk

#define	EXTI_EMR1_EM31_Pos (31U)

#define	EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos)

#define	EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk

#define	FLASH_ACR_LATENCY_Pos (0U)

#define	FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos)

#define	FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk

#define	FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos)

#define	FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos)

#define	FLASH_ACR_LATENCY_2 (0x4UL << FLASH_ACR_LATENCY_Pos)

#define	FLASH_ACR_PRFTEN_Pos (8U)

#define	FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos)

#define	FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk

#define	FLASH_ACR_ICEN_Pos (9U)

#define	FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos)

#define	FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk

#define	FLASH_ACR_ICRST_Pos (11U)

#define	FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos)

#define	FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk

#define	FLASH_ACR_PROGEMPTY_Pos (16U)

#define	FLASH_ACR_PROGEMPTY_Msk (0x1UL << FLASH_ACR_PROGEMPTY_Pos)

#define	FLASH_ACR_PROGEMPTY FLASH_ACR_PROGEMPTY_Msk

#define	FLASH_SR_EOP_Pos (0U)

#define	FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos)

#define	FLASH_SR_EOP FLASH_SR_EOP_Msk

#define	FLASH_SR_OPERR_Pos (1U)

#define	FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos)

#define	FLASH_SR_OPERR FLASH_SR_OPERR_Msk

#define	FLASH_SR_PROGERR_Pos (3U)

#define	FLASH_SR_PROGERR_Msk (0x1UL << FLASH_SR_PROGERR_Pos)

#define	FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk

#define	FLASH_SR_WRPERR_Pos (4U)

#define	FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos)

#define	FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk

#define	FLASH_SR_PGAERR_Pos (5U)

#define	FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos)

#define	FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk

#define	FLASH_SR_SIZERR_Pos (6U)

#define	FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos)

#define	FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk

#define	FLASH_SR_PGSERR_Pos (7U)

#define	FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos)

#define	FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk

#define	FLASH_SR_MISERR_Pos (8U)

#define	FLASH_SR_MISERR_Msk (0x1UL << FLASH_SR_MISERR_Pos)

#define	FLASH_SR_MISERR FLASH_SR_MISERR_Msk

#define	FLASH_SR_FASTERR_Pos (9U)

#define	FLASH_SR_FASTERR_Msk (0x1UL << FLASH_SR_FASTERR_Pos)

#define	FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk

#define	FLASH_SR_OPTVERR_Pos (15U)

#define	FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos)

#define	FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk

#define	FLASH_SR_BSY1_Pos (16U)

#define	FLASH_SR_BSY1_Msk (0x1UL << FLASH_SR_BSY1_Pos)

#define	FLASH_SR_BSY1 FLASH_SR_BSY1_Msk

#define	FLASH_SR_CFGBSY_Pos (18U)

#define	FLASH_SR_CFGBSY_Msk (0x1UL << FLASH_SR_CFGBSY_Pos)

#define	FLASH_SR_CFGBSY FLASH_SR_CFGBSY_Msk

#define	FLASH_CR_PG_Pos (0U)

#define	FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos)

#define	FLASH_CR_PG FLASH_CR_PG_Msk

#define	FLASH_CR_PER_Pos (1U)

#define	FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos)

#define	FLASH_CR_PER FLASH_CR_PER_Msk

#define	FLASH_CR_MER1_Pos (2U)

#define	FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos)

#define	FLASH_CR_MER1 FLASH_CR_MER1_Msk

#define	FLASH_CR_PNB_Pos (3U)

#define	FLASH_CR_PNB_Msk (0x3FFUL << FLASH_CR_PNB_Pos)

#define	FLASH_CR_PNB FLASH_CR_PNB_Msk

#define	FLASH_CR_STRT_Pos (16U)

#define	FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos)

#define	FLASH_CR_STRT FLASH_CR_STRT_Msk

#define	FLASH_CR_OPTSTRT_Pos (17U)

#define	FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos)

#define	FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk

#define	FLASH_CR_FSTPG_Pos (18U)

#define	FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos)

#define	FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk

#define	FLASH_CR_EOPIE_Pos (24U)

#define	FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos)

#define	FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk

#define	FLASH_CR_ERRIE_Pos (25U)

#define	FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos)

#define	FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk

#define	FLASH_CR_OBL_LAUNCH_Pos (27U)

#define	FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos)

#define	FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk

#define	FLASH_CR_OPTLOCK_Pos (30U)

#define	FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos)

#define	FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk

#define	FLASH_CR_LOCK_Pos (31U)

#define	FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos)

#define	FLASH_CR_LOCK FLASH_CR_LOCK_Msk

#define	FLASH_ECCR_ADDR_ECC_Pos (0U)

#define	FLASH_ECCR_ADDR_ECC_Msk (0x3FFFUL << FLASH_ECCR_ADDR_ECC_Pos)

#define	FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk

#define	FLASH_ECCR_SYSF_ECC_Pos (20U)

#define	FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos)

#define	FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk

#define	FLASH_ECCR_ECCCIE_Pos (24U)

#define	FLASH_ECCR_ECCCIE_Msk (0x1UL << FLASH_ECCR_ECCCIE_Pos)

#define	FLASH_ECCR_ECCCIE FLASH_ECCR_ECCCIE_Msk

#define	FLASH_ECCR_ECCC_Pos (30U)

#define	FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos)

#define	FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk

#define	FLASH_ECCR_ECCD_Pos (31U)

#define	FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos)

#define	FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk

#define	FLASH_OPTR_RDP_Pos (0U)

#define	FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos)

#define	FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk

#define	FLASH_OPTR_nRST_STOP_Pos (13U)

#define	FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos)

#define	FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk

#define	FLASH_OPTR_nRST_STDBY_Pos (14U)

#define	FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos)

#define	FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk

#define	FLASH_OPTR_IWDG_SW_Pos (16U)

#define	FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos)

#define	FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk

#define	FLASH_OPTR_IWDG_STOP_Pos (17U)

#define	FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos)

#define	FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk

#define	FLASH_OPTR_IWDG_STDBY_Pos (18U)

#define	FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos)

#define	FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk

#define	FLASH_OPTR_WWDG_SW_Pos (19U)

#define	FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos)

#define	FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk

#define	FLASH_OPTR_RAM_PARITY_CHECK_Pos (22U)

#define	FLASH_OPTR_RAM_PARITY_CHECK_Msk (0x1UL << FLASH_OPTR_RAM_PARITY_CHECK_Pos)

#define	FLASH_OPTR_RAM_PARITY_CHECK FLASH_OPTR_RAM_PARITY_CHECK_Msk

#define	FLASH_OPTR_nBOOT_SEL_Pos (24U)

#define	FLASH_OPTR_nBOOT_SEL_Msk (0x1UL << FLASH_OPTR_nBOOT_SEL_Pos)

#define	FLASH_OPTR_nBOOT_SEL FLASH_OPTR_nBOOT_SEL_Msk

#define	FLASH_OPTR_nBOOT1_Pos (25U)

#define	FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos)

#define	FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk

#define	FLASH_OPTR_nBOOT0_Pos (26U)

#define	FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos)

#define	FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk

#define	FLASH_WRP1AR_WRP1A_STRT_Pos (0U)

#define	FLASH_WRP1AR_WRP1A_STRT_Msk (0x1FUL << FLASH_WRP1AR_WRP1A_STRT_Pos)

#define	FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk

#define	FLASH_WRP1AR_WRP1A_END_Pos (16U)

#define	FLASH_WRP1AR_WRP1A_END_Msk (0x1FUL << FLASH_WRP1AR_WRP1A_END_Pos)

#define	FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk

#define	FLASH_WRP1BR_WRP1B_STRT_Pos (0U)

#define	FLASH_WRP1BR_WRP1B_STRT_Msk (0x1FUL << FLASH_WRP1BR_WRP1B_STRT_Pos)

#define	FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk

#define	FLASH_WRP1BR_WRP1B_END_Pos (16U)

#define	FLASH_WRP1BR_WRP1B_END_Msk (0x1FUL << FLASH_WRP1BR_WRP1B_END_Pos)

#define	FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk

#define	GPIO_MODER_MODE0_Pos (0U)

#define	GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos)

#define	GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk

#define	GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos)

#define	GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos)

#define	GPIO_MODER_MODE1_Pos (2U)

#define	GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos)

#define	GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk

#define	GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos)

#define	GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos)

#define	GPIO_MODER_MODE2_Pos (4U)

#define	GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos)

#define	GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk

#define	GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos)

#define	GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos)

#define	GPIO_MODER_MODE3_Pos (6U)

#define	GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos)

#define	GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk

#define	GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos)

#define	GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos)

#define	GPIO_MODER_MODE4_Pos (8U)

#define	GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos)

#define	GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk

#define	GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos)

#define	GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos)

#define	GPIO_MODER_MODE5_Pos (10U)

#define	GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos)

#define	GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk

#define	GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos)

#define	GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos)

#define	GPIO_MODER_MODE6_Pos (12U)

#define	GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos)

#define	GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk

#define	GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos)

#define	GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos)

#define	GPIO_MODER_MODE7_Pos (14U)

#define	GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos)

#define	GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk

#define	GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos)

#define	GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos)

#define	GPIO_MODER_MODE8_Pos (16U)

#define	GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos)

#define	GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk

#define	GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos)

#define	GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos)

#define	GPIO_MODER_MODE9_Pos (18U)

#define	GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos)

#define	GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk

#define	GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos)

#define	GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos)

#define	GPIO_MODER_MODE10_Pos (20U)

#define	GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos)

#define	GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk

#define	GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos)

#define	GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos)

#define	GPIO_MODER_MODE11_Pos (22U)

#define	GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos)

#define	GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk

#define	GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos)

#define	GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos)

#define	GPIO_MODER_MODE12_Pos (24U)

#define	GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos)

#define	GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk

#define	GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos)

#define	GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos)

#define	GPIO_MODER_MODE13_Pos (26U)

#define	GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos)

#define	GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk

#define	GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos)

#define	GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos)

#define	GPIO_MODER_MODE14_Pos (28U)

#define	GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos)

#define	GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk

#define	GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos)

#define	GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos)

#define	GPIO_MODER_MODE15_Pos (30U)

#define	GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos)

#define	GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk

#define	GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos)

#define	GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos)

#define	GPIO_OTYPER_OT0_Pos (0U)

#define	GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos)

#define	GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk

#define	GPIO_OTYPER_OT1_Pos (1U)

#define	GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos)

#define	GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk

#define	GPIO_OTYPER_OT2_Pos (2U)

#define	GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos)

#define	GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk

#define	GPIO_OTYPER_OT3_Pos (3U)

#define	GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos)

#define	GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk

#define	GPIO_OTYPER_OT4_Pos (4U)

#define	GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos)

#define	GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk

#define	GPIO_OTYPER_OT5_Pos (5U)

#define	GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos)

#define	GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk

#define	GPIO_OTYPER_OT6_Pos (6U)

#define	GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos)

#define	GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk

#define	GPIO_OTYPER_OT7_Pos (7U)

#define	GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos)

#define	GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk

#define	GPIO_OTYPER_OT8_Pos (8U)

#define	GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos)

#define	GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk

#define	GPIO_OTYPER_OT9_Pos (9U)

#define	GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos)

#define	GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk

#define	GPIO_OTYPER_OT10_Pos (10U)

#define	GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos)

#define	GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk

#define	GPIO_OTYPER_OT11_Pos (11U)

#define	GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos)

#define	GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk

#define	GPIO_OTYPER_OT12_Pos (12U)

#define	GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos)

#define	GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk

#define	GPIO_OTYPER_OT13_Pos (13U)

#define	GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos)

#define	GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk

#define	GPIO_OTYPER_OT14_Pos (14U)

#define	GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos)

#define	GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk

#define	GPIO_OTYPER_OT15_Pos (15U)

#define	GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos)

#define	GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk

#define	GPIO_OSPEEDR_OSPEED0_Pos (0U)

#define	GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)

#define	GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk

#define	GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)

#define	GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)

#define	GPIO_OSPEEDR_OSPEED1_Pos (2U)

#define	GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)

#define	GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk

#define	GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)

#define	GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)

#define	GPIO_OSPEEDR_OSPEED2_Pos (4U)

#define	GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)

#define	GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk

#define	GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)

#define	GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)

#define	GPIO_OSPEEDR_OSPEED3_Pos (6U)

#define	GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)

#define	GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk

#define	GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)

#define	GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)

#define	GPIO_OSPEEDR_OSPEED4_Pos (8U)

#define	GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)

#define	GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk

#define	GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)

#define	GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)

#define	GPIO_OSPEEDR_OSPEED5_Pos (10U)

#define	GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)

#define	GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk

#define	GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)

#define	GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)

#define	GPIO_OSPEEDR_OSPEED6_Pos (12U)

#define	GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)

#define	GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk

#define	GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)

#define	GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)

#define	GPIO_OSPEEDR_OSPEED7_Pos (14U)

#define	GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)

#define	GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk

#define	GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)

#define	GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)

#define	GPIO_OSPEEDR_OSPEED8_Pos (16U)

#define	GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)

#define	GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk

#define	GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)

#define	GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)

#define	GPIO_OSPEEDR_OSPEED9_Pos (18U)

#define	GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)

#define	GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk

#define	GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)

#define	GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)

#define	GPIO_OSPEEDR_OSPEED10_Pos (20U)

#define	GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)

#define	GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk

#define	GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)

#define	GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)

#define	GPIO_OSPEEDR_OSPEED11_Pos (22U)

#define	GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)

#define	GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk

#define	GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)

#define	GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)

#define	GPIO_OSPEEDR_OSPEED12_Pos (24U)

#define	GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)

#define	GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk

#define	GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)

#define	GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)

#define	GPIO_OSPEEDR_OSPEED13_Pos (26U)

#define	GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)

#define	GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk

#define	GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)

#define	GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)

#define	GPIO_OSPEEDR_OSPEED14_Pos (28U)

#define	GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)

#define	GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk

#define	GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)

#define	GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)

#define	GPIO_OSPEEDR_OSPEED15_Pos (30U)

#define	GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)

#define	GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk

#define	GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)

#define	GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)

#define	GPIO_PUPDR_PUPD0_Pos (0U)

#define	GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos)

#define	GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk

#define	GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos)

#define	GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos)

#define	GPIO_PUPDR_PUPD1_Pos (2U)

#define	GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos)

#define	GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk

#define	GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos)

#define	GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos)

#define	GPIO_PUPDR_PUPD2_Pos (4U)

#define	GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos)

#define	GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk

#define	GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos)

#define	GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos)

#define	GPIO_PUPDR_PUPD3_Pos (6U)

#define	GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos)

#define	GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk

#define	GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos)

#define	GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos)

#define	GPIO_PUPDR_PUPD4_Pos (8U)

#define	GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos)

#define	GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk

#define	GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos)

#define	GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos)

#define	GPIO_PUPDR_PUPD5_Pos (10U)

#define	GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos)

#define	GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk

#define	GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos)

#define	GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos)

#define	GPIO_PUPDR_PUPD6_Pos (12U)

#define	GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos)

#define	GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk

#define	GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos)

#define	GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos)

#define	GPIO_PUPDR_PUPD7_Pos (14U)

#define	GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos)

#define	GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk

#define	GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos)

#define	GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos)

#define	GPIO_PUPDR_PUPD8_Pos (16U)

#define	GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos)

#define	GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk

#define	GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos)

#define	GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos)

#define	GPIO_PUPDR_PUPD9_Pos (18U)

#define	GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos)

#define	GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk

#define	GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos)

#define	GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos)

#define	GPIO_PUPDR_PUPD10_Pos (20U)

#define	GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos)

#define	GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk

#define	GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos)

#define	GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos)

#define	GPIO_PUPDR_PUPD11_Pos (22U)

#define	GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos)

#define	GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk

#define	GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos)

#define	GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos)

#define	GPIO_PUPDR_PUPD12_Pos (24U)

#define	GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos)

#define	GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk

#define	GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos)

#define	GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos)

#define	GPIO_PUPDR_PUPD13_Pos (26U)

#define	GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos)

#define	GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk

#define	GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos)

#define	GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos)

#define	GPIO_PUPDR_PUPD14_Pos (28U)

#define	GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos)

#define	GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk

#define	GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos)

#define	GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos)

#define	GPIO_PUPDR_PUPD15_Pos (30U)

#define	GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos)

#define	GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk

#define	GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos)

#define	GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos)

#define	GPIO_IDR_ID0_Pos (0U)

#define	GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos)

#define	GPIO_IDR_ID0 GPIO_IDR_ID0_Msk

#define	GPIO_IDR_ID1_Pos (1U)

#define	GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos)

#define	GPIO_IDR_ID1 GPIO_IDR_ID1_Msk

#define	GPIO_IDR_ID2_Pos (2U)

#define	GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos)

#define	GPIO_IDR_ID2 GPIO_IDR_ID2_Msk

#define	GPIO_IDR_ID3_Pos (3U)

#define	GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos)

#define	GPIO_IDR_ID3 GPIO_IDR_ID3_Msk

#define	GPIO_IDR_ID4_Pos (4U)

#define	GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos)

#define	GPIO_IDR_ID4 GPIO_IDR_ID4_Msk

#define	GPIO_IDR_ID5_Pos (5U)

#define	GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos)

#define	GPIO_IDR_ID5 GPIO_IDR_ID5_Msk

#define	GPIO_IDR_ID6_Pos (6U)

#define	GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos)

#define	GPIO_IDR_ID6 GPIO_IDR_ID6_Msk

#define	GPIO_IDR_ID7_Pos (7U)

#define	GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos)

#define	GPIO_IDR_ID7 GPIO_IDR_ID7_Msk

#define	GPIO_IDR_ID8_Pos (8U)

#define	GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos)

#define	GPIO_IDR_ID8 GPIO_IDR_ID8_Msk

#define	GPIO_IDR_ID9_Pos (9U)

#define	GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos)

#define	GPIO_IDR_ID9 GPIO_IDR_ID9_Msk

#define	GPIO_IDR_ID10_Pos (10U)

#define	GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos)

#define	GPIO_IDR_ID10 GPIO_IDR_ID10_Msk

#define	GPIO_IDR_ID11_Pos (11U)

#define	GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos)

#define	GPIO_IDR_ID11 GPIO_IDR_ID11_Msk

#define	GPIO_IDR_ID12_Pos (12U)

#define	GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos)

#define	GPIO_IDR_ID12 GPIO_IDR_ID12_Msk

#define	GPIO_IDR_ID13_Pos (13U)

#define	GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos)

#define	GPIO_IDR_ID13 GPIO_IDR_ID13_Msk

#define	GPIO_IDR_ID14_Pos (14U)

#define	GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos)

#define	GPIO_IDR_ID14 GPIO_IDR_ID14_Msk

#define	GPIO_IDR_ID15_Pos (15U)

#define	GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos)

#define	GPIO_IDR_ID15 GPIO_IDR_ID15_Msk

#define	GPIO_ODR_OD0_Pos (0U)

#define	GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos)

#define	GPIO_ODR_OD0 GPIO_ODR_OD0_Msk

#define	GPIO_ODR_OD1_Pos (1U)

#define	GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos)

#define	GPIO_ODR_OD1 GPIO_ODR_OD1_Msk

#define	GPIO_ODR_OD2_Pos (2U)

#define	GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos)

#define	GPIO_ODR_OD2 GPIO_ODR_OD2_Msk

#define	GPIO_ODR_OD3_Pos (3U)

#define	GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos)

#define	GPIO_ODR_OD3 GPIO_ODR_OD3_Msk

#define	GPIO_ODR_OD4_Pos (4U)

#define	GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos)

#define	GPIO_ODR_OD4 GPIO_ODR_OD4_Msk

#define	GPIO_ODR_OD5_Pos (5U)

#define	GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos)

#define	GPIO_ODR_OD5 GPIO_ODR_OD5_Msk

#define	GPIO_ODR_OD6_Pos (6U)

#define	GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos)

#define	GPIO_ODR_OD6 GPIO_ODR_OD6_Msk

#define	GPIO_ODR_OD7_Pos (7U)

#define	GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos)

#define	GPIO_ODR_OD7 GPIO_ODR_OD7_Msk

#define	GPIO_ODR_OD8_Pos (8U)

#define	GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos)

#define	GPIO_ODR_OD8 GPIO_ODR_OD8_Msk

#define	GPIO_ODR_OD9_Pos (9U)

#define	GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos)

#define	GPIO_ODR_OD9 GPIO_ODR_OD9_Msk

#define	GPIO_ODR_OD10_Pos (10U)

#define	GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos)

#define	GPIO_ODR_OD10 GPIO_ODR_OD10_Msk

#define	GPIO_ODR_OD11_Pos (11U)

#define	GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos)

#define	GPIO_ODR_OD11 GPIO_ODR_OD11_Msk

#define	GPIO_ODR_OD12_Pos (12U)

#define	GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos)

#define	GPIO_ODR_OD12 GPIO_ODR_OD12_Msk

#define	GPIO_ODR_OD13_Pos (13U)

#define	GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos)

#define	GPIO_ODR_OD13 GPIO_ODR_OD13_Msk

#define	GPIO_ODR_OD14_Pos (14U)

#define	GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos)

#define	GPIO_ODR_OD14 GPIO_ODR_OD14_Msk

#define	GPIO_ODR_OD15_Pos (15U)

#define	GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos)

#define	GPIO_ODR_OD15 GPIO_ODR_OD15_Msk

#define	GPIO_BSRR_BS0_Pos (0U)

#define	GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos)

#define	GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk

#define	GPIO_BSRR_BS1_Pos (1U)

#define	GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos)

#define	GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk

#define	GPIO_BSRR_BS2_Pos (2U)

#define	GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos)

#define	GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk

#define	GPIO_BSRR_BS3_Pos (3U)

#define	GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos)

#define	GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk

#define	GPIO_BSRR_BS4_Pos (4U)

#define	GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos)

#define	GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk

#define	GPIO_BSRR_BS5_Pos (5U)

#define	GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos)

#define	GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk

#define	GPIO_BSRR_BS6_Pos (6U)

#define	GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos)

#define	GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk

#define	GPIO_BSRR_BS7_Pos (7U)

#define	GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos)

#define	GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk

#define	GPIO_BSRR_BS8_Pos (8U)

#define	GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos)

#define	GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk

#define	GPIO_BSRR_BS9_Pos (9U)

#define	GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos)

#define	GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk

#define	GPIO_BSRR_BS10_Pos (10U)

#define	GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos)

#define	GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk

#define	GPIO_BSRR_BS11_Pos (11U)

#define	GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos)

#define	GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk

#define	GPIO_BSRR_BS12_Pos (12U)

#define	GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos)

#define	GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk

#define	GPIO_BSRR_BS13_Pos (13U)

#define	GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos)

#define	GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk

#define	GPIO_BSRR_BS14_Pos (14U)

#define	GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos)

#define	GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk

#define	GPIO_BSRR_BS15_Pos (15U)

#define	GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos)

#define	GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk

#define	GPIO_BSRR_BR0_Pos (16U)

#define	GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos)

#define	GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk

#define	GPIO_BSRR_BR1_Pos (17U)

#define	GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos)

#define	GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk

#define	GPIO_BSRR_BR2_Pos (18U)

#define	GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos)

#define	GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk

#define	GPIO_BSRR_BR3_Pos (19U)

#define	GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos)

#define	GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk

#define	GPIO_BSRR_BR4_Pos (20U)

#define	GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos)

#define	GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk

#define	GPIO_BSRR_BR5_Pos (21U)

#define	GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos)

#define	GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk

#define	GPIO_BSRR_BR6_Pos (22U)

#define	GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos)

#define	GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk

#define	GPIO_BSRR_BR7_Pos (23U)

#define	GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos)

#define	GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk

#define	GPIO_BSRR_BR8_Pos (24U)

#define	GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos)

#define	GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk

#define	GPIO_BSRR_BR9_Pos (25U)

#define	GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos)

#define	GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk

#define	GPIO_BSRR_BR10_Pos (26U)

#define	GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos)

#define	GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk

#define	GPIO_BSRR_BR11_Pos (27U)

#define	GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos)

#define	GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk

#define	GPIO_BSRR_BR12_Pos (28U)

#define	GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos)

#define	GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk

#define	GPIO_BSRR_BR13_Pos (29U)

#define	GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos)

#define	GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk

#define	GPIO_BSRR_BR14_Pos (30U)

#define	GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos)

#define	GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk

#define	GPIO_BSRR_BR15_Pos (31U)

#define	GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos)

#define	GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk

#define	GPIO_LCKR_LCK0_Pos (0U)

#define	GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos)

#define	GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk

#define	GPIO_LCKR_LCK1_Pos (1U)

#define	GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos)

#define	GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk

#define	GPIO_LCKR_LCK2_Pos (2U)

#define	GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos)

#define	GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk

#define	GPIO_LCKR_LCK3_Pos (3U)

#define	GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos)

#define	GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk

#define	GPIO_LCKR_LCK4_Pos (4U)

#define	GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos)

#define	GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk

#define	GPIO_LCKR_LCK5_Pos (5U)

#define	GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos)

#define	GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk

#define	GPIO_LCKR_LCK6_Pos (6U)

#define	GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos)

#define	GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk

#define	GPIO_LCKR_LCK7_Pos (7U)

#define	GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos)

#define	GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk

#define	GPIO_LCKR_LCK8_Pos (8U)

#define	GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos)

#define	GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk

#define	GPIO_LCKR_LCK9_Pos (9U)

#define	GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos)

#define	GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk

#define	GPIO_LCKR_LCK10_Pos (10U)

#define	GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos)

#define	GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk

#define	GPIO_LCKR_LCK11_Pos (11U)

#define	GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos)

#define	GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk

#define	GPIO_LCKR_LCK12_Pos (12U)

#define	GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos)

#define	GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk

#define	GPIO_LCKR_LCK13_Pos (13U)

#define	GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos)

#define	GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk

#define	GPIO_LCKR_LCK14_Pos (14U)

#define	GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos)

#define	GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk

#define	GPIO_LCKR_LCK15_Pos (15U)

#define	GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos)

#define	GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk

#define	GPIO_LCKR_LCKK_Pos (16U)

#define	GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos)

#define	GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk

#define	GPIO_AFRL_AFSEL0_Pos (0U)

#define	GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos)

#define	GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk

#define	GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos)

#define	GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos)

#define	GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos)

#define	GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos)

#define	GPIO_AFRL_AFSEL1_Pos (4U)

#define	GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos)

#define	GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk

#define	GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos)

#define	GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos)

#define	GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos)

#define	GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos)

#define	GPIO_AFRL_AFSEL2_Pos (8U)

#define	GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos)

#define	GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk

#define	GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos)

#define	GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos)

#define	GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos)

#define	GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos)

#define	GPIO_AFRL_AFSEL3_Pos (12U)

#define	GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos)

#define	GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk

#define	GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos)

#define	GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos)

#define	GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos)

#define	GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos)

#define	GPIO_AFRL_AFSEL4_Pos (16U)

#define	GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos)

#define	GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk

#define	GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos)

#define	GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos)

#define	GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos)

#define	GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos)

#define	GPIO_AFRL_AFSEL5_Pos (20U)

#define	GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos)

#define	GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk

#define	GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos)

#define	GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos)

#define	GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos)

#define	GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos)

#define	GPIO_AFRL_AFSEL6_Pos (24U)

#define	GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos)

#define	GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk

#define	GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos)

#define	GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos)

#define	GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos)

#define	GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos)

#define	GPIO_AFRL_AFSEL7_Pos (28U)

#define	GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos)

#define	GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk

#define	GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos)

#define	GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos)

#define	GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos)

#define	GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos)

#define	GPIO_AFRH_AFSEL8_Pos (0U)

#define	GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos)

#define	GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk

#define	GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos)

#define	GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos)

#define	GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos)

#define	GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos)

#define	GPIO_AFRH_AFSEL9_Pos (4U)

#define	GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos)

#define	GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk

#define	GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos)

#define	GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos)

#define	GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos)

#define	GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos)

#define	GPIO_AFRH_AFSEL10_Pos (8U)

#define	GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos)

#define	GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk

#define	GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos)

#define	GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos)

#define	GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos)

#define	GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos)

#define	GPIO_AFRH_AFSEL11_Pos (12U)

#define	GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos)

#define	GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk

#define	GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos)

#define	GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos)

#define	GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos)

#define	GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos)

#define	GPIO_AFRH_AFSEL12_Pos (16U)

#define	GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos)

#define	GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk

#define	GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos)

#define	GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos)

#define	GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos)

#define	GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos)

#define	GPIO_AFRH_AFSEL13_Pos (20U)

#define	GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos)

#define	GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk

#define	GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos)

#define	GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos)

#define	GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos)

#define	GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos)

#define	GPIO_AFRH_AFSEL14_Pos (24U)

#define	GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos)

#define	GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk

#define	GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos)

#define	GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos)

#define	GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos)

#define	GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos)

#define	GPIO_AFRH_AFSEL15_Pos (28U)

#define	GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos)

#define	GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk

#define	GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos)

#define	GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos)

#define	GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos)

#define	GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos)

#define	GPIO_BRR_BR0_Pos (0U)

#define	GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos)

#define	GPIO_BRR_BR0 GPIO_BRR_BR0_Msk

#define	GPIO_BRR_BR1_Pos (1U)

#define	GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos)

#define	GPIO_BRR_BR1 GPIO_BRR_BR1_Msk

#define	GPIO_BRR_BR2_Pos (2U)

#define	GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos)

#define	GPIO_BRR_BR2 GPIO_BRR_BR2_Msk

#define	GPIO_BRR_BR3_Pos (3U)

#define	GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos)

#define	GPIO_BRR_BR3 GPIO_BRR_BR3_Msk

#define	GPIO_BRR_BR4_Pos (4U)

#define	GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos)

#define	GPIO_BRR_BR4 GPIO_BRR_BR4_Msk

#define	GPIO_BRR_BR5_Pos (5U)

#define	GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos)

#define	GPIO_BRR_BR5 GPIO_BRR_BR5_Msk

#define	GPIO_BRR_BR6_Pos (6U)

#define	GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos)

#define	GPIO_BRR_BR6 GPIO_BRR_BR6_Msk

#define	GPIO_BRR_BR7_Pos (7U)

#define	GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos)

#define	GPIO_BRR_BR7 GPIO_BRR_BR7_Msk

#define	GPIO_BRR_BR8_Pos (8U)

#define	GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos)

#define	GPIO_BRR_BR8 GPIO_BRR_BR8_Msk

#define	GPIO_BRR_BR9_Pos (9U)

#define	GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos)

#define	GPIO_BRR_BR9 GPIO_BRR_BR9_Msk

#define	GPIO_BRR_BR10_Pos (10U)

#define	GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos)

#define	GPIO_BRR_BR10 GPIO_BRR_BR10_Msk

#define	GPIO_BRR_BR11_Pos (11U)

#define	GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos)

#define	GPIO_BRR_BR11 GPIO_BRR_BR11_Msk

#define	GPIO_BRR_BR12_Pos (12U)

#define	GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos)

#define	GPIO_BRR_BR12 GPIO_BRR_BR12_Msk

#define	GPIO_BRR_BR13_Pos (13U)

#define	GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos)

#define	GPIO_BRR_BR13 GPIO_BRR_BR13_Msk

#define	GPIO_BRR_BR14_Pos (14U)

#define	GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos)

#define	GPIO_BRR_BR14 GPIO_BRR_BR14_Msk

#define	GPIO_BRR_BR15_Pos (15U)

#define	GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos)

#define	GPIO_BRR_BR15 GPIO_BRR_BR15_Msk

#define	I2C_CR1_PE_Pos (0U)

#define	I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos)

#define	I2C_CR1_PE I2C_CR1_PE_Msk

#define	I2C_CR1_TXIE_Pos (1U)

#define	I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos)

#define	I2C_CR1_TXIE I2C_CR1_TXIE_Msk

#define	I2C_CR1_RXIE_Pos (2U)

#define	I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos)

#define	I2C_CR1_RXIE I2C_CR1_RXIE_Msk

#define	I2C_CR1_ADDRIE_Pos (3U)

#define	I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos)

#define	I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk

#define	I2C_CR1_NACKIE_Pos (4U)

#define	I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos)

#define	I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk

#define	I2C_CR1_STOPIE_Pos (5U)

#define	I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos)

#define	I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk

#define	I2C_CR1_TCIE_Pos (6U)

#define	I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos)

#define	I2C_CR1_TCIE I2C_CR1_TCIE_Msk

#define	I2C_CR1_ERRIE_Pos (7U)

#define	I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos)

#define	I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk

#define	I2C_CR1_DNF_Pos (8U)

#define	I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos)

#define	I2C_CR1_DNF I2C_CR1_DNF_Msk

#define	I2C_CR1_ANFOFF_Pos (12U)

#define	I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos)

#define	I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk

#define	I2C_CR1_SWRST_Pos (13U)

#define	I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos)

#define	I2C_CR1_SWRST I2C_CR1_SWRST_Msk

#define	I2C_CR1_TXDMAEN_Pos (14U)

#define	I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos)

#define	I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk

#define	I2C_CR1_RXDMAEN_Pos (15U)

#define	I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos)

#define	I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk

#define	I2C_CR1_SBC_Pos (16U)

#define	I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos)

#define	I2C_CR1_SBC I2C_CR1_SBC_Msk

#define	I2C_CR1_NOSTRETCH_Pos (17U)

#define	I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos)

#define	I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk

#define	I2C_CR1_WUPEN_Pos (18U)

#define	I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos)

#define	I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk

#define	I2C_CR1_GCEN_Pos (19U)

#define	I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos)

#define	I2C_CR1_GCEN I2C_CR1_GCEN_Msk

#define	I2C_CR1_SMBHEN_Pos (20U)

#define	I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos)

#define	I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk

#define	I2C_CR1_SMBDEN_Pos (21U)

#define	I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos)

#define	I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk

#define	I2C_CR1_ALERTEN_Pos (22U)

#define	I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos)

#define	I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk

#define	I2C_CR1_PECEN_Pos (23U)

#define	I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos)

#define	I2C_CR1_PECEN I2C_CR1_PECEN_Msk

#define	I2C_CR2_SADD_Pos (0U)

#define	I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos)

#define	I2C_CR2_SADD I2C_CR2_SADD_Msk

#define	I2C_CR2_RD_WRN_Pos (10U)

#define	I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos)

#define	I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk

#define	I2C_CR2_ADD10_Pos (11U)

#define	I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos)

#define	I2C_CR2_ADD10 I2C_CR2_ADD10_Msk

#define	I2C_CR2_HEAD10R_Pos (12U)

#define	I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos)

#define	I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk

#define	I2C_CR2_START_Pos (13U)

#define	I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos)

#define	I2C_CR2_START I2C_CR2_START_Msk

#define	I2C_CR2_STOP_Pos (14U)

#define	I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos)

#define	I2C_CR2_STOP I2C_CR2_STOP_Msk

#define	I2C_CR2_NACK_Pos (15U)

#define	I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos)

#define	I2C_CR2_NACK I2C_CR2_NACK_Msk

#define	I2C_CR2_NBYTES_Pos (16U)

#define	I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos)

#define	I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk

#define	I2C_CR2_RELOAD_Pos (24U)

#define	I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos)

#define	I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk

#define	I2C_CR2_AUTOEND_Pos (25U)

#define	I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos)

#define	I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk

#define	I2C_CR2_PECBYTE_Pos (26U)

#define	I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos)

#define	I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk

#define	I2C_OAR1_OA1_Pos (0U)

#define	I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos)

#define	I2C_OAR1_OA1 I2C_OAR1_OA1_Msk

#define	I2C_OAR1_OA1MODE_Pos (10U)

#define	I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos)

#define	I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk

#define	I2C_OAR1_OA1EN_Pos (15U)

#define	I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos)

#define	I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk

#define	I2C_OAR2_OA2_Pos (1U)

#define	I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos)

#define	I2C_OAR2_OA2 I2C_OAR2_OA2_Msk

#define	I2C_OAR2_OA2MSK_Pos (8U)

#define	I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos)

#define	I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk

#define	I2C_OAR2_OA2NOMASK (0U)

#define	I2C_OAR2_OA2MASK01_Pos (8U)

#define	I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos)

#define	I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk

#define	I2C_OAR2_OA2MASK02_Pos (9U)

#define	I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos)

#define	I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk

#define	I2C_OAR2_OA2MASK03_Pos (8U)

#define	I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos)

#define	I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk

#define	I2C_OAR2_OA2MASK04_Pos (10U)

#define	I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos)

#define	I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk

#define	I2C_OAR2_OA2MASK05_Pos (8U)

#define	I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos)

#define	I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk

#define	I2C_OAR2_OA2MASK06_Pos (9U)

#define	I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos)

#define	I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk

#define	I2C_OAR2_OA2MASK07_Pos (8U)

#define	I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos)

#define	I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk

#define	I2C_OAR2_OA2EN_Pos (15U)

#define	I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos)

#define	I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk

#define	I2C_TIMINGR_SCLL_Pos (0U)

#define	I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos)

#define	I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk

#define	I2C_TIMINGR_SCLH_Pos (8U)

#define	I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos)

#define	I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk

#define	I2C_TIMINGR_SDADEL_Pos (16U)

#define	I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos)

#define	I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk

#define	I2C_TIMINGR_SCLDEL_Pos (20U)

#define	I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos)

#define	I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk

#define	I2C_TIMINGR_PRESC_Pos (28U)

#define	I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos)

#define	I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk

#define	I2C_TIMEOUTR_TIMEOUTA_Pos (0U)

#define	I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)

#define	I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk

#define	I2C_TIMEOUTR_TIDLE_Pos (12U)

#define	I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)

#define	I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk

#define	I2C_TIMEOUTR_TIMOUTEN_Pos (15U)

#define	I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)

#define	I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk

#define	I2C_TIMEOUTR_TIMEOUTB_Pos (16U)

#define	I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)

#define	I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk

#define	I2C_TIMEOUTR_TEXTEN_Pos (31U)

#define	I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)

#define	I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk

#define	I2C_ISR_TXE_Pos (0U)

#define	I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos)

#define	I2C_ISR_TXE I2C_ISR_TXE_Msk

#define	I2C_ISR_TXIS_Pos (1U)

#define	I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos)

#define	I2C_ISR_TXIS I2C_ISR_TXIS_Msk

#define	I2C_ISR_RXNE_Pos (2U)

#define	I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos)

#define	I2C_ISR_RXNE I2C_ISR_RXNE_Msk

#define	I2C_ISR_ADDR_Pos (3U)

#define	I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos)

#define	I2C_ISR_ADDR I2C_ISR_ADDR_Msk

#define	I2C_ISR_NACKF_Pos (4U)

#define	I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos)

#define	I2C_ISR_NACKF I2C_ISR_NACKF_Msk

#define	I2C_ISR_STOPF_Pos (5U)

#define	I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos)

#define	I2C_ISR_STOPF I2C_ISR_STOPF_Msk

#define	I2C_ISR_TC_Pos (6U)

#define	I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos)

#define	I2C_ISR_TC I2C_ISR_TC_Msk

#define	I2C_ISR_TCR_Pos (7U)

#define	I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos)

#define	I2C_ISR_TCR I2C_ISR_TCR_Msk

#define	I2C_ISR_BERR_Pos (8U)

#define	I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos)

#define	I2C_ISR_BERR I2C_ISR_BERR_Msk

#define	I2C_ISR_ARLO_Pos (9U)

#define	I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos)

#define	I2C_ISR_ARLO I2C_ISR_ARLO_Msk

#define	I2C_ISR_OVR_Pos (10U)

#define	I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos)

#define	I2C_ISR_OVR I2C_ISR_OVR_Msk

#define	I2C_ISR_PECERR_Pos (11U)

#define	I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos)

#define	I2C_ISR_PECERR I2C_ISR_PECERR_Msk

#define	I2C_ISR_TIMEOUT_Pos (12U)

#define	I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos)

#define	I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk

#define	I2C_ISR_ALERT_Pos (13U)

#define	I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos)

#define	I2C_ISR_ALERT I2C_ISR_ALERT_Msk

#define	I2C_ISR_BUSY_Pos (15U)

#define	I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos)

#define	I2C_ISR_BUSY I2C_ISR_BUSY_Msk

#define	I2C_ISR_DIR_Pos (16U)

#define	I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos)

#define	I2C_ISR_DIR I2C_ISR_DIR_Msk

#define	I2C_ISR_ADDCODE_Pos (17U)

#define	I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos)

#define	I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk

#define	I2C_ICR_ADDRCF_Pos (3U)

#define	I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos)

#define	I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk

#define	I2C_ICR_NACKCF_Pos (4U)

#define	I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos)

#define	I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk

#define	I2C_ICR_STOPCF_Pos (5U)

#define	I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos)

#define	I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk

#define	I2C_ICR_BERRCF_Pos (8U)

#define	I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos)

#define	I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk

#define	I2C_ICR_ARLOCF_Pos (9U)

#define	I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos)

#define	I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk

#define	I2C_ICR_OVRCF_Pos (10U)

#define	I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos)

#define	I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk

#define	I2C_ICR_PECCF_Pos (11U)

#define	I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos)

#define	I2C_ICR_PECCF I2C_ICR_PECCF_Msk

#define	I2C_ICR_TIMOUTCF_Pos (12U)

#define	I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos)

#define	I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk

#define	I2C_ICR_ALERTCF_Pos (13U)

#define	I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos)

#define	I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk

#define	I2C_PECR_PEC_Pos (0U)

#define	I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos)

#define	I2C_PECR_PEC I2C_PECR_PEC_Msk

#define	I2C_RXDR_RXDATA_Pos (0U)

#define	I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos)

#define	I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk

#define	I2C_TXDR_TXDATA_Pos (0U)

#define	I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos)

#define	I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk

#define	IWDG_KR_KEY_Pos (0U)

#define	IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos)

#define	IWDG_KR_KEY IWDG_KR_KEY_Msk

#define	IWDG_PR_PR_Pos (0U)

#define	IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos)

#define	IWDG_PR_PR IWDG_PR_PR_Msk

#define	IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos)

#define	IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos)

#define	IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos)

#define	IWDG_RLR_RL_Pos (0U)

#define	IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos)

#define	IWDG_RLR_RL IWDG_RLR_RL_Msk

#define	IWDG_SR_PVU_Pos (0U)

#define	IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos)

#define	IWDG_SR_PVU IWDG_SR_PVU_Msk

#define	IWDG_SR_RVU_Pos (1U)

#define	IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos)

#define	IWDG_SR_RVU IWDG_SR_RVU_Msk

#define	IWDG_SR_WVU_Pos (2U)

#define	IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos)

#define	IWDG_SR_WVU IWDG_SR_WVU_Msk

#define	IWDG_WINR_WIN_Pos (0U)

#define	IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos)

#define	IWDG_WINR_WIN IWDG_WINR_WIN_Msk

#define	PWR_CR1_LPMS_Pos (0U)

#define	PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos)

#define	PWR_CR1_LPMS PWR_CR1_LPMS_Msk

#define	PWR_CR1_LPMS_0 (0x1UL << PWR_CR1_LPMS_Pos)

#define	PWR_CR1_LPMS_1 (0x2UL << PWR_CR1_LPMS_Pos)

#define	PWR_CR1_FPD_STOP_Pos (3U)

#define	PWR_CR1_FPD_STOP_Msk (0x1UL << PWR_CR1_FPD_STOP_Pos)

#define	PWR_CR1_FPD_STOP PWR_CR1_FPD_STOP_Msk

#define	PWR_CR1_FPD_LPRUN_Pos (4U)

#define	PWR_CR1_FPD_LPRUN_Msk (0x1UL << PWR_CR1_FPD_LPRUN_Pos)

#define	PWR_CR1_FPD_LPRUN PWR_CR1_FPD_LPRUN_Msk

#define	PWR_CR1_FPD_LPSLP_Pos (5U)

#define	PWR_CR1_FPD_LPSLP_Msk (0x1UL << PWR_CR1_FPD_LPSLP_Pos)

#define	PWR_CR1_FPD_LPSLP PWR_CR1_FPD_LPSLP_Msk

#define	PWR_CR1_DBP_Pos (8U)

#define	PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos)

#define	PWR_CR1_DBP PWR_CR1_DBP_Msk

#define	PWR_CR1_VOS_Pos (9U)

#define	PWR_CR1_VOS_Msk (0x3UL << PWR_CR1_VOS_Pos)

#define	PWR_CR1_VOS PWR_CR1_VOS_Msk

#define	PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_Pos)

#define	PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_Pos)

#define	PWR_CR1_LPR_Pos (14U)

#define	PWR_CR1_LPR_Msk (0x1UL << PWR_CR1_LPR_Pos)

#define	PWR_CR1_LPR PWR_CR1_LPR_Msk

#define	PWR_CR3_EWUP_Pos (0U)

#define	PWR_CR3_EWUP_Msk (0x2BUL << PWR_CR3_EWUP_Pos)

#define	PWR_CR3_EWUP PWR_CR3_EWUP_Msk

#define	PWR_CR3_EWUP1_Pos (0U)

#define	PWR_CR3_EWUP1_Msk (0x1UL << PWR_CR3_EWUP1_Pos)

#define	PWR_CR3_EWUP1 PWR_CR3_EWUP1_Msk

#define	PWR_CR3_EWUP2_Pos (1U)

#define	PWR_CR3_EWUP2_Msk (0x1UL << PWR_CR3_EWUP2_Pos)

#define	PWR_CR3_EWUP2 PWR_CR3_EWUP2_Msk

#define	PWR_CR3_EWUP4_Pos (3U)

#define	PWR_CR3_EWUP4_Msk (0x1UL << PWR_CR3_EWUP4_Pos)

#define	PWR_CR3_EWUP4 PWR_CR3_EWUP4_Msk

#define	PWR_CR3_EWUP6_Pos (5U)

#define	PWR_CR3_EWUP6_Msk (0x1UL << PWR_CR3_EWUP6_Pos)

#define	PWR_CR3_EWUP6 PWR_CR3_EWUP6_Msk

#define	PWR_CR3_APC_Pos (10U)

#define	PWR_CR3_APC_Msk (0x1UL << PWR_CR3_APC_Pos)

#define	PWR_CR3_APC PWR_CR3_APC_Msk

#define	PWR_CR3_EIWUL_Pos (15U)

#define	PWR_CR3_EIWUL_Msk (0x1UL << PWR_CR3_EIWUL_Pos)

#define	PWR_CR3_EIWUL PWR_CR3_EIWUL_Msk

#define	PWR_CR4_WP_Pos (0U)

#define	PWR_CR4_WP_Msk (0x2BUL << PWR_CR4_WP_Pos)

#define	PWR_CR4_WP PWR_CR4_WP_Msk

#define	PWR_CR4_WP1_Pos (0U)

#define	PWR_CR4_WP1_Msk (0x1UL << PWR_CR4_WP1_Pos)

#define	PWR_CR4_WP1 PWR_CR4_WP1_Msk

#define	PWR_CR4_WP2_Pos (1U)

#define	PWR_CR4_WP2_Msk (0x1UL << PWR_CR4_WP2_Pos)

#define	PWR_CR4_WP2 PWR_CR4_WP2_Msk

#define	PWR_CR4_WP4_Pos (3U)

#define	PWR_CR4_WP4_Msk (0x1UL << PWR_CR4_WP4_Pos)

#define	PWR_CR4_WP4 PWR_CR4_WP4_Msk

#define	PWR_CR4_WP6_Pos (5U)

#define	PWR_CR4_WP6_Msk (0x1UL << PWR_CR4_WP6_Pos)

#define	PWR_CR4_WP6 PWR_CR4_WP6_Msk

#define	PWR_CR4_VBE_Pos (8U)

#define	PWR_CR4_VBE_Msk (0x1UL << PWR_CR4_VBE_Pos)

#define	PWR_CR4_VBE PWR_CR4_VBE_Msk

#define	PWR_CR4_VBRS_Pos (9U)

#define	PWR_CR4_VBRS_Msk (0x1UL << PWR_CR4_VBRS_Pos)

#define	PWR_CR4_VBRS PWR_CR4_VBRS_Msk

#define	PWR_SR1_WUF_Pos (0U)

#define	PWR_SR1_WUF_Msk (0x2BUL << PWR_SR1_WUF_Pos)

#define	PWR_SR1_WUF PWR_SR1_WUF_Msk

#define	PWR_SR1_WUF1_Pos (0U)

#define	PWR_SR1_WUF1_Msk (0x1UL << PWR_SR1_WUF1_Pos)

#define	PWR_SR1_WUF1 PWR_SR1_WUF1_Msk

#define	PWR_SR1_WUF2_Pos (1U)

#define	PWR_SR1_WUF2_Msk (0x1UL << PWR_SR1_WUF2_Pos)

#define	PWR_SR1_WUF2 PWR_SR1_WUF2_Msk

#define	PWR_SR1_WUF4_Pos (3U)

#define	PWR_SR1_WUF4_Msk (0x1UL << PWR_SR1_WUF4_Pos)

#define	PWR_SR1_WUF4 PWR_SR1_WUF4_Msk

#define	PWR_SR1_WUF6_Pos (5U)

#define	PWR_SR1_WUF6_Msk (0x1UL << PWR_SR1_WUF6_Pos)

#define	PWR_SR1_WUF6 PWR_SR1_WUF6_Msk

#define	PWR_SR1_SBF_Pos (8U)

#define	PWR_SR1_SBF_Msk (0x1UL << PWR_SR1_SBF_Pos)

#define	PWR_SR1_SBF PWR_SR1_SBF_Msk

#define	PWR_SR1_WUFI_Pos (15U)

#define	PWR_SR1_WUFI_Msk (0x1UL << PWR_SR1_WUFI_Pos)

#define	PWR_SR1_WUFI PWR_SR1_WUFI_Msk

#define	PWR_SR2_FLASH_RDY_Pos (7U)

#define	PWR_SR2_FLASH_RDY_Msk (0x1UL << PWR_SR2_FLASH_RDY_Pos)

#define	PWR_SR2_FLASH_RDY PWR_SR2_FLASH_RDY_Msk

#define	PWR_SR2_REGLPS_Pos (8U)

#define	PWR_SR2_REGLPS_Msk (0x1UL << PWR_SR2_REGLPS_Pos)

#define	PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk

#define	PWR_SR2_REGLPF_Pos (9U)

#define	PWR_SR2_REGLPF_Msk (0x1UL << PWR_SR2_REGLPF_Pos)

#define	PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk

#define	PWR_SR2_VOSF_Pos (10U)

#define	PWR_SR2_VOSF_Msk (0x1UL << PWR_SR2_VOSF_Pos)

#define	PWR_SR2_VOSF PWR_SR2_VOSF_Msk

#define	PWR_SCR_CWUF_Pos (0U)

#define	PWR_SCR_CWUF_Msk (0x2BUL << PWR_SCR_CWUF_Pos)

#define	PWR_SCR_CWUF PWR_SCR_CWUF_Msk

#define	PWR_SCR_CWUF1_Pos (0U)

#define	PWR_SCR_CWUF1_Msk (0x1UL << PWR_SCR_CWUF1_Pos)

#define	PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk

#define	PWR_SCR_CWUF2_Pos (1U)

#define	PWR_SCR_CWUF2_Msk (0x1UL << PWR_SCR_CWUF2_Pos)

#define	PWR_SCR_CWUF2 PWR_SCR_CWUF2_Msk

#define	PWR_SCR_CWUF4_Pos (3U)

#define	PWR_SCR_CWUF4_Msk (0x1UL << PWR_SCR_CWUF4_Pos)

#define	PWR_SCR_CWUF4 PWR_SCR_CWUF4_Msk

#define	PWR_SCR_CWUF6_Pos (5U)

#define	PWR_SCR_CWUF6_Msk (0x1UL << PWR_SCR_CWUF6_Pos)

#define	PWR_SCR_CWUF6 PWR_SCR_CWUF6_Msk

#define	PWR_SCR_CSBF_Pos (8U)

#define	PWR_SCR_CSBF_Msk (0x1UL << PWR_SCR_CSBF_Pos)

#define	PWR_SCR_CSBF PWR_SCR_CSBF_Msk

#define	PWR_PUCRA_PU0_Pos (0U)

#define	PWR_PUCRA_PU0_Msk (0x1UL << PWR_PUCRA_PU0_Pos)

#define	PWR_PUCRA_PU0 PWR_PUCRA_PU0_Msk

#define	PWR_PUCRA_PU1_Pos (1U)

#define	PWR_PUCRA_PU1_Msk (0x1UL << PWR_PUCRA_PU1_Pos)

#define	PWR_PUCRA_PU1 PWR_PUCRA_PU1_Msk

#define	PWR_PUCRA_PU2_Pos (2U)

#define	PWR_PUCRA_PU2_Msk (0x1UL << PWR_PUCRA_PU2_Pos)

#define	PWR_PUCRA_PU2 PWR_PUCRA_PU2_Msk

#define	PWR_PUCRA_PU3_Pos (3U)

#define	PWR_PUCRA_PU3_Msk (0x1UL << PWR_PUCRA_PU3_Pos)

#define	PWR_PUCRA_PU3 PWR_PUCRA_PU3_Msk

#define	PWR_PUCRA_PU4_Pos (4U)

#define	PWR_PUCRA_PU4_Msk (0x1UL << PWR_PUCRA_PU4_Pos)

#define	PWR_PUCRA_PU4 PWR_PUCRA_PU4_Msk

#define	PWR_PUCRA_PU5_Pos (5U)

#define	PWR_PUCRA_PU5_Msk (0x1UL << PWR_PUCRA_PU5_Pos)

#define	PWR_PUCRA_PU5 PWR_PUCRA_PU5_Msk

#define	PWR_PUCRA_PU6_Pos (6U)

#define	PWR_PUCRA_PU6_Msk (0x1UL << PWR_PUCRA_PU6_Pos)

#define	PWR_PUCRA_PU6 PWR_PUCRA_PU6_Msk

#define	PWR_PUCRA_PU7_Pos (7U)

#define	PWR_PUCRA_PU7_Msk (0x1UL << PWR_PUCRA_PU7_Pos)

#define	PWR_PUCRA_PU7 PWR_PUCRA_PU7_Msk

#define	PWR_PUCRA_PU8_Pos (8U)

#define	PWR_PUCRA_PU8_Msk (0x1UL << PWR_PUCRA_PU8_Pos)

#define	PWR_PUCRA_PU8 PWR_PUCRA_PU8_Msk

#define	PWR_PUCRA_PU9_Pos (9U)

#define	PWR_PUCRA_PU9_Msk (0x1UL << PWR_PUCRA_PU9_Pos)

#define	PWR_PUCRA_PU9 PWR_PUCRA_PU9_Msk

#define	PWR_PUCRA_PU10_Pos (10U)

#define	PWR_PUCRA_PU10_Msk (0x1UL << PWR_PUCRA_PU10_Pos)

#define	PWR_PUCRA_PU10 PWR_PUCRA_PU10_Msk

#define	PWR_PUCRA_PU11_Pos (11U)

#define	PWR_PUCRA_PU11_Msk (0x1UL << PWR_PUCRA_PU11_Pos)

#define	PWR_PUCRA_PU11 PWR_PUCRA_PU11_Msk

#define	PWR_PUCRA_PU12_Pos (12U)

#define	PWR_PUCRA_PU12_Msk (0x1UL << PWR_PUCRA_PU12_Pos)

#define	PWR_PUCRA_PU12 PWR_PUCRA_PU12_Msk

#define	PWR_PUCRA_PU13_Pos (13U)

#define	PWR_PUCRA_PU13_Msk (0x1UL << PWR_PUCRA_PU13_Pos)

#define	PWR_PUCRA_PU13 PWR_PUCRA_PU13_Msk

#define	PWR_PUCRA_PU14_Pos (14U)

#define	PWR_PUCRA_PU14_Msk (0x1UL << PWR_PUCRA_PU14_Pos)

#define	PWR_PUCRA_PU14 PWR_PUCRA_PU14_Msk

#define	PWR_PUCRA_PU15_Pos (15U)

#define	PWR_PUCRA_PU15_Msk (0x1UL << PWR_PUCRA_PU15_Pos)

#define	PWR_PUCRA_PU15 PWR_PUCRA_PU15_Msk

#define	PWR_PDCRA_PD0_Pos (0U)

#define	PWR_PDCRA_PD0_Msk (0x1UL << PWR_PDCRA_PD0_Pos)

#define	PWR_PDCRA_PD0 PWR_PDCRA_PD0_Msk

#define	PWR_PDCRA_PD1_Pos (1U)

#define	PWR_PDCRA_PD1_Msk (0x1UL << PWR_PDCRA_PD1_Pos)

#define	PWR_PDCRA_PD1 PWR_PDCRA_PD1_Msk

#define	PWR_PDCRA_PD2_Pos (2U)

#define	PWR_PDCRA_PD2_Msk (0x1UL << PWR_PDCRA_PD2_Pos)

#define	PWR_PDCRA_PD2 PWR_PDCRA_PD2_Msk

#define	PWR_PDCRA_PD3_Pos (3U)

#define	PWR_PDCRA_PD3_Msk (0x1UL << PWR_PDCRA_PD3_Pos)

#define	PWR_PDCRA_PD3 PWR_PDCRA_PD3_Msk

#define	PWR_PDCRA_PD4_Pos (4U)

#define	PWR_PDCRA_PD4_Msk (0x1UL << PWR_PDCRA_PD4_Pos)

#define	PWR_PDCRA_PD4 PWR_PDCRA_PD4_Msk

#define	PWR_PDCRA_PD5_Pos (5U)

#define	PWR_PDCRA_PD5_Msk (0x1UL << PWR_PDCRA_PD5_Pos)

#define	PWR_PDCRA_PD5 PWR_PDCRA_PD5_Msk

#define	PWR_PDCRA_PD6_Pos (6U)

#define	PWR_PDCRA_PD6_Msk (0x1UL << PWR_PDCRA_PD6_Pos)

#define	PWR_PDCRA_PD6 PWR_PDCRA_PD6_Msk

#define	PWR_PDCRA_PD7_Pos (7U)

#define	PWR_PDCRA_PD7_Msk (0x1UL << PWR_PDCRA_PD7_Pos)

#define	PWR_PDCRA_PD7 PWR_PDCRA_PD7_Msk

#define	PWR_PDCRA_PD8_Pos (8U)

#define	PWR_PDCRA_PD8_Msk (0x1UL << PWR_PDCRA_PD8_Pos)

#define	PWR_PDCRA_PD8 PWR_PDCRA_PD8_Msk

#define	PWR_PDCRA_PD9_Pos (9U)

#define	PWR_PDCRA_PD9_Msk (0x1UL << PWR_PDCRA_PD9_Pos)

#define	PWR_PDCRA_PD9 PWR_PDCRA_PD9_Msk

#define	PWR_PDCRA_PD10_Pos (10U)

#define	PWR_PDCRA_PD10_Msk (0x1UL << PWR_PDCRA_PD10_Pos)

#define	PWR_PDCRA_PD10 PWR_PDCRA_PD10_Msk

#define	PWR_PDCRA_PD11_Pos (11U)

#define	PWR_PDCRA_PD11_Msk (0x1UL << PWR_PDCRA_PD11_Pos)

#define	PWR_PDCRA_PD11 PWR_PDCRA_PD11_Msk

#define	PWR_PDCRA_PD12_Pos (12U)

#define	PWR_PDCRA_PD12_Msk (0x1UL << PWR_PDCRA_PD12_Pos)

#define	PWR_PDCRA_PD12 PWR_PDCRA_PD12_Msk

#define	PWR_PDCRA_PD13_Pos (13U)

#define	PWR_PDCRA_PD13_Msk (0x1UL << PWR_PDCRA_PD13_Pos)

#define	PWR_PDCRA_PD13 PWR_PDCRA_PD13_Msk

#define	PWR_PDCRA_PD14_Pos (14U)

#define	PWR_PDCRA_PD14_Msk (0x1UL << PWR_PDCRA_PD14_Pos)

#define	PWR_PDCRA_PD14 PWR_PDCRA_PD14_Msk

#define	PWR_PDCRA_PD15_Pos (15U)

#define	PWR_PDCRA_PD15_Msk (0x1UL << PWR_PDCRA_PD15_Pos)

#define	PWR_PDCRA_PD15 PWR_PDCRA_PD15_Msk

#define	PWR_PUCRB_PU0_Pos (0U)

#define	PWR_PUCRB_PU0_Msk (0x1UL << PWR_PUCRB_PU0_Pos)

#define	PWR_PUCRB_PU0 PWR_PUCRB_PU0_Msk

#define	PWR_PUCRB_PU1_Pos (1U)

#define	PWR_PUCRB_PU1_Msk (0x1UL << PWR_PUCRB_PU1_Pos)

#define	PWR_PUCRB_PU1 PWR_PUCRB_PU1_Msk

#define	PWR_PUCRB_PU2_Pos (2U)

#define	PWR_PUCRB_PU2_Msk (0x1UL << PWR_PUCRB_PU2_Pos)

#define	PWR_PUCRB_PU2 PWR_PUCRB_PU2_Msk

#define	PWR_PUCRB_PU3_Pos (3U)

#define	PWR_PUCRB_PU3_Msk (0x1UL << PWR_PUCRB_PU3_Pos)

#define	PWR_PUCRB_PU3 PWR_PUCRB_PU3_Msk

#define	PWR_PUCRB_PU4_Pos (4U)

#define	PWR_PUCRB_PU4_Msk (0x1UL << PWR_PUCRB_PU4_Pos)

#define	PWR_PUCRB_PU4 PWR_PUCRB_PU4_Msk

#define	PWR_PUCRB_PU5_Pos (5U)

#define	PWR_PUCRB_PU5_Msk (0x1UL << PWR_PUCRB_PU5_Pos)

#define	PWR_PUCRB_PU5 PWR_PUCRB_PU5_Msk

#define	PWR_PUCRB_PU6_Pos (6U)

#define	PWR_PUCRB_PU6_Msk (0x1UL << PWR_PUCRB_PU6_Pos)

#define	PWR_PUCRB_PU6 PWR_PUCRB_PU6_Msk

#define	PWR_PUCRB_PU7_Pos (7U)

#define	PWR_PUCRB_PU7_Msk (0x1UL << PWR_PUCRB_PU7_Pos)

#define	PWR_PUCRB_PU7 PWR_PUCRB_PU7_Msk

#define	PWR_PUCRB_PU8_Pos (8U)

#define	PWR_PUCRB_PU8_Msk (0x1UL << PWR_PUCRB_PU8_Pos)

#define	PWR_PUCRB_PU8 PWR_PUCRB_PU8_Msk

#define	PWR_PUCRB_PU9_Pos (9U)

#define	PWR_PUCRB_PU9_Msk (0x1UL << PWR_PUCRB_PU9_Pos)

#define	PWR_PUCRB_PU9 PWR_PUCRB_PU9_Msk

#define	PWR_PUCRB_PU10_Pos (10U)

#define	PWR_PUCRB_PU10_Msk (0x1UL << PWR_PUCRB_PU10_Pos)

#define	PWR_PUCRB_PU10 PWR_PUCRB_PU10_Msk

#define	PWR_PUCRB_PU11_Pos (11U)

#define	PWR_PUCRB_PU11_Msk (0x1UL << PWR_PUCRB_PU11_Pos)

#define	PWR_PUCRB_PU11 PWR_PUCRB_PU11_Msk

#define	PWR_PUCRB_PU12_Pos (12U)

#define	PWR_PUCRB_PU12_Msk (0x1UL << PWR_PUCRB_PU12_Pos)

#define	PWR_PUCRB_PU12 PWR_PUCRB_PU12_Msk

#define	PWR_PUCRB_PU13_Pos (13U)

#define	PWR_PUCRB_PU13_Msk (0x1UL << PWR_PUCRB_PU13_Pos)

#define	PWR_PUCRB_PU13 PWR_PUCRB_PU13_Msk

#define	PWR_PUCRB_PU14_Pos (14U)

#define	PWR_PUCRB_PU14_Msk (0x1UL << PWR_PUCRB_PU14_Pos)

#define	PWR_PUCRB_PU14 PWR_PUCRB_PU14_Msk

#define	PWR_PUCRB_PU15_Pos (15U)

#define	PWR_PUCRB_PU15_Msk (0x1UL << PWR_PUCRB_PU15_Pos)

#define	PWR_PUCRB_PU15 PWR_PUCRB_PU15_Msk

#define	PWR_PDCRB_PD0_Pos (0U)

#define	PWR_PDCRB_PD0_Msk (0x1UL << PWR_PDCRB_PD0_Pos)

#define	PWR_PDCRB_PD0 PWR_PDCRB_PD0_Msk

#define	PWR_PDCRB_PD1_Pos (1U)

#define	PWR_PDCRB_PD1_Msk (0x1UL << PWR_PDCRB_PD1_Pos)

#define	PWR_PDCRB_PD1 PWR_PDCRB_PD1_Msk

#define	PWR_PDCRB_PD2_Pos (2U)

#define	PWR_PDCRB_PD2_Msk (0x1UL << PWR_PDCRB_PD2_Pos)

#define	PWR_PDCRB_PD2 PWR_PDCRB_PD2_Msk

#define	PWR_PDCRB_PD3_Pos (3U)

#define	PWR_PDCRB_PD3_Msk (0x1UL << PWR_PDCRB_PD3_Pos)

#define	PWR_PDCRB_PD3 PWR_PDCRB_PD3_Msk

#define	PWR_PDCRB_PD4_Pos (4U)

#define	PWR_PDCRB_PD4_Msk (0x1UL << PWR_PDCRB_PD4_Pos)

#define	PWR_PDCRB_PD4 PWR_PDCRB_PD4_Msk

#define	PWR_PDCRB_PD5_Pos (5U)

#define	PWR_PDCRB_PD5_Msk (0x1UL << PWR_PDCRB_PD5_Pos)

#define	PWR_PDCRB_PD5 PWR_PDCRB_PD5_Msk

#define	PWR_PDCRB_PD6_Pos (6U)

#define	PWR_PDCRB_PD6_Msk (0x1UL << PWR_PDCRB_PD6_Pos)

#define	PWR_PDCRB_PD6 PWR_PDCRB_PD6_Msk

#define	PWR_PDCRB_PD7_Pos (7U)

#define	PWR_PDCRB_PD7_Msk (0x1UL << PWR_PDCRB_PD7_Pos)

#define	PWR_PDCRB_PD7 PWR_PDCRB_PD7_Msk

#define	PWR_PDCRB_PD8_Pos (8U)

#define	PWR_PDCRB_PD8_Msk (0x1UL << PWR_PDCRB_PD8_Pos)

#define	PWR_PDCRB_PD8 PWR_PDCRB_PD8_Msk

#define	PWR_PDCRB_PD9_Pos (9U)

#define	PWR_PDCRB_PD9_Msk (0x1UL << PWR_PDCRB_PD9_Pos)

#define	PWR_PDCRB_PD9 PWR_PDCRB_PD9_Msk

#define	PWR_PDCRB_PD10_Pos (10U)

#define	PWR_PDCRB_PD10_Msk (0x1UL << PWR_PDCRB_PD10_Pos)

#define	PWR_PDCRB_PD10 PWR_PDCRB_PD10_Msk

#define	PWR_PDCRB_PD11_Pos (11U)

#define	PWR_PDCRB_PD11_Msk (0x1UL << PWR_PDCRB_PD11_Pos)

#define	PWR_PDCRB_PD11 PWR_PDCRB_PD11_Msk

#define	PWR_PDCRB_PD12_Pos (12U)

#define	PWR_PDCRB_PD12_Msk (0x1UL << PWR_PDCRB_PD12_Pos)

#define	PWR_PDCRB_PD12 PWR_PDCRB_PD12_Msk

#define	PWR_PDCRB_PD13_Pos (13U)

#define	PWR_PDCRB_PD13_Msk (0x1UL << PWR_PDCRB_PD13_Pos)

#define	PWR_PDCRB_PD13 PWR_PDCRB_PD13_Msk

#define	PWR_PDCRB_PD14_Pos (14U)

#define	PWR_PDCRB_PD14_Msk (0x1UL << PWR_PDCRB_PD14_Pos)

#define	PWR_PDCRB_PD14 PWR_PDCRB_PD14_Msk

#define	PWR_PDCRB_PD15_Pos (15U)

#define	PWR_PDCRB_PD15_Msk (0x1UL << PWR_PDCRB_PD15_Pos)

#define	PWR_PDCRB_PD15 PWR_PDCRB_PD15_Msk

#define	PWR_PUCRC_PU6_Pos (6U)

#define	PWR_PUCRC_PU6_Msk (0x1UL << PWR_PUCRC_PU6_Pos)

#define	PWR_PUCRC_PU6 PWR_PUCRC_PU6_Msk

#define	PWR_PUCRC_PU7_Pos (7U)

#define	PWR_PUCRC_PU7_Msk (0x1UL << PWR_PUCRC_PU7_Pos)

#define	PWR_PUCRC_PU7 PWR_PUCRC_PU7_Msk

#define	PWR_PUCRC_PU13_Pos (13U)

#define	PWR_PUCRC_PU13_Msk (0x1UL << PWR_PUCRC_PU13_Pos)

#define	PWR_PUCRC_PU13 PWR_PUCRC_PU13_Msk

#define	PWR_PUCRC_PU14_Pos (14U)

#define	PWR_PUCRC_PU14_Msk (0x1UL << PWR_PUCRC_PU14_Pos)

#define	PWR_PUCRC_PU14 PWR_PUCRC_PU14_Msk

#define	PWR_PUCRC_PU15_Pos (15U)

#define	PWR_PUCRC_PU15_Msk (0x1UL << PWR_PUCRC_PU15_Pos)

#define	PWR_PUCRC_PU15 PWR_PUCRC_PU15_Msk

#define	PWR_PDCRC_PD6_Pos (6U)

#define	PWR_PDCRC_PD6_Msk (0x1UL << PWR_PDCRC_PD6_Pos)

#define	PWR_PDCRC_PD6 PWR_PDCRC_PD6_Msk

#define	PWR_PDCRC_PD7_Pos (7U)

#define	PWR_PDCRC_PD7_Msk (0x1UL << PWR_PDCRC_PD7_Pos)

#define	PWR_PDCRC_PD7 PWR_PDCRC_PD7_Msk

#define	PWR_PDCRC_PD13_Pos (13U)

#define	PWR_PDCRC_PD13_Msk (0x1UL << PWR_PDCRC_PD13_Pos)

#define	PWR_PDCRC_PD13 PWR_PDCRC_PD13_Msk

#define	PWR_PDCRC_PD14_Pos (14U)

#define	PWR_PDCRC_PD14_Msk (0x1UL << PWR_PDCRC_PD14_Pos)

#define	PWR_PDCRC_PD14 PWR_PDCRC_PD14_Msk

#define	PWR_PDCRC_PD15_Pos (15U)

#define	PWR_PDCRC_PD15_Msk (0x1UL << PWR_PDCRC_PD15_Pos)

#define	PWR_PDCRC_PD15 PWR_PDCRC_PD15_Msk

#define	PWR_PUCRD_PU0_Pos (0U)

#define	PWR_PUCRD_PU0_Msk (0x1UL << PWR_PUCRD_PU0_Pos)

#define	PWR_PUCRD_PU0 PWR_PUCRD_PU0_Msk

#define	PWR_PUCRD_PU1_Pos (1U)

#define	PWR_PUCRD_PU1_Msk (0x1UL << PWR_PUCRD_PU1_Pos)

#define	PWR_PUCRD_PU1 PWR_PUCRD_PU1_Msk

#define	PWR_PUCRD_PU2_Pos (2U)

#define	PWR_PUCRD_PU2_Msk (0x1UL << PWR_PUCRD_PU2_Pos)

#define	PWR_PUCRD_PU2 PWR_PUCRD_PU2_Msk

#define	PWR_PUCRD_PU3_Pos (3U)

#define	PWR_PUCRD_PU3_Msk (0x1UL << PWR_PUCRD_PU3_Pos)

#define	PWR_PUCRD_PU3 PWR_PUCRD_PU3_Msk

#define	PWR_PDCRD_PD0_Pos (0U)

#define	PWR_PDCRD_PD0_Msk (0x1UL << PWR_PDCRD_PD0_Pos)

#define	PWR_PDCRD_PD0 PWR_PDCRD_PD0_Msk

#define	PWR_PDCRD_PD1_Pos (1U)

#define	PWR_PDCRD_PD1_Msk (0x1UL << PWR_PDCRD_PD1_Pos)

#define	PWR_PDCRD_PD1 PWR_PDCRD_PD1_Msk

#define	PWR_PDCRD_PD2_Pos (2U)

#define	PWR_PDCRD_PD2_Msk (0x1UL << PWR_PDCRD_PD2_Pos)

#define	PWR_PDCRD_PD2 PWR_PDCRD_PD2_Msk

#define	PWR_PDCRD_PD3_Pos (3U)

#define	PWR_PDCRD_PD3_Msk (0x1UL << PWR_PDCRD_PD3_Pos)

#define	PWR_PDCRD_PD3 PWR_PDCRD_PD3_Msk

#define	PWR_PUCRF_PU0_Pos (0U)

#define	PWR_PUCRF_PU0_Msk (0x1UL << PWR_PUCRF_PU0_Pos)

#define	PWR_PUCRF_PU0 PWR_PUCRF_PU0_Msk

#define	PWR_PUCRF_PU1_Pos (1U)

#define	PWR_PUCRF_PU1_Msk (0x1UL << PWR_PUCRF_PU1_Pos)

#define	PWR_PUCRF_PU1 PWR_PUCRF_PU1_Msk

#define	PWR_PUCRF_PU2_Pos (2U)

#define	PWR_PUCRF_PU2_Msk (0x1UL << PWR_PUCRF_PU2_Pos)

#define	PWR_PUCRF_PU2 PWR_PUCRF_PU2_Msk

#define	PWR_PDCRF_PD0_Pos (0U)

#define	PWR_PDCRF_PD0_Msk (0x1UL << PWR_PDCRF_PD0_Pos)

#define	PWR_PDCRF_PD0 PWR_PDCRF_PD0_Msk

#define	PWR_PDCRF_PD1_Pos (1U)

#define	PWR_PDCRF_PD1_Msk (0x1UL << PWR_PDCRF_PD1_Pos)

#define	PWR_PDCRF_PD1 PWR_PDCRF_PD1_Msk

#define	PWR_PDCRF_PD2_Pos (2U)

#define	PWR_PDCRF_PD2_Msk (0x1UL << PWR_PDCRF_PD2_Pos)

#define	PWR_PDCRF_PD2 PWR_PDCRF_PD2_Msk

#define	RCC_CR_HSION_Pos (8U)

#define	RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos)

#define	RCC_CR_HSION RCC_CR_HSION_Msk

#define	RCC_CR_HSIKERON_Pos (9U)

#define	RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos)

#define	RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk

#define	RCC_CR_HSIRDY_Pos (10U)

#define	RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)

#define	RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk

#define	RCC_CR_HSIDIV_Pos (11U)

#define	RCC_CR_HSIDIV_Msk (0x7UL << RCC_CR_HSIDIV_Pos)

#define	RCC_CR_HSIDIV RCC_CR_HSIDIV_Msk

#define	RCC_CR_HSIDIV_0 (0x1UL << RCC_CR_HSIDIV_Pos)

#define	RCC_CR_HSIDIV_1 (0x2UL << RCC_CR_HSIDIV_Pos)

#define	RCC_CR_HSIDIV_2 (0x4UL << RCC_CR_HSIDIV_Pos)

#define	RCC_CR_HSEON_Pos (16U)

#define	RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)

#define	RCC_CR_HSEON RCC_CR_HSEON_Msk

#define	RCC_CR_HSERDY_Pos (17U)

#define	RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)

#define	RCC_CR_HSERDY RCC_CR_HSERDY_Msk

#define	RCC_CR_HSEBYP_Pos (18U)

#define	RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos)

#define	RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk

#define	RCC_CR_CSSON_Pos (19U)

#define	RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos)

#define	RCC_CR_CSSON RCC_CR_CSSON_Msk

#define	RCC_CR_PLLON_Pos (24U)

#define	RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)

#define	RCC_CR_PLLON RCC_CR_PLLON_Msk

#define	RCC_CR_PLLRDY_Pos (25U)

#define	RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)

#define	RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk

#define	RCC_ICSCR_HSICAL_Pos (0U)

#define	RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos)

#define	RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk

#define	RCC_ICSCR_HSICAL_0 (0x01UL << RCC_ICSCR_HSICAL_Pos)

#define	RCC_ICSCR_HSICAL_1 (0x02UL << RCC_ICSCR_HSICAL_Pos)

#define	RCC_ICSCR_HSICAL_2 (0x04UL << RCC_ICSCR_HSICAL_Pos)

#define	RCC_ICSCR_HSICAL_3 (0x08UL << RCC_ICSCR_HSICAL_Pos)

#define	RCC_ICSCR_HSICAL_4 (0x10UL << RCC_ICSCR_HSICAL_Pos)

#define	RCC_ICSCR_HSICAL_5 (0x20UL << RCC_ICSCR_HSICAL_Pos)

#define	RCC_ICSCR_HSICAL_6 (0x40UL << RCC_ICSCR_HSICAL_Pos)

#define	RCC_ICSCR_HSICAL_7 (0x80UL << RCC_ICSCR_HSICAL_Pos)

#define	RCC_ICSCR_HSITRIM_Pos (8U)

#define	RCC_ICSCR_HSITRIM_Msk (0x7FUL << RCC_ICSCR_HSITRIM_Pos)

#define	RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk

#define	RCC_ICSCR_HSITRIM_0 (0x01UL << RCC_ICSCR_HSITRIM_Pos)

#define	RCC_ICSCR_HSITRIM_1 (0x02UL << RCC_ICSCR_HSITRIM_Pos)

#define	RCC_ICSCR_HSITRIM_2 (0x04UL << RCC_ICSCR_HSITRIM_Pos)

#define	RCC_ICSCR_HSITRIM_3 (0x08UL << RCC_ICSCR_HSITRIM_Pos)

#define	RCC_ICSCR_HSITRIM_4 (0x10UL << RCC_ICSCR_HSITRIM_Pos)

#define	RCC_ICSCR_HSITRIM_5 (0x20UL << RCC_ICSCR_HSITRIM_Pos)

#define	RCC_ICSCR_HSITRIM_6 (0x40UL << RCC_ICSCR_HSITRIM_Pos)

#define	RCC_CFGR_SW_Pos (0U)

#define	RCC_CFGR_SW_Msk (0x7UL << RCC_CFGR_SW_Pos)

#define	RCC_CFGR_SW RCC_CFGR_SW_Msk

#define	RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)

#define	RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)

#define	RCC_CFGR_SW_2 (0x4UL << RCC_CFGR_SW_Pos)

#define	RCC_CFGR_SWS_Pos (3U)

#define	RCC_CFGR_SWS_Msk (0x7UL << RCC_CFGR_SWS_Pos)

#define	RCC_CFGR_SWS RCC_CFGR_SWS_Msk

#define	RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)

#define	RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)

#define	RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos)

#define	RCC_CFGR_HPRE_Pos (8U)

#define	RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos)

#define	RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk

#define	RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos)

#define	RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos)

#define	RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos)

#define	RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos)

#define	RCC_CFGR_PPRE_Pos (12U)

#define	RCC_CFGR_PPRE_Msk (0x7UL << RCC_CFGR_PPRE_Pos)

#define	RCC_CFGR_PPRE RCC_CFGR_PPRE_Msk

#define	RCC_CFGR_PPRE_0 (0x1UL << RCC_CFGR_PPRE_Pos)

#define	RCC_CFGR_PPRE_1 (0x2UL << RCC_CFGR_PPRE_Pos)

#define	RCC_CFGR_PPRE_2 (0x4UL << RCC_CFGR_PPRE_Pos)

#define	RCC_CFGR_MCOSEL_Pos (24U)

#define	RCC_CFGR_MCOSEL_Msk (0x7UL << RCC_CFGR_MCOSEL_Pos)

#define	RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk

#define	RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos)

#define	RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos)

#define	RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos)

#define	RCC_CFGR_MCOPRE_Pos (28U)

#define	RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos)

#define	RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk

#define	RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos)

#define	RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos)

#define	RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos)

#define	RCC_PLLCFGR_PLLSRC_Pos (0U)

#define	RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos)

#define	RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk

#define	RCC_PLLCFGR_PLLSRC_0 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)

#define	RCC_PLLCFGR_PLLSRC_1 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos)

#define	RCC_PLLCFGR_PLLSRC_NONE (0x00000000UL)

#define	RCC_PLLCFGR_PLLSRC_HSI_Pos (1U)

#define	RCC_PLLCFGR_PLLSRC_HSI_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSI_Pos)

#define	RCC_PLLCFGR_PLLSRC_HSI RCC_PLLCFGR_PLLSRC_HSI_Msk

#define	RCC_PLLCFGR_PLLSRC_HSE_Pos (0U)

#define	RCC_PLLCFGR_PLLSRC_HSE_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)

#define	RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk

#define	RCC_PLLCFGR_PLLM_Pos (4U)

#define	RCC_PLLCFGR_PLLM_Msk (0x7UL << RCC_PLLCFGR_PLLM_Pos)

#define	RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk

#define	RCC_PLLCFGR_PLLM_0 (0x1UL << RCC_PLLCFGR_PLLM_Pos)

#define	RCC_PLLCFGR_PLLM_1 (0x2UL << RCC_PLLCFGR_PLLM_Pos)

#define	RCC_PLLCFGR_PLLM_2 (0x4UL << RCC_PLLCFGR_PLLM_Pos)

#define	RCC_PLLCFGR_PLLN_Pos (8U)

#define	RCC_PLLCFGR_PLLN_Msk (0x7FUL << RCC_PLLCFGR_PLLN_Pos)

#define	RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk

#define	RCC_PLLCFGR_PLLN_0 (0x01UL << RCC_PLLCFGR_PLLN_Pos)

#define	RCC_PLLCFGR_PLLN_1 (0x02UL << RCC_PLLCFGR_PLLN_Pos)

#define	RCC_PLLCFGR_PLLN_2 (0x04UL << RCC_PLLCFGR_PLLN_Pos)

#define	RCC_PLLCFGR_PLLN_3 (0x08UL << RCC_PLLCFGR_PLLN_Pos)

#define	RCC_PLLCFGR_PLLN_4 (0x10UL << RCC_PLLCFGR_PLLN_Pos)

#define	RCC_PLLCFGR_PLLN_5 (0x20UL << RCC_PLLCFGR_PLLN_Pos)

#define	RCC_PLLCFGR_PLLN_6 (0x40UL << RCC_PLLCFGR_PLLN_Pos)

#define	RCC_PLLCFGR_PLLPEN_Pos (16U)

#define	RCC_PLLCFGR_PLLPEN_Msk (0x1UL << RCC_PLLCFGR_PLLPEN_Pos)

#define	RCC_PLLCFGR_PLLPEN RCC_PLLCFGR_PLLPEN_Msk

#define	RCC_PLLCFGR_PLLP_Pos (17U)

#define	RCC_PLLCFGR_PLLP_Msk (0x1FUL << RCC_PLLCFGR_PLLP_Pos)

#define	RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk

#define	RCC_PLLCFGR_PLLP_0 (0x01UL << RCC_PLLCFGR_PLLP_Pos)

#define	RCC_PLLCFGR_PLLP_1 (0x02UL << RCC_PLLCFGR_PLLP_Pos)

#define	RCC_PLLCFGR_PLLP_2 (0x04UL << RCC_PLLCFGR_PLLP_Pos)

#define	RCC_PLLCFGR_PLLP_3 (0x08UL << RCC_PLLCFGR_PLLP_Pos)

#define	RCC_PLLCFGR_PLLP_4 (0x10UL << RCC_PLLCFGR_PLLP_Pos)

#define	RCC_PLLCFGR_PLLREN_Pos (28U)

#define	RCC_PLLCFGR_PLLREN_Msk (0x1UL << RCC_PLLCFGR_PLLREN_Pos)

#define	RCC_PLLCFGR_PLLREN RCC_PLLCFGR_PLLREN_Msk

#define	RCC_PLLCFGR_PLLR_Pos (29U)

#define	RCC_PLLCFGR_PLLR_Msk (0x7UL << RCC_PLLCFGR_PLLR_Pos)

#define	RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk

#define	RCC_PLLCFGR_PLLR_0 (0x1UL << RCC_PLLCFGR_PLLR_Pos)

#define	RCC_PLLCFGR_PLLR_1 (0x2UL << RCC_PLLCFGR_PLLR_Pos)

#define	RCC_PLLCFGR_PLLR_2 (0x4UL << RCC_PLLCFGR_PLLR_Pos)

#define	RCC_CIER_LSIRDYIE_Pos (0U)

#define	RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos)

#define	RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk

#define	RCC_CIER_LSERDYIE_Pos (1U)

#define	RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos)

#define	RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk

#define	RCC_CIER_HSIRDYIE_Pos (3U)

#define	RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos)

#define	RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk

#define	RCC_CIER_HSERDYIE_Pos (4U)

#define	RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos)

#define	RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk

#define	RCC_CIER_PLLRDYIE_Pos (5U)

#define	RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos)

#define	RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk

#define	RCC_CIFR_LSIRDYF_Pos (0U)

#define	RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos)

#define	RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk

#define	RCC_CIFR_LSERDYF_Pos (1U)

#define	RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos)

#define	RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk

#define	RCC_CIFR_HSIRDYF_Pos (3U)

#define	RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos)

#define	RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk

#define	RCC_CIFR_HSERDYF_Pos (4U)

#define	RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos)

#define	RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk

#define	RCC_CIFR_PLLRDYF_Pos (5U)

#define	RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos)

#define	RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk

#define	RCC_CIFR_CSSF_Pos (8U)

#define	RCC_CIFR_CSSF_Msk (0x1UL << RCC_CIFR_CSSF_Pos)

#define	RCC_CIFR_CSSF RCC_CIFR_CSSF_Msk

#define	RCC_CIFR_LSECSSF_Pos (9U)

#define	RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos)

#define	RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk

#define	RCC_CICR_LSIRDYC_Pos (0U)

#define	RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos)

#define	RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk

#define	RCC_CICR_LSERDYC_Pos (1U)

#define	RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos)

#define	RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk

#define	RCC_CICR_HSIRDYC_Pos (3U)

#define	RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos)

#define	RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk

#define	RCC_CICR_HSERDYC_Pos (4U)

#define	RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos)

#define	RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk

#define	RCC_CICR_PLLRDYC_Pos (5U)

#define	RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos)

#define	RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk

#define	RCC_CICR_CSSC_Pos (8U)

#define	RCC_CICR_CSSC_Msk (0x1UL << RCC_CICR_CSSC_Pos)

#define	RCC_CICR_CSSC RCC_CICR_CSSC_Msk

#define	RCC_CICR_LSECSSC_Pos (9U)

#define	RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos)

#define	RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk

#define	RCC_IOPRSTR_GPIOARST_Pos (0U)

#define	RCC_IOPRSTR_GPIOARST_Msk (0x1UL << RCC_IOPRSTR_GPIOARST_Pos)

#define	RCC_IOPRSTR_GPIOARST RCC_IOPRSTR_GPIOARST_Msk

#define	RCC_IOPRSTR_GPIOBRST_Pos (1U)

#define	RCC_IOPRSTR_GPIOBRST_Msk (0x1UL << RCC_IOPRSTR_GPIOBRST_Pos)

#define	RCC_IOPRSTR_GPIOBRST RCC_IOPRSTR_GPIOBRST_Msk

#define	RCC_IOPRSTR_GPIOCRST_Pos (2U)

#define	RCC_IOPRSTR_GPIOCRST_Msk (0x1UL << RCC_IOPRSTR_GPIOCRST_Pos)

#define	RCC_IOPRSTR_GPIOCRST RCC_IOPRSTR_GPIOCRST_Msk

#define	RCC_IOPRSTR_GPIODRST_Pos (3U)

#define	RCC_IOPRSTR_GPIODRST_Msk (0x1UL << RCC_IOPRSTR_GPIODRST_Pos)

#define	RCC_IOPRSTR_GPIODRST RCC_IOPRSTR_GPIODRST_Msk

#define	RCC_IOPRSTR_GPIOFRST_Pos (5U)

#define	RCC_IOPRSTR_GPIOFRST_Msk (0x1UL << RCC_IOPRSTR_GPIOFRST_Pos)

#define	RCC_IOPRSTR_GPIOFRST RCC_IOPRSTR_GPIOFRST_Msk

#define	RCC_AHBRSTR_DMA1RST_Pos (0U)

#define	RCC_AHBRSTR_DMA1RST_Msk (0x1UL << RCC_AHBRSTR_DMA1RST_Pos)

#define	RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMA1RST_Msk

#define	RCC_AHBRSTR_FLASHRST_Pos (8U)

#define	RCC_AHBRSTR_FLASHRST_Msk (0x1UL << RCC_AHBRSTR_FLASHRST_Pos)

#define	RCC_AHBRSTR_FLASHRST RCC_AHBRSTR_FLASHRST_Msk

#define	RCC_AHBRSTR_CRCRST_Pos (12U)

#define	RCC_AHBRSTR_CRCRST_Msk (0x1UL << RCC_AHBRSTR_CRCRST_Pos)

#define	RCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_Msk

#define	RCC_APBRSTR1_TIM3RST_Pos (1U)

#define	RCC_APBRSTR1_TIM3RST_Msk (0x1UL << RCC_APBRSTR1_TIM3RST_Pos)

#define	RCC_APBRSTR1_TIM3RST RCC_APBRSTR1_TIM3RST_Msk

#define	RCC_APBRSTR1_SPI2RST_Pos (14U)

#define	RCC_APBRSTR1_SPI2RST_Msk (0x1UL << RCC_APBRSTR1_SPI2RST_Pos)

#define	RCC_APBRSTR1_SPI2RST RCC_APBRSTR1_SPI2RST_Msk

#define	RCC_APBRSTR1_USART2RST_Pos (17U)

#define	RCC_APBRSTR1_USART2RST_Msk (0x1UL << RCC_APBRSTR1_USART2RST_Pos)

#define	RCC_APBRSTR1_USART2RST RCC_APBRSTR1_USART2RST_Msk

#define	RCC_APBRSTR1_I2C1RST_Pos (21U)

#define	RCC_APBRSTR1_I2C1RST_Msk (0x1UL << RCC_APBRSTR1_I2C1RST_Pos)

#define	RCC_APBRSTR1_I2C1RST RCC_APBRSTR1_I2C1RST_Msk

#define	RCC_APBRSTR1_I2C2RST_Pos (22U)

#define	RCC_APBRSTR1_I2C2RST_Msk (0x1UL << RCC_APBRSTR1_I2C2RST_Pos)

#define	RCC_APBRSTR1_I2C2RST RCC_APBRSTR1_I2C2RST_Msk

#define	RCC_APBRSTR1_DBGRST_Pos (27U)

#define	RCC_APBRSTR1_DBGRST_Msk (0x1UL << RCC_APBRSTR1_DBGRST_Pos)

#define	RCC_APBRSTR1_DBGRST RCC_APBRSTR1_DBGRST_Msk

#define	RCC_APBRSTR1_PWRRST_Pos (28U)

#define	RCC_APBRSTR1_PWRRST_Msk (0x1UL << RCC_APBRSTR1_PWRRST_Pos)

#define	RCC_APBRSTR1_PWRRST RCC_APBRSTR1_PWRRST_Msk

#define	RCC_APBRSTR2_SYSCFGRST_Pos (0U)

#define	RCC_APBRSTR2_SYSCFGRST_Msk (0x1UL << RCC_APBRSTR2_SYSCFGRST_Pos)

#define	RCC_APBRSTR2_SYSCFGRST RCC_APBRSTR2_SYSCFGRST_Msk

#define	RCC_APBRSTR2_TIM1RST_Pos (11U)

#define	RCC_APBRSTR2_TIM1RST_Msk (0x1UL << RCC_APBRSTR2_TIM1RST_Pos)

#define	RCC_APBRSTR2_TIM1RST RCC_APBRSTR2_TIM1RST_Msk

#define	RCC_APBRSTR2_SPI1RST_Pos (12U)

#define	RCC_APBRSTR2_SPI1RST_Msk (0x1UL << RCC_APBRSTR2_SPI1RST_Pos)

#define	RCC_APBRSTR2_SPI1RST RCC_APBRSTR2_SPI1RST_Msk

#define	RCC_APBRSTR2_USART1RST_Pos (14U)

#define	RCC_APBRSTR2_USART1RST_Msk (0x1UL << RCC_APBRSTR2_USART1RST_Pos)

#define	RCC_APBRSTR2_USART1RST RCC_APBRSTR2_USART1RST_Msk

#define	RCC_APBRSTR2_TIM14RST_Pos (15U)

#define	RCC_APBRSTR2_TIM14RST_Msk (0x1UL << RCC_APBRSTR2_TIM14RST_Pos)

#define	RCC_APBRSTR2_TIM14RST RCC_APBRSTR2_TIM14RST_Msk

#define	RCC_APBRSTR2_TIM16RST_Pos (17U)

#define	RCC_APBRSTR2_TIM16RST_Msk (0x1UL << RCC_APBRSTR2_TIM16RST_Pos)

#define	RCC_APBRSTR2_TIM16RST RCC_APBRSTR2_TIM16RST_Msk

#define	RCC_APBRSTR2_TIM17RST_Pos (18U)

#define	RCC_APBRSTR2_TIM17RST_Msk (0x1UL << RCC_APBRSTR2_TIM17RST_Pos)

#define	RCC_APBRSTR2_TIM17RST RCC_APBRSTR2_TIM17RST_Msk

#define	RCC_APBRSTR2_ADCRST_Pos (20U)

#define	RCC_APBRSTR2_ADCRST_Msk (0x1UL << RCC_APBRSTR2_ADCRST_Pos)

#define	RCC_APBRSTR2_ADCRST RCC_APBRSTR2_ADCRST_Msk

#define	RCC_IOPENR_GPIOAEN_Pos (0U)

#define	RCC_IOPENR_GPIOAEN_Msk (0x1UL << RCC_IOPENR_GPIOAEN_Pos)

#define	RCC_IOPENR_GPIOAEN RCC_IOPENR_GPIOAEN_Msk

#define	RCC_IOPENR_GPIOBEN_Pos (1U)

#define	RCC_IOPENR_GPIOBEN_Msk (0x1UL << RCC_IOPENR_GPIOBEN_Pos)

#define	RCC_IOPENR_GPIOBEN RCC_IOPENR_GPIOBEN_Msk

#define	RCC_IOPENR_GPIOCEN_Pos (2U)

#define	RCC_IOPENR_GPIOCEN_Msk (0x1UL << RCC_IOPENR_GPIOCEN_Pos)

#define	RCC_IOPENR_GPIOCEN RCC_IOPENR_GPIOCEN_Msk

#define	RCC_IOPENR_GPIODEN_Pos (3U)

#define	RCC_IOPENR_GPIODEN_Msk (0x1UL << RCC_IOPENR_GPIODEN_Pos)

#define	RCC_IOPENR_GPIODEN RCC_IOPENR_GPIODEN_Msk

#define	RCC_IOPENR_GPIOFEN_Pos (5U)

#define	RCC_IOPENR_GPIOFEN_Msk (0x1UL << RCC_IOPENR_GPIOFEN_Pos)

#define	RCC_IOPENR_GPIOFEN RCC_IOPENR_GPIOFEN_Msk

#define	RCC_AHBENR_DMA1EN_Pos (0U)

#define	RCC_AHBENR_DMA1EN_Msk (0x1UL << RCC_AHBENR_DMA1EN_Pos)

#define	RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk

#define	RCC_AHBENR_FLASHEN_Pos (8U)

#define	RCC_AHBENR_FLASHEN_Msk (0x1UL << RCC_AHBENR_FLASHEN_Pos)

#define	RCC_AHBENR_FLASHEN RCC_AHBENR_FLASHEN_Msk

#define	RCC_AHBENR_CRCEN_Pos (12U)

#define	RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos)

#define	RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk

#define	RCC_APBENR1_TIM3EN_Pos (1U)

#define	RCC_APBENR1_TIM3EN_Msk (0x1UL << RCC_APBENR1_TIM3EN_Pos)

#define	RCC_APBENR1_TIM3EN RCC_APBENR1_TIM3EN_Msk

#define	RCC_APBENR1_RTCAPBEN_Pos (10U)

#define	RCC_APBENR1_RTCAPBEN_Msk (0x1UL << RCC_APBENR1_RTCAPBEN_Pos)

#define	RCC_APBENR1_RTCAPBEN RCC_APBENR1_RTCAPBEN_Msk

#define	RCC_APBENR1_WWDGEN_Pos (11U)

#define	RCC_APBENR1_WWDGEN_Msk (0x1UL << RCC_APBENR1_WWDGEN_Pos)

#define	RCC_APBENR1_WWDGEN RCC_APBENR1_WWDGEN_Msk

#define	RCC_APBENR1_SPI2EN_Pos (14U)

#define	RCC_APBENR1_SPI2EN_Msk (0x1UL << RCC_APBENR1_SPI2EN_Pos)

#define	RCC_APBENR1_SPI2EN RCC_APBENR1_SPI2EN_Msk

#define	RCC_APBENR1_USART2EN_Pos (17U)

#define	RCC_APBENR1_USART2EN_Msk (0x1UL << RCC_APBENR1_USART2EN_Pos)

#define	RCC_APBENR1_USART2EN RCC_APBENR1_USART2EN_Msk

#define	RCC_APBENR1_I2C1EN_Pos (21U)

#define	RCC_APBENR1_I2C1EN_Msk (0x1UL << RCC_APBENR1_I2C1EN_Pos)

#define	RCC_APBENR1_I2C1EN RCC_APBENR1_I2C1EN_Msk

#define	RCC_APBENR1_I2C2EN_Pos (22U)

#define	RCC_APBENR1_I2C2EN_Msk (0x1UL << RCC_APBENR1_I2C2EN_Pos)

#define	RCC_APBENR1_I2C2EN RCC_APBENR1_I2C2EN_Msk

#define	RCC_APBENR1_DBGEN_Pos (27U)

#define	RCC_APBENR1_DBGEN_Msk (0x1UL << RCC_APBENR1_DBGEN_Pos)

#define	RCC_APBENR1_DBGEN RCC_APBENR1_DBGEN_Msk

#define	RCC_APBENR1_PWREN_Pos (28U)

#define	RCC_APBENR1_PWREN_Msk (0x1UL << RCC_APBENR1_PWREN_Pos)

#define	RCC_APBENR1_PWREN RCC_APBENR1_PWREN_Msk

#define	RCC_APBENR2_SYSCFGEN_Pos (0U)

#define	RCC_APBENR2_SYSCFGEN_Msk (0x1UL << RCC_APBENR2_SYSCFGEN_Pos)

#define	RCC_APBENR2_SYSCFGEN RCC_APBENR2_SYSCFGEN_Msk

#define	RCC_APBENR2_TIM1EN_Pos (11U)

#define	RCC_APBENR2_TIM1EN_Msk (0x1UL << RCC_APBENR2_TIM1EN_Pos)

#define	RCC_APBENR2_TIM1EN RCC_APBENR2_TIM1EN_Msk

#define	RCC_APBENR2_SPI1EN_Pos (12U)

#define	RCC_APBENR2_SPI1EN_Msk (0x1UL << RCC_APBENR2_SPI1EN_Pos)

#define	RCC_APBENR2_SPI1EN RCC_APBENR2_SPI1EN_Msk

#define	RCC_APBENR2_USART1EN_Pos (14U)

#define	RCC_APBENR2_USART1EN_Msk (0x1UL << RCC_APBENR2_USART1EN_Pos)

#define	RCC_APBENR2_USART1EN RCC_APBENR2_USART1EN_Msk

#define	RCC_APBENR2_TIM14EN_Pos (15U)

#define	RCC_APBENR2_TIM14EN_Msk (0x1UL << RCC_APBENR2_TIM14EN_Pos)

#define	RCC_APBENR2_TIM14EN RCC_APBENR2_TIM14EN_Msk

#define	RCC_APBENR2_TIM16EN_Pos (17U)

#define	RCC_APBENR2_TIM16EN_Msk (0x1UL << RCC_APBENR2_TIM16EN_Pos)

#define	RCC_APBENR2_TIM16EN RCC_APBENR2_TIM16EN_Msk

#define	RCC_APBENR2_TIM17EN_Pos (18U)

#define	RCC_APBENR2_TIM17EN_Msk (0x1UL << RCC_APBENR2_TIM17EN_Pos)

#define	RCC_APBENR2_TIM17EN RCC_APBENR2_TIM17EN_Msk

#define	RCC_APBENR2_ADCEN_Pos (20U)

#define	RCC_APBENR2_ADCEN_Msk (0x1UL << RCC_APBENR2_ADCEN_Pos)

#define	RCC_APBENR2_ADCEN RCC_APBENR2_ADCEN_Msk

#define	RCC_IOPSMENR_GPIOASMEN_Pos (0U)

#define	RCC_IOPSMENR_GPIOASMEN_Msk (0x1UL << RCC_IOPSMENR_GPIOASMEN_Pos)

#define	RCC_IOPSMENR_GPIOASMEN RCC_IOPSMENR_GPIOASMEN_Msk

#define	RCC_IOPSMENR_GPIOBSMEN_Pos (1U)

#define	RCC_IOPSMENR_GPIOBSMEN_Msk (0x1UL << RCC_IOPSMENR_GPIOBSMEN_Pos)

#define	RCC_IOPSMENR_GPIOBSMEN RCC_IOPSMENR_GPIOBSMEN_Msk

#define	RCC_IOPSMENR_GPIOCSMEN_Pos (2U)

#define	RCC_IOPSMENR_GPIOCSMEN_Msk (0x1UL << RCC_IOPSMENR_GPIOCSMEN_Pos)

#define	RCC_IOPSMENR_GPIOCSMEN RCC_IOPSMENR_GPIOCSMEN_Msk

#define	RCC_IOPSMENR_GPIODSMEN_Pos (3U)

#define	RCC_IOPSMENR_GPIODSMEN_Msk (0x1UL << RCC_IOPSMENR_GPIODSMEN_Pos)

#define	RCC_IOPSMENR_GPIODSMEN RCC_IOPSMENR_GPIODSMEN_Msk

#define	RCC_IOPSMENR_GPIOFSMEN_Pos (5U)

#define	RCC_IOPSMENR_GPIOFSMEN_Msk (0x1UL << RCC_IOPSMENR_GPIOFSMEN_Pos)

#define	RCC_IOPSMENR_GPIOFSMEN RCC_IOPSMENR_GPIOFSMEN_Msk

#define	RCC_AHBSMENR_DMA1SMEN_Pos (0U)

#define	RCC_AHBSMENR_DMA1SMEN_Msk (0x1UL << RCC_AHBSMENR_DMA1SMEN_Pos)

#define	RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMA1SMEN_Msk

#define	RCC_AHBSMENR_FLASHSMEN_Pos (8U)

#define	RCC_AHBSMENR_FLASHSMEN_Msk (0x1UL << RCC_AHBSMENR_FLASHSMEN_Pos)

#define	RCC_AHBSMENR_FLASHSMEN RCC_AHBSMENR_FLASHSMEN_Msk

#define	RCC_AHBSMENR_SRAMSMEN_Pos (9U)

#define	RCC_AHBSMENR_SRAMSMEN_Msk (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos)

#define	RCC_AHBSMENR_SRAMSMEN RCC_AHBSMENR_SRAMSMEN_Msk

#define	RCC_AHBSMENR_CRCSMEN_Pos (12U)

#define	RCC_AHBSMENR_CRCSMEN_Msk (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos)

#define	RCC_AHBSMENR_CRCSMEN RCC_AHBSMENR_CRCSMEN_Msk

#define	RCC_APBSMENR1_TIM3SMEN_Pos (1U)

#define	RCC_APBSMENR1_TIM3SMEN_Msk (0x1UL << RCC_APBSMENR1_TIM3SMEN_Pos)

#define	RCC_APBSMENR1_TIM3SMEN RCC_APBSMENR1_TIM3SMEN_Msk

#define	RCC_APBSMENR1_RTCAPBSMEN_Pos (10U)

#define	RCC_APBSMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APBSMENR1_RTCAPBSMEN_Pos)

#define	RCC_APBSMENR1_RTCAPBSMEN RCC_APBSMENR1_RTCAPBSMEN_Msk

#define	RCC_APBSMENR1_WWDGSMEN_Pos (11U)

#define	RCC_APBSMENR1_WWDGSMEN_Msk (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos)

#define	RCC_APBSMENR1_WWDGSMEN RCC_APBSMENR1_WWDGSMEN_Msk

#define	RCC_APBSMENR1_SPI2SMEN_Pos (14U)

#define	RCC_APBSMENR1_SPI2SMEN_Msk (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos)

#define	RCC_APBSMENR1_SPI2SMEN RCC_APBSMENR1_SPI2SMEN_Msk

#define	RCC_APBSMENR1_USART2SMEN_Pos (17U)

#define	RCC_APBSMENR1_USART2SMEN_Msk (0x1UL << RCC_APBSMENR1_USART2SMEN_Pos)

#define	RCC_APBSMENR1_USART2SMEN RCC_APBSMENR1_USART2SMEN_Msk

#define	RCC_APBSMENR1_I2C1SMEN_Pos (21U)

#define	RCC_APBSMENR1_I2C1SMEN_Msk (0x1UL << RCC_APBSMENR1_I2C1SMEN_Pos)

#define	RCC_APBSMENR1_I2C1SMEN RCC_APBSMENR1_I2C1SMEN_Msk

#define	RCC_APBSMENR1_I2C2SMEN_Pos (22U)

#define	RCC_APBSMENR1_I2C2SMEN_Msk (0x1UL << RCC_APBSMENR1_I2C2SMEN_Pos)

#define	RCC_APBSMENR1_I2C2SMEN RCC_APBSMENR1_I2C2SMEN_Msk

#define	RCC_APBSMENR1_DBGSMEN_Pos (27U)

#define	RCC_APBSMENR1_DBGSMEN_Msk (0x1UL << RCC_APBSMENR1_DBGSMEN_Pos)

#define	RCC_APBSMENR1_DBGSMEN RCC_APBSMENR1_DBGSMEN_Msk

#define	RCC_APBSMENR1_PWRSMEN_Pos (28U)

#define	RCC_APBSMENR1_PWRSMEN_Msk (0x1UL << RCC_APBSMENR1_PWRSMEN_Pos)

#define	RCC_APBSMENR1_PWRSMEN RCC_APBSMENR1_PWRSMEN_Msk

#define	RCC_APBSMENR2_SYSCFGSMEN_Pos (0U)

#define	RCC_APBSMENR2_SYSCFGSMEN_Msk (0x1UL << RCC_APBSMENR2_SYSCFGSMEN_Pos)

#define	RCC_APBSMENR2_SYSCFGSMEN RCC_APBSMENR2_SYSCFGSMEN_Msk

#define	RCC_APBSMENR2_TIM1SMEN_Pos (11U)

#define	RCC_APBSMENR2_TIM1SMEN_Msk (0x1UL << RCC_APBSMENR2_TIM1SMEN_Pos)

#define	RCC_APBSMENR2_TIM1SMEN RCC_APBSMENR2_TIM1SMEN_Msk

#define	RCC_APBSMENR2_SPI1SMEN_Pos (12U)

#define	RCC_APBSMENR2_SPI1SMEN_Msk (0x1UL << RCC_APBSMENR2_SPI1SMEN_Pos)

#define	RCC_APBSMENR2_SPI1SMEN RCC_APBSMENR2_SPI1SMEN_Msk

#define	RCC_APBSMENR2_USART1SMEN_Pos (14U)

#define	RCC_APBSMENR2_USART1SMEN_Msk (0x1UL << RCC_APBSMENR2_USART1SMEN_Pos)

#define	RCC_APBSMENR2_USART1SMEN RCC_APBSMENR2_USART1SMEN_Msk

#define	RCC_APBSMENR2_TIM14SMEN_Pos (15U)

#define	RCC_APBSMENR2_TIM14SMEN_Msk (0x1UL << RCC_APBSMENR2_TIM14SMEN_Pos)

#define	RCC_APBSMENR2_TIM14SMEN RCC_APBSMENR2_TIM14SMEN_Msk

#define	RCC_APBSMENR2_TIM16SMEN_Pos (17U)

#define	RCC_APBSMENR2_TIM16SMEN_Msk (0x1UL << RCC_APBSMENR2_TIM16SMEN_Pos)

#define	RCC_APBSMENR2_TIM16SMEN RCC_APBSMENR2_TIM16SMEN_Msk

#define	RCC_APBSMENR2_TIM17SMEN_Pos (18U)

#define	RCC_APBSMENR2_TIM17SMEN_Msk (0x1UL << RCC_APBSMENR2_TIM17SMEN_Pos)

#define	RCC_APBSMENR2_TIM17SMEN RCC_APBSMENR2_TIM17SMEN_Msk

#define	RCC_APBSMENR2_ADCSMEN_Pos (20U)

#define	RCC_APBSMENR2_ADCSMEN_Msk (0x1UL << RCC_APBSMENR2_ADCSMEN_Pos)

#define	RCC_APBSMENR2_ADCSMEN RCC_APBSMENR2_ADCSMEN_Msk

#define	RCC_CCIPR_USART1SEL_Pos (0U)

#define	RCC_CCIPR_USART1SEL_Msk (0x3UL << RCC_CCIPR_USART1SEL_Pos)

#define	RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk

#define	RCC_CCIPR_USART1SEL_0 (0x1UL << RCC_CCIPR_USART1SEL_Pos)

#define	RCC_CCIPR_USART1SEL_1 (0x2UL << RCC_CCIPR_USART1SEL_Pos)

#define	RCC_CCIPR_I2C1SEL_Pos (12U)

#define	RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos)

#define	RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk

#define	RCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos)

#define	RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos)

#define	RCC_CCIPR_I2S1SEL_Pos (14U)

#define	RCC_CCIPR_I2S1SEL_Msk (0x3UL << RCC_CCIPR_I2S1SEL_Pos)

#define	RCC_CCIPR_I2S1SEL RCC_CCIPR_I2S1SEL_Msk

#define	RCC_CCIPR_I2S1SEL_0 (0x1UL << RCC_CCIPR_I2S1SEL_Pos)

#define	RCC_CCIPR_I2S1SEL_1 (0x2UL << RCC_CCIPR_I2S1SEL_Pos)

#define	RCC_CCIPR_ADCSEL_Pos (30U)

#define	RCC_CCIPR_ADCSEL_Msk (0x3UL << RCC_CCIPR_ADCSEL_Pos)

#define	RCC_CCIPR_ADCSEL RCC_CCIPR_ADCSEL_Msk

#define	RCC_CCIPR_ADCSEL_0 (0x1UL << RCC_CCIPR_ADCSEL_Pos)

#define	RCC_CCIPR_ADCSEL_1 (0x2UL << RCC_CCIPR_ADCSEL_Pos)

#define	RCC_BDCR_LSEON_Pos (0U)

#define	RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos)

#define	RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk

#define	RCC_BDCR_LSERDY_Pos (1U)

#define	RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos)

#define	RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk

#define	RCC_BDCR_LSEBYP_Pos (2U)

#define	RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos)

#define	RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk

#define	RCC_BDCR_LSEDRV_Pos (3U)

#define	RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos)

#define	RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk

#define	RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos)

#define	RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos)

#define	RCC_BDCR_LSECSSON_Pos (5U)

#define	RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos)

#define	RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk

#define	RCC_BDCR_LSECSSD_Pos (6U)

#define	RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos)

#define	RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk

#define	RCC_BDCR_RTCSEL_Pos (8U)

#define	RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos)

#define	RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk

#define	RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos)

#define	RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos)

#define	RCC_BDCR_RTCEN_Pos (15U)

#define	RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos)

#define	RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk

#define	RCC_BDCR_BDRST_Pos (16U)

#define	RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos)

#define	RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk

#define	RCC_BDCR_LSCOEN_Pos (24U)

#define	RCC_BDCR_LSCOEN_Msk (0x1UL << RCC_BDCR_LSCOEN_Pos)

#define	RCC_BDCR_LSCOEN RCC_BDCR_LSCOEN_Msk

#define	RCC_BDCR_LSCOSEL_Pos (25U)

#define	RCC_BDCR_LSCOSEL_Msk (0x1UL << RCC_BDCR_LSCOSEL_Pos)

#define	RCC_BDCR_LSCOSEL RCC_BDCR_LSCOSEL_Msk

#define	RCC_CSR_LSION_Pos (0U)

#define	RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos)

#define	RCC_CSR_LSION RCC_CSR_LSION_Msk

#define	RCC_CSR_LSIRDY_Pos (1U)

#define	RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos)

#define	RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk

#define	RCC_CSR_RMVF_Pos (23U)

#define	RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos)

#define	RCC_CSR_RMVF RCC_CSR_RMVF_Msk

#define	RCC_CSR_OBLRSTF_Pos (25U)

#define	RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos)

#define	RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk

#define	RCC_CSR_PINRSTF_Pos (26U)

#define	RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos)

#define	RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk

#define	RCC_CSR_PWRRSTF_Pos (27U)

#define	RCC_CSR_PWRRSTF_Msk (0x1UL << RCC_CSR_PWRRSTF_Pos)

#define	RCC_CSR_PWRRSTF RCC_CSR_PWRRSTF_Msk

#define	RCC_CSR_SFTRSTF_Pos (28U)

#define	RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos)

#define	RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk

#define	RCC_CSR_IWDGRSTF_Pos (29U)

#define	RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos)

#define	RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk

#define	RCC_CSR_WWDGRSTF_Pos (30U)

#define	RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos)

#define	RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk

#define	RCC_CSR_LPWRRSTF_Pos (31U)

#define	RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos)

#define	RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk

#define	RTC_WAKEUP_SUPPORT

#define	RTC_BACKUP_SUPPORT

#define	RTC_TR_PM_Pos (22U)

#define	RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos)

#define	RTC_TR_PM RTC_TR_PM_Msk

#define	RTC_TR_HT_Pos (20U)

#define	RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos)

#define	RTC_TR_HT RTC_TR_HT_Msk

#define	RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos)

#define	RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos)

#define	RTC_TR_HU_Pos (16U)

#define	RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos)

#define	RTC_TR_HU RTC_TR_HU_Msk

#define	RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos)

#define	RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos)

#define	RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos)

#define	RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos)

#define	RTC_TR_MNT_Pos (12U)

#define	RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos)

#define	RTC_TR_MNT RTC_TR_MNT_Msk

#define	RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos)

#define	RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos)

#define	RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos)

#define	RTC_TR_MNU_Pos (8U)

#define	RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos)

#define	RTC_TR_MNU RTC_TR_MNU_Msk

#define	RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos)

#define	RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos)

#define	RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos)

#define	RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos)

#define	RTC_TR_ST_Pos (4U)

#define	RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos)

#define	RTC_TR_ST RTC_TR_ST_Msk

#define	RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos)

#define	RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos)

#define	RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos)

#define	RTC_TR_SU_Pos (0U)

#define	RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos)

#define	RTC_TR_SU RTC_TR_SU_Msk

#define	RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos)

#define	RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos)

#define	RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos)

#define	RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos)

#define	RTC_DR_YT_Pos (20U)

#define	RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos)

#define	RTC_DR_YT RTC_DR_YT_Msk

#define	RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos)

#define	RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos)

#define	RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos)

#define	RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos)

#define	RTC_DR_YU_Pos (16U)

#define	RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos)

#define	RTC_DR_YU RTC_DR_YU_Msk

#define	RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos)

#define	RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos)

#define	RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos)

#define	RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos)

#define	RTC_DR_WDU_Pos (13U)

#define	RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos)

#define	RTC_DR_WDU RTC_DR_WDU_Msk

#define	RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos)

#define	RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos)

#define	RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos)

#define	RTC_DR_MT_Pos (12U)

#define	RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos)

#define	RTC_DR_MT RTC_DR_MT_Msk

#define	RTC_DR_MU_Pos (8U)

#define	RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos)

#define	RTC_DR_MU RTC_DR_MU_Msk

#define	RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos)

#define	RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos)

#define	RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos)

#define	RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos)

#define	RTC_DR_DT_Pos (4U)

#define	RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos)

#define	RTC_DR_DT RTC_DR_DT_Msk

#define	RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos)

#define	RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos)

#define	RTC_DR_DU_Pos (0U)

#define	RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos)

#define	RTC_DR_DU RTC_DR_DU_Msk

#define	RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos)

#define	RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos)

#define	RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos)

#define	RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos)

#define	RTC_SSR_SS_Pos (0U)

#define	RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos)

#define	RTC_SSR_SS RTC_SSR_SS_Msk

#define	RTC_ICSR_RECALPF_Pos (16U)

#define	RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos)

#define	RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk

#define	RTC_ICSR_INIT_Pos (7U)

#define	RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos)

#define	RTC_ICSR_INIT RTC_ICSR_INIT_Msk

#define	RTC_ICSR_INITF_Pos (6U)

#define	RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos)

#define	RTC_ICSR_INITF RTC_ICSR_INITF_Msk

#define	RTC_ICSR_RSF_Pos (5U)

#define	RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos)

#define	RTC_ICSR_RSF RTC_ICSR_RSF_Msk

#define	RTC_ICSR_INITS_Pos (4U)

#define	RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos)

#define	RTC_ICSR_INITS RTC_ICSR_INITS_Msk

#define	RTC_ICSR_SHPF_Pos (3U)

#define	RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos)

#define	RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk

#define	RTC_ICSR_WUTWF_Pos (2U)

#define	RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos)

#define	RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk

#define	RTC_ICSR_ALRBWF_Pos (1U)

#define	RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos)

#define	RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk

#define	RTC_ICSR_ALRAWF_Pos (0U)

#define	RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos)

#define	RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk

#define	RTC_PRER_PREDIV_A_Pos (16U)

#define	RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos)

#define	RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk

#define	RTC_PRER_PREDIV_S_Pos (0U)

#define	RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)

#define	RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk

#define	RTC_WUTR_WUT_Pos (0U)

#define	RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos)

#define	RTC_WUTR_WUT RTC_WUTR_WUT_Msk

#define	RTC_CR_OUT2EN_Pos (31U)

#define	RTC_CR_OUT2EN_Msk (0x1UL << RTC_CR_OUT2EN_Pos)

#define	RTC_CR_OUT2EN RTC_CR_OUT2EN_Msk

#define	RTC_CR_TAMPALRM_TYPE_Pos (30U)

#define	RTC_CR_TAMPALRM_TYPE_Msk (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos)

#define	RTC_CR_TAMPALRM_TYPE RTC_CR_TAMPALRM_TYPE_Msk

#define	RTC_CR_TAMPALRM_PU_Pos (29U)

#define	RTC_CR_TAMPALRM_PU_Msk (0x1UL << RTC_CR_TAMPALRM_PU_Pos)

#define	RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk

#define	RTC_CR_TAMPOE_Pos (26U)

#define	RTC_CR_TAMPOE_Msk (0x1UL << RTC_CR_TAMPOE_Pos)

#define	RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk

#define	RTC_CR_TAMPTS_Pos (25U)

#define	RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos)

#define	RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk

#define	RTC_CR_ITSE_Pos (24U)

#define	RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos)

#define	RTC_CR_ITSE RTC_CR_ITSE_Msk

#define	RTC_CR_COE_Pos (23U)

#define	RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos)

#define	RTC_CR_COE RTC_CR_COE_Msk

#define	RTC_CR_OSEL_Pos (21U)

#define	RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos)

#define	RTC_CR_OSEL RTC_CR_OSEL_Msk

#define	RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos)

#define	RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos)

#define	RTC_CR_POL_Pos (20U)

#define	RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos)

#define	RTC_CR_POL RTC_CR_POL_Msk

#define	RTC_CR_COSEL_Pos (19U)

#define	RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos)

#define	RTC_CR_COSEL RTC_CR_COSEL_Msk

#define	RTC_CR_BKP_Pos (18U)

#define	RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos)

#define	RTC_CR_BKP RTC_CR_BKP_Msk

#define	RTC_CR_SUB1H_Pos (17U)

#define	RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos)

#define	RTC_CR_SUB1H RTC_CR_SUB1H_Msk

#define	RTC_CR_ADD1H_Pos (16U)

#define	RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos)

#define	RTC_CR_ADD1H RTC_CR_ADD1H_Msk

#define	RTC_CR_TSIE_Pos (15U)

#define	RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos)

#define	RTC_CR_TSIE RTC_CR_TSIE_Msk

#define	RTC_CR_WUTIE_Pos (14U)

#define	RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos)

#define	RTC_CR_WUTIE RTC_CR_WUTIE_Msk

#define	RTC_CR_ALRBIE_Pos (13U)

#define	RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos)

#define	RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk

#define	RTC_CR_ALRAIE_Pos (12U)

#define	RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos)

#define	RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk

#define	RTC_CR_TSE_Pos (11U)

#define	RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos)

#define	RTC_CR_TSE RTC_CR_TSE_Msk

#define	RTC_CR_WUTE_Pos (10U)

#define	RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos)

#define	RTC_CR_WUTE RTC_CR_WUTE_Msk

#define	RTC_CR_ALRBE_Pos (9U)

#define	RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos)

#define	RTC_CR_ALRBE RTC_CR_ALRBE_Msk

#define	RTC_CR_ALRAE_Pos (8U)

#define	RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos)

#define	RTC_CR_ALRAE RTC_CR_ALRAE_Msk

#define	RTC_CR_FMT_Pos (6U)

#define	RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos)

#define	RTC_CR_FMT RTC_CR_FMT_Msk

#define	RTC_CR_BYPSHAD_Pos (5U)

#define	RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos)

#define	RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk

#define	RTC_CR_REFCKON_Pos (4U)

#define	RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos)

#define	RTC_CR_REFCKON RTC_CR_REFCKON_Msk

#define	RTC_CR_TSEDGE_Pos (3U)

#define	RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos)

#define	RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk

#define	RTC_CR_WUCKSEL_Pos (0U)

#define	RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos)

#define	RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk

#define	RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos)

#define	RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos)

#define	RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos)

#define	RTC_WPR_KEY_Pos (0U)

#define	RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos)

#define	RTC_WPR_KEY RTC_WPR_KEY_Msk

#define	RTC_CALR_CALP_Pos (15U)

#define	RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos)

#define	RTC_CALR_CALP RTC_CALR_CALP_Msk

#define	RTC_CALR_CALW8_Pos (14U)

#define	RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos)

#define	RTC_CALR_CALW8 RTC_CALR_CALW8_Msk

#define	RTC_CALR_CALW16_Pos (13U)

#define	RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos)

#define	RTC_CALR_CALW16 RTC_CALR_CALW16_Msk

#define	RTC_CALR_CALM_Pos (0U)

#define	RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos)

#define	RTC_CALR_CALM RTC_CALR_CALM_Msk

#define	RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos)

#define	RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos)

#define	RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos)

#define	RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos)

#define	RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos)

#define	RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos)

#define	RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos)

#define	RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos)

#define	RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos)

#define	RTC_SHIFTR_SUBFS_Pos (0U)

#define	RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)

#define	RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk

#define	RTC_SHIFTR_ADD1S_Pos (31U)

#define	RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos)

#define	RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk

#define	RTC_TSTR_PM_Pos (22U)

#define	RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos)

#define	RTC_TSTR_PM RTC_TSTR_PM_Msk

#define	RTC_TSTR_HT_Pos (20U)

#define	RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos)

#define	RTC_TSTR_HT RTC_TSTR_HT_Msk

#define	RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos)

#define	RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos)

#define	RTC_TSTR_HU_Pos (16U)

#define	RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos)

#define	RTC_TSTR_HU RTC_TSTR_HU_Msk

#define	RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos)

#define	RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos)

#define	RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos)

#define	RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos)

#define	RTC_TSTR_MNT_Pos (12U)

#define	RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos)

#define	RTC_TSTR_MNT RTC_TSTR_MNT_Msk

#define	RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos)

#define	RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos)

#define	RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos)

#define	RTC_TSTR_MNU_Pos (8U)

#define	RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos)

#define	RTC_TSTR_MNU RTC_TSTR_MNU_Msk

#define	RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos)

#define	RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos)

#define	RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos)

#define	RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos)

#define	RTC_TSTR_ST_Pos (4U)

#define	RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos)

#define	RTC_TSTR_ST RTC_TSTR_ST_Msk

#define	RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos)

#define	RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos)

#define	RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos)

#define	RTC_TSTR_SU_Pos (0U)

#define	RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos)

#define	RTC_TSTR_SU RTC_TSTR_SU_Msk

#define	RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos)

#define	RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos)

#define	RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos)

#define	RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos)

#define	RTC_TSDR_WDU_Pos (13U)

#define	RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos)

#define	RTC_TSDR_WDU RTC_TSDR_WDU_Msk

#define	RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos)

#define	RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos)

#define	RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos)

#define	RTC_TSDR_MT_Pos (12U)

#define	RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos)

#define	RTC_TSDR_MT RTC_TSDR_MT_Msk

#define	RTC_TSDR_MU_Pos (8U)

#define	RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos)

#define	RTC_TSDR_MU RTC_TSDR_MU_Msk

#define	RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos)

#define	RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos)

#define	RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos)

#define	RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos)

#define	RTC_TSDR_DT_Pos (4U)

#define	RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos)

#define	RTC_TSDR_DT RTC_TSDR_DT_Msk

#define	RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos)

#define	RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos)

#define	RTC_TSDR_DU_Pos (0U)

#define	RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos)

#define	RTC_TSDR_DU RTC_TSDR_DU_Msk

#define	RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos)

#define	RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos)

#define	RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos)

#define	RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos)

#define	RTC_TSSSR_SS_Pos (0U)

#define	RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos)

#define	RTC_TSSSR_SS RTC_TSSSR_SS_Msk

#define	RTC_ALRMAR_MSK4_Pos (31U)

#define	RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos)

#define	RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk

#define	RTC_ALRMAR_WDSEL_Pos (30U)

#define	RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos)

#define	RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk

#define	RTC_ALRMAR_DT_Pos (28U)

#define	RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos)

#define	RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk

#define	RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos)

#define	RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos)

#define	RTC_ALRMAR_DU_Pos (24U)

#define	RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos)

#define	RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk

#define	RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos)

#define	RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos)

#define	RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos)

#define	RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos)

#define	RTC_ALRMAR_MSK3_Pos (23U)

#define	RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos)

#define	RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk

#define	RTC_ALRMAR_PM_Pos (22U)

#define	RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos)

#define	RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk

#define	RTC_ALRMAR_HT_Pos (20U)

#define	RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos)

#define	RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk

#define	RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos)

#define	RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos)

#define	RTC_ALRMAR_HU_Pos (16U)

#define	RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos)

#define	RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk

#define	RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos)

#define	RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos)

#define	RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos)

#define	RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos)

#define	RTC_ALRMAR_MSK2_Pos (15U)

#define	RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos)

#define	RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk

#define	RTC_ALRMAR_MNT_Pos (12U)

#define	RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos)

#define	RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk

#define	RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos)

#define	RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos)

#define	RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos)

#define	RTC_ALRMAR_MNU_Pos (8U)

#define	RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos)

#define	RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk

#define	RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos)

#define	RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos)

#define	RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos)

#define	RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos)

#define	RTC_ALRMAR_MSK1_Pos (7U)

#define	RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos)

#define	RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk

#define	RTC_ALRMAR_ST_Pos (4U)

#define	RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos)

#define	RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk

#define	RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos)

#define	RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos)

#define	RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos)

#define	RTC_ALRMAR_SU_Pos (0U)

#define	RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos)

#define	RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk

#define	RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos)

#define	RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos)

#define	RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos)

#define	RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos)

#define	RTC_ALRMASSR_MASKSS_Pos (24U)

#define	RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos)

#define	RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk

#define	RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos)

#define	RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos)

#define	RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos)

#define	RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos)

#define	RTC_ALRMASSR_SS_Pos (0U)

#define	RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos)

#define	RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk

#define	RTC_ALRMBR_MSK4_Pos (31U)

#define	RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos)

#define	RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk

#define	RTC_ALRMBR_WDSEL_Pos (30U)

#define	RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos)

#define	RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk

#define	RTC_ALRMBR_DT_Pos (28U)

#define	RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos)

#define	RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk

#define	RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos)

#define	RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos)

#define	RTC_ALRMBR_DU_Pos (24U)

#define	RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos)

#define	RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk

#define	RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos)

#define	RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos)

#define	RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos)

#define	RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos)

#define	RTC_ALRMBR_MSK3_Pos (23U)

#define	RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos)

#define	RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk

#define	RTC_ALRMBR_PM_Pos (22U)

#define	RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos)

#define	RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk

#define	RTC_ALRMBR_HT_Pos (20U)

#define	RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos)

#define	RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk

#define	RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos)

#define	RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos)

#define	RTC_ALRMBR_HU_Pos (16U)

#define	RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos)

#define	RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk

#define	RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos)

#define	RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos)

#define	RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos)

#define	RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos)

#define	RTC_ALRMBR_MSK2_Pos (15U)

#define	RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos)

#define	RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk

#define	RTC_ALRMBR_MNT_Pos (12U)

#define	RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos)

#define	RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk

#define	RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos)

#define	RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos)

#define	RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos)

#define	RTC_ALRMBR_MNU_Pos (8U)

#define	RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos)

#define	RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk

#define	RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos)

#define	RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos)

#define	RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos)

#define	RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos)

#define	RTC_ALRMBR_MSK1_Pos (7U)

#define	RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos)

#define	RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk

#define	RTC_ALRMBR_ST_Pos (4U)

#define	RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos)

#define	RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk

#define	RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos)

#define	RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos)

#define	RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos)

#define	RTC_ALRMBR_SU_Pos (0U)

#define	RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos)

#define	RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk

#define	RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos)

#define	RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos)

#define	RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos)

#define	RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos)

#define	RTC_ALRMBSSR_MASKSS_Pos (24U)

#define	RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)

#define	RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk

#define	RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)

#define	RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)

#define	RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)

#define	RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)

#define	RTC_ALRMBSSR_SS_Pos (0U)

#define	RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)

#define	RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk

#define	RTC_SR_ITSF_Pos (5U)

#define	RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos)

#define	RTC_SR_ITSF RTC_SR_ITSF_Msk

#define	RTC_SR_TSOVF_Pos (4U)

#define	RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos)

#define	RTC_SR_TSOVF RTC_SR_TSOVF_Msk

#define	RTC_SR_TSF_Pos (3U)

#define	RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos)

#define	RTC_SR_TSF RTC_SR_TSF_Msk

#define	RTC_SR_WUTF_Pos (2U)

#define	RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos)

#define	RTC_SR_WUTF RTC_SR_WUTF_Msk

#define	RTC_SR_ALRBF_Pos (1U)

#define	RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos)

#define	RTC_SR_ALRBF RTC_SR_ALRBF_Msk

#define	RTC_SR_ALRAF_Pos (0U)

#define	RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos)

#define	RTC_SR_ALRAF RTC_SR_ALRAF_Msk

#define	RTC_MISR_ITSMF_Pos (5U)

#define	RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos)

#define	RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk

#define	RTC_MISR_TSOVMF_Pos (4U)

#define	RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos)

#define	RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk

#define	RTC_MISR_TSMF_Pos (3U)

#define	RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos)

#define	RTC_MISR_TSMF RTC_MISR_TSMF_Msk

#define	RTC_MISR_WUTMF_Pos (2U)

#define	RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos)

#define	RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk

#define	RTC_MISR_ALRBMF_Pos (1U)

#define	RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos)

#define	RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk

#define	RTC_MISR_ALRAMF_Pos (0U)

#define	RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos)

#define	RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk

#define	RTC_SCR_CITSF_Pos (5U)

#define	RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos)

#define	RTC_SCR_CITSF RTC_SCR_CITSF_Msk

#define	RTC_SCR_CTSOVF_Pos (4U)

#define	RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos)

#define	RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk

#define	RTC_SCR_CTSF_Pos (3U)

#define	RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos)

#define	RTC_SCR_CTSF RTC_SCR_CTSF_Msk

#define	RTC_SCR_CWUTF_Pos (2U)

#define	RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos)

#define	RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk

#define	RTC_SCR_CALRBF_Pos (1U)

#define	RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos)

#define	RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk

#define	RTC_SCR_CALRAF_Pos (0U)

#define	RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos)

#define	RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk

#define	TAMP_CR1_TAMP1E_Pos (0U)

#define	TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos)

#define	TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk

#define	TAMP_CR1_TAMP2E_Pos (1U)

#define	TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos)

#define	TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk

#define	TAMP_CR1_ITAMP3E_Pos (18U)

#define	TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos)

#define	TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk

#define	TAMP_CR1_ITAMP4E_Pos (19U)

#define	TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos)

#define	TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk

#define	TAMP_CR1_ITAMP5E_Pos (20U)

#define	TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos)

#define	TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk

#define	TAMP_CR1_ITAMP6E_Pos (21U)

#define	TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos)

#define	TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk

#define	TAMP_CR2_TAMP1NOERASE_Pos (0U)

#define	TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos)

#define	TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk

#define	TAMP_CR2_TAMP2NOERASE_Pos (1U)

#define	TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos)

#define	TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk

#define	TAMP_CR2_TAMP1MSK_Pos (16U)

#define	TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos)

#define	TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk

#define	TAMP_CR2_TAMP2MSK_Pos (17U)

#define	TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos)

#define	TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk

#define	TAMP_CR2_TAMP1TRG_Pos (24U)

#define	TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos)

#define	TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk

#define	TAMP_CR2_TAMP2TRG_Pos (25U)

#define	TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos)

#define	TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk

#define	TAMP_FLTCR_TAMPFREQ_0 0x00000001U

#define	TAMP_FLTCR_TAMPFREQ_1 0x00000002U

#define	TAMP_FLTCR_TAMPFREQ_2 0x00000004U

#define	TAMP_FLTCR_TAMPFREQ_Pos (0U)

#define	TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos)

#define	TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk

#define	TAMP_FLTCR_TAMPFLT_0 0x00000008U

#define	TAMP_FLTCR_TAMPFLT_1 0x00000010U

#define	TAMP_FLTCR_TAMPFLT_Pos (3U)

#define	TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos)

#define	TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk

#define	TAMP_FLTCR_TAMPPRCH_0 0x00000020U

#define	TAMP_FLTCR_TAMPPRCH_1 0x00000040U

#define	TAMP_FLTCR_TAMPPRCH_Pos (5U)

#define	TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos)

#define	TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk

#define	TAMP_FLTCR_TAMPPUDIS_Pos (7U)

#define	TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos)

#define	TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk

#define	TAMP_IER_TAMP1IE_Pos (0U)

#define	TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos)

#define	TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk

#define	TAMP_IER_TAMP2IE_Pos (1U)

#define	TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos)

#define	TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk

#define	TAMP_IER_ITAMP3IE_Pos (18U)

#define	TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos)

#define	TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk

#define	TAMP_IER_ITAMP4IE_Pos (19U)

#define	TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos)

#define	TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk

#define	TAMP_IER_ITAMP5IE_Pos (20U)

#define	TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos)

#define	TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk

#define	TAMP_IER_ITAMP6IE_Pos (21U)

#define	TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos)

#define	TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk

#define	TAMP_SR_TAMP1F_Pos (0U)

#define	TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos)

#define	TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk

#define	TAMP_SR_TAMP2F_Pos (1U)

#define	TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos)

#define	TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk

#define	TAMP_SR_ITAMP3F_Pos (18U)

#define	TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos)

#define	TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk

#define	TAMP_SR_ITAMP4F_Pos (19U)

#define	TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos)

#define	TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk

#define	TAMP_SR_ITAMP5F_Pos (20U)

#define	TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos)

#define	TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk

#define	TAMP_SR_ITAMP6F_Pos (21U)

#define	TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos)

#define	TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk

#define	TAMP_MISR_TAMP1MF_Pos (0U)

#define	TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos)

#define	TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk

#define	TAMP_MISR_TAMP2MF_Pos (1U)

#define	TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos)

#define	TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk

#define	TAMP_MISR_ITAMP3MF_Pos (18U)

#define	TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos)

#define	TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk

#define	TAMP_MISR_ITAMP4MF_Pos (19U)

#define	TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos)

#define	TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk

#define	TAMP_MISR_ITAMP5MF_Pos (20U)

#define	TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos)

#define	TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk

#define	TAMP_MISR_ITAMP6MF_Pos (21U)

#define	TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos)

#define	TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk

#define	TAMP_SCR_CTAMP1F_Pos (0U)

#define	TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos)

#define	TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk

#define	TAMP_SCR_CTAMP2F_Pos (1U)

#define	TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos)

#define	TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk

#define	TAMP_SCR_CITAMP3F_Pos (18U)

#define	TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos)

#define	TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk

#define	TAMP_SCR_CITAMP4F_Pos (19U)

#define	TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos)

#define	TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk

#define	TAMP_SCR_CITAMP5F_Pos (20U)

#define	TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos)

#define	TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk

#define	TAMP_SCR_CITAMP6F_Pos (21U)

#define	TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos)

#define	TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk

#define	TAMP_BKP0R_Pos (0U)

#define	TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos)

#define	TAMP_BKP0R TAMP_BKP0R_Msk

#define	TAMP_BKP1R_Pos (0U)

#define	TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos)

#define	TAMP_BKP1R TAMP_BKP1R_Msk

#define	TAMP_BKP2R_Pos (0U)

#define	TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos)

#define	TAMP_BKP2R TAMP_BKP2R_Msk

#define	TAMP_BKP3R_Pos (0U)

#define	TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos)

#define	TAMP_BKP3R TAMP_BKP3R_Msk

#define	TAMP_BKP4R_Pos (0U)

#define	TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos)

#define	TAMP_BKP4R TAMP_BKP4R_Msk

#define	SPI_I2S_SUPPORT

#define	SPI_CR1_CPHA_Pos (0U)

#define	SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos)

#define	SPI_CR1_CPHA SPI_CR1_CPHA_Msk

#define	SPI_CR1_CPOL_Pos (1U)

#define	SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos)

#define	SPI_CR1_CPOL SPI_CR1_CPOL_Msk

#define	SPI_CR1_MSTR_Pos (2U)

#define	SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos)

#define	SPI_CR1_MSTR SPI_CR1_MSTR_Msk

#define	SPI_CR1_BR_Pos (3U)

#define	SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos)

#define	SPI_CR1_BR SPI_CR1_BR_Msk

#define	SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos)

#define	SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos)

#define	SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos)

#define	SPI_CR1_SPE_Pos (6U)

#define	SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos)

#define	SPI_CR1_SPE SPI_CR1_SPE_Msk

#define	SPI_CR1_LSBFIRST_Pos (7U)

#define	SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos)

#define	SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk

#define	SPI_CR1_SSI_Pos (8U)

#define	SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos)

#define	SPI_CR1_SSI SPI_CR1_SSI_Msk

#define	SPI_CR1_SSM_Pos (9U)

#define	SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos)

#define	SPI_CR1_SSM SPI_CR1_SSM_Msk

#define	SPI_CR1_RXONLY_Pos (10U)

#define	SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos)

#define	SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk

#define	SPI_CR1_CRCL_Pos (11U)

#define	SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos)

#define	SPI_CR1_CRCL SPI_CR1_CRCL_Msk

#define	SPI_CR1_CRCNEXT_Pos (12U)

#define	SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos)

#define	SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk

#define	SPI_CR1_CRCEN_Pos (13U)

#define	SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos)

#define	SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk

#define	SPI_CR1_BIDIOE_Pos (14U)

#define	SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos)

#define	SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk

#define	SPI_CR1_BIDIMODE_Pos (15U)

#define	SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos)

#define	SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk

#define	SPI_CR2_RXDMAEN_Pos (0U)

#define	SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos)

#define	SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk

#define	SPI_CR2_TXDMAEN_Pos (1U)

#define	SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos)

#define	SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk

#define	SPI_CR2_SSOE_Pos (2U)

#define	SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos)

#define	SPI_CR2_SSOE SPI_CR2_SSOE_Msk

#define	SPI_CR2_NSSP_Pos (3U)

#define	SPI_CR2_NSSP_Msk (0x1UL << SPI_CR2_NSSP_Pos)

#define	SPI_CR2_NSSP SPI_CR2_NSSP_Msk

#define	SPI_CR2_FRF_Pos (4U)

#define	SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos)

#define	SPI_CR2_FRF SPI_CR2_FRF_Msk

#define	SPI_CR2_ERRIE_Pos (5U)

#define	SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos)

#define	SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk

#define	SPI_CR2_RXNEIE_Pos (6U)

#define	SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos)

#define	SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk

#define	SPI_CR2_TXEIE_Pos (7U)

#define	SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos)

#define	SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk

#define	SPI_CR2_DS_Pos (8U)

#define	SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos)

#define	SPI_CR2_DS SPI_CR2_DS_Msk

#define	SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos)

#define	SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos)

#define	SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos)

#define	SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos)

#define	SPI_CR2_FRXTH_Pos (12U)

#define	SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos)

#define	SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk

#define	SPI_CR2_LDMARX_Pos (13U)

#define	SPI_CR2_LDMARX_Msk (0x1UL << SPI_CR2_LDMARX_Pos)

#define	SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk

#define	SPI_CR2_LDMATX_Pos (14U)

#define	SPI_CR2_LDMATX_Msk (0x1UL << SPI_CR2_LDMATX_Pos)

#define	SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk

#define	SPI_SR_RXNE_Pos (0U)

#define	SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos)

#define	SPI_SR_RXNE SPI_SR_RXNE_Msk

#define	SPI_SR_TXE_Pos (1U)

#define	SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos)

#define	SPI_SR_TXE SPI_SR_TXE_Msk

#define	SPI_SR_CHSIDE_Pos (2U)

#define	SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos)

#define	SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk

#define	SPI_SR_UDR_Pos (3U)

#define	SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos)

#define	SPI_SR_UDR SPI_SR_UDR_Msk

#define	SPI_SR_CRCERR_Pos (4U)

#define	SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos)

#define	SPI_SR_CRCERR SPI_SR_CRCERR_Msk

#define	SPI_SR_MODF_Pos (5U)

#define	SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos)

#define	SPI_SR_MODF SPI_SR_MODF_Msk

#define	SPI_SR_OVR_Pos (6U)

#define	SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos)

#define	SPI_SR_OVR SPI_SR_OVR_Msk

#define	SPI_SR_BSY_Pos (7U)

#define	SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos)

#define	SPI_SR_BSY SPI_SR_BSY_Msk

#define	SPI_SR_FRE_Pos (8U)

#define	SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos)

#define	SPI_SR_FRE SPI_SR_FRE_Msk

#define	SPI_SR_FRLVL_Pos (9U)

#define	SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos)

#define	SPI_SR_FRLVL SPI_SR_FRLVL_Msk

#define	SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos)

#define	SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos)

#define	SPI_SR_FTLVL_Pos (11U)

#define	SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos)

#define	SPI_SR_FTLVL SPI_SR_FTLVL_Msk

#define	SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos)

#define	SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos)

#define	SPI_DR_DR_Pos (0U)

#define	SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos)

#define	SPI_DR_DR SPI_DR_DR_Msk

#define	SPI_CRCPR_CRCPOLY_Pos (0U)

#define	SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)

#define	SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk

#define	SPI_RXCRCR_RXCRC_Pos (0U)

#define	SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)

#define	SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk

#define	SPI_TXCRCR_TXCRC_Pos (0U)

#define	SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)

#define	SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk

#define	SPI_I2SCFGR_CHLEN_Pos (0U)

#define	SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos)

#define	SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk

#define	SPI_I2SCFGR_DATLEN_Pos (1U)

#define	SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos)

#define	SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk

#define	SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos)

#define	SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos)

#define	SPI_I2SCFGR_CKPOL_Pos (3U)

#define	SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos)

#define	SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk

#define	SPI_I2SCFGR_I2SSTD_Pos (4U)

#define	SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)

#define	SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk

#define	SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)

#define	SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)

#define	SPI_I2SCFGR_PCMSYNC_Pos (7U)

#define	SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)

#define	SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk

#define	SPI_I2SCFGR_I2SCFG_Pos (8U)

#define	SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)

#define	SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk

#define	SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)

#define	SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)

#define	SPI_I2SCFGR_I2SE_Pos (10U)

#define	SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos)

#define	SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk

#define	SPI_I2SCFGR_I2SMOD_Pos (11U)

#define	SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)

#define	SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk

#define	SPI_I2SCFGR_ASTRTEN_Pos (12U)

#define	SPI_I2SCFGR_ASTRTEN_Msk (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos)

#define	SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk

#define	SPI_I2SPR_I2SDIV_Pos (0U)

#define	SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos)

#define	SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk

#define	SPI_I2SPR_ODD_Pos (8U)

#define	SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos)

#define	SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk

#define	SPI_I2SPR_MCKOE_Pos (9U)

#define	SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos)

#define	SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk

#define	SYSCFG_CDEN_SUPPORT

#define	SYSCFG_CFGR1_MEM_MODE_Pos (0U)

#define	SYSCFG_CFGR1_MEM_MODE_Msk (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos)

#define	SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk

#define	SYSCFG_CFGR1_MEM_MODE_0 (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos)

#define	SYSCFG_CFGR1_MEM_MODE_1 (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos)

#define	SYSCFG_CFGR1_PA11_RMP_Pos (3U)

#define	SYSCFG_CFGR1_PA11_RMP_Msk (0x1UL << SYSCFG_CFGR1_PA11_RMP_Pos)

#define	SYSCFG_CFGR1_PA11_RMP SYSCFG_CFGR1_PA11_RMP_Msk

#define	SYSCFG_CFGR1_PA12_RMP_Pos (4U)

#define	SYSCFG_CFGR1_PA12_RMP_Msk (0x1UL << SYSCFG_CFGR1_PA12_RMP_Pos)

#define	SYSCFG_CFGR1_PA12_RMP SYSCFG_CFGR1_PA12_RMP_Msk

#define	SYSCFG_CFGR1_IR_POL_Pos (5U)

#define	SYSCFG_CFGR1_IR_POL_Msk (0x1UL << SYSCFG_CFGR1_IR_POL_Pos)

#define	SYSCFG_CFGR1_IR_POL SYSCFG_CFGR1_IR_POL_Msk

#define	SYSCFG_CFGR1_IR_MOD_Pos (6U)

#define	SYSCFG_CFGR1_IR_MOD_Msk (0x3UL << SYSCFG_CFGR1_IR_MOD_Pos)

#define	SYSCFG_CFGR1_IR_MOD SYSCFG_CFGR1_IR_MOD_Msk

#define	SYSCFG_CFGR1_IR_MOD_0 (0x1UL << SYSCFG_CFGR1_IR_MOD_Pos)

#define	SYSCFG_CFGR1_IR_MOD_1 (0x2UL << SYSCFG_CFGR1_IR_MOD_Pos)

#define	SYSCFG_CFGR1_BOOSTEN_Pos (8U)

#define	SYSCFG_CFGR1_BOOSTEN_Msk (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos)

#define	SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN_Msk

#define	SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U)

#define	SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos)

#define	SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk

#define	SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U)

#define	SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos)

#define	SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk

#define	SYSCFG_CFGR1_I2C_PB8_FMP_Pos (18U)

#define	SYSCFG_CFGR1_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos)

#define	SYSCFG_CFGR1_I2C_PB8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk

#define	SYSCFG_CFGR1_I2C_PB9_FMP_Pos (19U)

#define	SYSCFG_CFGR1_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos)

#define	SYSCFG_CFGR1_I2C_PB9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk

#define	SYSCFG_CFGR1_I2C1_FMP_Pos (20U)

#define	SYSCFG_CFGR1_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos)

#define	SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk

#define	SYSCFG_CFGR1_I2C2_FMP_Pos (21U)

#define	SYSCFG_CFGR1_I2C2_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C2_FMP_Pos)

#define	SYSCFG_CFGR1_I2C2_FMP SYSCFG_CFGR1_I2C2_FMP_Msk

#define	SYSCFG_CFGR1_I2C_PA9_FMP_Pos (22U)

#define	SYSCFG_CFGR1_I2C_PA9_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PA9_FMP_Pos)

#define	SYSCFG_CFGR1_I2C_PA9_FMP SYSCFG_CFGR1_I2C_PA9_FMP_Msk

#define	SYSCFG_CFGR1_I2C_PA10_FMP_Pos (23U)

#define	SYSCFG_CFGR1_I2C_PA10_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PA10_FMP_Pos)

#define	SYSCFG_CFGR1_I2C_PA10_FMP SYSCFG_CFGR1_I2C_PA10_FMP_Msk

#define	SYSCFG_CFGR2_CLL_Pos (0U)

#define	SYSCFG_CFGR2_CLL_Msk (0x1UL << SYSCFG_CFGR2_CLL_Pos)

#define	SYSCFG_CFGR2_CLL SYSCFG_CFGR2_CLL_Msk

#define	SYSCFG_CFGR2_SPL_Pos (1U)

#define	SYSCFG_CFGR2_SPL_Msk (0x1UL << SYSCFG_CFGR2_SPL_Pos)

#define	SYSCFG_CFGR2_SPL SYSCFG_CFGR2_SPL_Msk

#define	SYSCFG_CFGR2_ECCL_Pos (3U)

#define	SYSCFG_CFGR2_ECCL_Msk (0x1UL << SYSCFG_CFGR2_ECCL_Pos)

#define	SYSCFG_CFGR2_ECCL SYSCFG_CFGR2_ECCL_Msk

#define	SYSCFG_CFGR2_SPF_Pos (8U)

#define	SYSCFG_CFGR2_SPF_Msk (0x1UL << SYSCFG_CFGR2_SPF_Pos)

#define	SYSCFG_CFGR2_SPF SYSCFG_CFGR2_SPF_Msk

#define	SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SPF

#define	SYSCFG_CFGR2_PA1_CDEN_Pos (16U)

#define	SYSCFG_CFGR2_PA1_CDEN_Msk (0x1UL << SYSCFG_CFGR2_PA1_CDEN_Pos) /* 0x00010000 */

#define	SYSCFG_CFGR2_PA1_CDEN SYSCFG_CFGR2_PA1_CDEN_Msk

#define	SYSCFG_CFGR2_PA3_CDEN_Pos (17U)

#define	SYSCFG_CFGR2_PA3_CDEN_Msk (0x1UL << SYSCFG_CFGR2_PA3_CDEN_Pos) /* 0x00020000 */

#define	SYSCFG_CFGR2_PA3_CDEN SYSCFG_CFGR2_PA3_CDEN_Msk

#define	SYSCFG_CFGR2_PA5_CDEN_Pos (18U)

#define	SYSCFG_CFGR2_PA5_CDEN_Msk (0x1UL << SYSCFG_CFGR2_PA5_CDEN_Pos) /* 0x00040000 */

#define	SYSCFG_CFGR2_PA5_CDEN SYSCFG_CFGR2_PA5_CDEN_Msk

#define	SYSCFG_CFGR2_PA6_CDEN_Pos (19U)

#define	SYSCFG_CFGR2_PA6_CDEN_Msk (0x1UL << SYSCFG_CFGR2_PA6_CDEN_Pos) /* 0x00080000 */

#define	SYSCFG_CFGR2_PA6_CDEN SYSCFG_CFGR2_PA6_CDEN_Msk

#define	SYSCFG_CFGR2_PA13_CDEN_Pos (20U)

#define	SYSCFG_CFGR2_PA13_CDEN_Msk (0x1UL << SYSCFG_CFGR2_PA13_CDEN_Pos) /* 0x00100000 */

#define	SYSCFG_CFGR2_PA13_CDEN SYSCFG_CFGR2_PA13_CDEN_Msk

#define	SYSCFG_CFGR2_PB0_CDEN_Pos (21U)

#define	SYSCFG_CFGR2_PB0_CDEN_Msk (0x1UL << SYSCFG_CFGR2_PB0_CDEN_Pos) /* 0x00200000 */

#define	SYSCFG_CFGR2_PB0_CDEN SYSCFG_CFGR2_PB0_CDEN_Msk

#define	SYSCFG_CFGR2_PB1_CDEN_Pos (22U)

#define	SYSCFG_CFGR2_PB1_CDEN_Msk (0x1UL << SYSCFG_CFGR2_PB1_CDEN_Pos) /* 0x00400000 */

#define	SYSCFG_CFGR2_PB1_CDEN SYSCFG_CFGR2_PB1_CDEN_Msk

#define	SYSCFG_CFGR2_PB2_CDEN_Pos (23U)

#define	SYSCFG_CFGR2_PB2_CDEN_Msk (0x1UL << SYSCFG_CFGR2_PB2_CDEN_Pos) /* 0x00800000 */

#define	SYSCFG_CFGR2_PB2_CDEN SYSCFG_CFGR2_PB2_CDEN_Msk

#define	SYSCFG_ITLINE0_SR_EWDG_Pos (0U)

#define	SYSCFG_ITLINE0_SR_EWDG_Msk (0x1UL << SYSCFG_ITLINE0_SR_EWDG_Pos)

#define	SYSCFG_ITLINE0_SR_EWDG SYSCFG_ITLINE0_SR_EWDG_Msk

#define	SYSCFG_ITLINE2_SR_TAMPER_Pos (0U)

#define	SYSCFG_ITLINE2_SR_TAMPER_Msk (0x1UL << SYSCFG_ITLINE2_SR_TAMPER_Pos)

#define	SYSCFG_ITLINE2_SR_TAMPER SYSCFG_ITLINE2_SR_TAMPER_Msk

#define	SYSCFG_ITLINE2_SR_RTC_Pos (1U)

#define	SYSCFG_ITLINE2_SR_RTC_Msk (0x1UL << SYSCFG_ITLINE2_SR_RTC_Pos)

#define	SYSCFG_ITLINE2_SR_RTC SYSCFG_ITLINE2_SR_RTC_Msk

#define	SYSCFG_ITLINE3_SR_FLASH_ECC_Pos (0U)

#define	SYSCFG_ITLINE3_SR_FLASH_ECC_Msk (0x1UL << SYSCFG_ITLINE3_SR_FLASH_ECC_Pos)

#define	SYSCFG_ITLINE3_SR_FLASH_ECC SYSCFG_ITLINE3_SR_FLASH_ECC_Msk

#define	SYSCFG_ITLINE3_SR_FLASH_ITF_Pos (1U)

#define	SYSCFG_ITLINE3_SR_FLASH_ITF_Msk (0x1UL << SYSCFG_ITLINE3_SR_FLASH_ITF_Pos)

#define	SYSCFG_ITLINE3_SR_FLASH_ITF SYSCFG_ITLINE3_SR_FLASH_ITF_Msk

#define	SYSCFG_ITLINE4_SR_CLK_CTRL_Pos (0U)

#define	SYSCFG_ITLINE4_SR_CLK_CTRL_Msk (0x1UL << SYSCFG_ITLINE4_SR_CLK_CTRL_Pos)

#define	SYSCFG_ITLINE4_SR_CLK_CTRL SYSCFG_ITLINE4_SR_CLK_CTRL_Msk

#define	SYSCFG_ITLINE5_SR_EXTI0_Pos (0U)

#define	SYSCFG_ITLINE5_SR_EXTI0_Msk (0x1UL << SYSCFG_ITLINE5_SR_EXTI0_Pos)

#define	SYSCFG_ITLINE5_SR_EXTI0 SYSCFG_ITLINE5_SR_EXTI0_Msk

#define	SYSCFG_ITLINE5_SR_EXTI1_Pos (1U)

#define	SYSCFG_ITLINE5_SR_EXTI1_Msk (0x1UL << SYSCFG_ITLINE5_SR_EXTI1_Pos)

#define	SYSCFG_ITLINE5_SR_EXTI1 SYSCFG_ITLINE5_SR_EXTI1_Msk

#define	SYSCFG_ITLINE6_SR_EXTI2_Pos (0U)

#define	SYSCFG_ITLINE6_SR_EXTI2_Msk (0x1UL << SYSCFG_ITLINE6_SR_EXTI2_Pos)

#define	SYSCFG_ITLINE6_SR_EXTI2 SYSCFG_ITLINE6_SR_EXTI2_Msk

#define	SYSCFG_ITLINE6_SR_EXTI3_Pos (1U)

#define	SYSCFG_ITLINE6_SR_EXTI3_Msk (0x1UL << SYSCFG_ITLINE6_SR_EXTI3_Pos)

#define	SYSCFG_ITLINE6_SR_EXTI3 SYSCFG_ITLINE6_SR_EXTI3_Msk

#define	SYSCFG_ITLINE7_SR_EXTI4_Pos (0U)

#define	SYSCFG_ITLINE7_SR_EXTI4_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI4_Pos)

#define	SYSCFG_ITLINE7_SR_EXTI4 SYSCFG_ITLINE7_SR_EXTI4_Msk

#define	SYSCFG_ITLINE7_SR_EXTI5_Pos (1U)

#define	SYSCFG_ITLINE7_SR_EXTI5_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI5_Pos)

#define	SYSCFG_ITLINE7_SR_EXTI5 SYSCFG_ITLINE7_SR_EXTI5_Msk

#define	SYSCFG_ITLINE7_SR_EXTI6_Pos (2U)

#define	SYSCFG_ITLINE7_SR_EXTI6_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI6_Pos)

#define	SYSCFG_ITLINE7_SR_EXTI6 SYSCFG_ITLINE7_SR_EXTI6_Msk

#define	SYSCFG_ITLINE7_SR_EXTI7_Pos (3U)

#define	SYSCFG_ITLINE7_SR_EXTI7_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI7_Pos)

#define	SYSCFG_ITLINE7_SR_EXTI7 SYSCFG_ITLINE7_SR_EXTI7_Msk

#define	SYSCFG_ITLINE7_SR_EXTI8_Pos (4U)

#define	SYSCFG_ITLINE7_SR_EXTI8_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI8_Pos)

#define	SYSCFG_ITLINE7_SR_EXTI8 SYSCFG_ITLINE7_SR_EXTI8_Msk

#define	SYSCFG_ITLINE7_SR_EXTI9_Pos (5U)

#define	SYSCFG_ITLINE7_SR_EXTI9_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI9_Pos)

#define	SYSCFG_ITLINE7_SR_EXTI9 SYSCFG_ITLINE7_SR_EXTI9_Msk

#define	SYSCFG_ITLINE7_SR_EXTI10_Pos (6U)

#define	SYSCFG_ITLINE7_SR_EXTI10_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI10_Pos)

#define	SYSCFG_ITLINE7_SR_EXTI10 SYSCFG_ITLINE7_SR_EXTI10_Msk

#define	SYSCFG_ITLINE7_SR_EXTI11_Pos (7U)

#define	SYSCFG_ITLINE7_SR_EXTI11_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI11_Pos)

#define	SYSCFG_ITLINE7_SR_EXTI11 SYSCFG_ITLINE7_SR_EXTI11_Msk

#define	SYSCFG_ITLINE7_SR_EXTI12_Pos (8U)

#define	SYSCFG_ITLINE7_SR_EXTI12_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI12_Pos)

#define	SYSCFG_ITLINE7_SR_EXTI12 SYSCFG_ITLINE7_SR_EXTI12_Msk

#define	SYSCFG_ITLINE7_SR_EXTI13_Pos (9U)

#define	SYSCFG_ITLINE7_SR_EXTI13_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI13_Pos)

#define	SYSCFG_ITLINE7_SR_EXTI13 SYSCFG_ITLINE7_SR_EXTI13_Msk

#define	SYSCFG_ITLINE7_SR_EXTI14_Pos (10U)

#define	SYSCFG_ITLINE7_SR_EXTI14_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI14_Pos)

#define	SYSCFG_ITLINE7_SR_EXTI14 SYSCFG_ITLINE7_SR_EXTI14_Msk

#define	SYSCFG_ITLINE7_SR_EXTI15_Pos (11U)

#define	SYSCFG_ITLINE7_SR_EXTI15_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI15_Pos)

#define	SYSCFG_ITLINE7_SR_EXTI15 SYSCFG_ITLINE7_SR_EXTI15_Msk

#define	SYSCFG_ITLINE9_SR_DMA1_CH1_Pos (0U)

#define	SYSCFG_ITLINE9_SR_DMA1_CH1_Msk (0x1UL << SYSCFG_ITLINE9_SR_DMA1_CH1_Pos)

#define	SYSCFG_ITLINE9_SR_DMA1_CH1 SYSCFG_ITLINE9_SR_DMA1_CH1_Msk

#define	SYSCFG_ITLINE10_SR_DMA1_CH2_Pos (0U)

#define	SYSCFG_ITLINE10_SR_DMA1_CH2_Msk (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH2_Pos)

#define	SYSCFG_ITLINE10_SR_DMA1_CH2 SYSCFG_ITLINE10_SR_DMA1_CH2_Msk

#define	SYSCFG_ITLINE10_SR_DMA1_CH3_Pos (1U)

#define	SYSCFG_ITLINE10_SR_DMA1_CH3_Msk (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH3_Pos)

#define	SYSCFG_ITLINE10_SR_DMA1_CH3 SYSCFG_ITLINE10_SR_DMA1_CH3_Msk

#define	SYSCFG_ITLINE11_SR_DMAMUX1_Pos (0U)

#define	SYSCFG_ITLINE11_SR_DMAMUX1_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMAMUX1_Pos)

#define	SYSCFG_ITLINE11_SR_DMAMUX1 SYSCFG_ITLINE11_SR_DMAMUX1_Msk

#define	SYSCFG_ITLINE11_SR_DMA1_CH4_Pos (1U)

#define	SYSCFG_ITLINE11_SR_DMA1_CH4_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH4_Pos)

#define	SYSCFG_ITLINE11_SR_DMA1_CH4 SYSCFG_ITLINE11_SR_DMA1_CH4_Msk

#define	SYSCFG_ITLINE11_SR_DMA1_CH5_Pos (2U)

#define	SYSCFG_ITLINE11_SR_DMA1_CH5_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH5_Pos)

#define	SYSCFG_ITLINE11_SR_DMA1_CH5 SYSCFG_ITLINE11_SR_DMA1_CH5_Msk

#define	SYSCFG_ITLINE12_SR_ADC_Pos (0U)

#define	SYSCFG_ITLINE12_SR_ADC_Msk (0x1UL << SYSCFG_ITLINE12_SR_ADC_Pos)

#define	SYSCFG_ITLINE12_SR_ADC SYSCFG_ITLINE12_SR_ADC_Msk

#define	SYSCFG_ITLINE13_SR_TIM1_CCU_Pos (0U)

#define	SYSCFG_ITLINE13_SR_TIM1_CCU_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_CCU_Pos)

#define	SYSCFG_ITLINE13_SR_TIM1_CCU SYSCFG_ITLINE13_SR_TIM1_CCU_Msk

#define	SYSCFG_ITLINE13_SR_TIM1_TRG_Pos (1U)

#define	SYSCFG_ITLINE13_SR_TIM1_TRG_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_TRG_Pos)

#define	SYSCFG_ITLINE13_SR_TIM1_TRG SYSCFG_ITLINE13_SR_TIM1_TRG_Msk

#define	SYSCFG_ITLINE13_SR_TIM1_UPD_Pos (2U)

#define	SYSCFG_ITLINE13_SR_TIM1_UPD_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_UPD_Pos)

#define	SYSCFG_ITLINE13_SR_TIM1_UPD SYSCFG_ITLINE13_SR_TIM1_UPD_Msk

#define	SYSCFG_ITLINE13_SR_TIM1_BRK_Pos (3U)

#define	SYSCFG_ITLINE13_SR_TIM1_BRK_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_BRK_Pos)

#define	SYSCFG_ITLINE13_SR_TIM1_BRK SYSCFG_ITLINE13_SR_TIM1_BRK_Msk

#define	SYSCFG_ITLINE14_SR_TIM1_CC_Pos (0U)

#define	SYSCFG_ITLINE14_SR_TIM1_CC_Msk (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC_Pos)

#define	SYSCFG_ITLINE14_SR_TIM1_CC SYSCFG_ITLINE14_SR_TIM1_CC_Msk

#define	SYSCFG_ITLINE16_SR_TIM3_GLB_Pos (0U)

#define	SYSCFG_ITLINE16_SR_TIM3_GLB_Msk (0x1UL << SYSCFG_ITLINE16_SR_TIM3_GLB_Pos)

#define	SYSCFG_ITLINE16_SR_TIM3_GLB SYSCFG_ITLINE16_SR_TIM3_GLB_Msk

#define	SYSCFG_ITLINE19_SR_TIM14_GLB_Pos (0U)

#define	SYSCFG_ITLINE19_SR_TIM14_GLB_Msk (0x1UL << SYSCFG_ITLINE19_SR_TIM14_GLB_Pos)

#define	SYSCFG_ITLINE19_SR_TIM14_GLB SYSCFG_ITLINE19_SR_TIM14_GLB_Msk

#define	SYSCFG_ITLINE21_SR_TIM16_GLB_Pos (0U)

#define	SYSCFG_ITLINE21_SR_TIM16_GLB_Msk (0x1UL << SYSCFG_ITLINE21_SR_TIM16_GLB_Pos)

#define	SYSCFG_ITLINE21_SR_TIM16_GLB SYSCFG_ITLINE21_SR_TIM16_GLB_Msk

#define	SYSCFG_ITLINE22_SR_TIM17_GLB_Pos (0U)

#define	SYSCFG_ITLINE22_SR_TIM17_GLB_Msk (0x1UL << SYSCFG_ITLINE22_SR_TIM17_GLB_Pos)

#define	SYSCFG_ITLINE22_SR_TIM17_GLB SYSCFG_ITLINE22_SR_TIM17_GLB_Msk

#define	SYSCFG_ITLINE23_SR_I2C1_GLB_Pos (0U)

#define	SYSCFG_ITLINE23_SR_I2C1_GLB_Msk (0x1UL << SYSCFG_ITLINE23_SR_I2C1_GLB_Pos)

#define	SYSCFG_ITLINE23_SR_I2C1_GLB SYSCFG_ITLINE23_SR_I2C1_GLB_Msk

#define	SYSCFG_ITLINE24_SR_I2C2_GLB_Pos (0U)

#define	SYSCFG_ITLINE24_SR_I2C2_GLB_Msk (0x1UL << SYSCFG_ITLINE24_SR_I2C2_GLB_Pos)

#define	SYSCFG_ITLINE24_SR_I2C2_GLB SYSCFG_ITLINE24_SR_I2C2_GLB_Msk

#define	SYSCFG_ITLINE25_SR_SPI1_Pos (0U)

#define	SYSCFG_ITLINE25_SR_SPI1_Msk (0x1UL << SYSCFG_ITLINE25_SR_SPI1_Pos)

#define	SYSCFG_ITLINE25_SR_SPI1 SYSCFG_ITLINE25_SR_SPI1_Msk

#define	SYSCFG_ITLINE26_SR_SPI2_Pos (0U)

#define	SYSCFG_ITLINE26_SR_SPI2_Msk (0x1UL << SYSCFG_ITLINE26_SR_SPI2_Pos)

#define	SYSCFG_ITLINE26_SR_SPI2 SYSCFG_ITLINE26_SR_SPI2_Msk

#define	SYSCFG_ITLINE27_SR_USART1_GLB_Pos (0U)

#define	SYSCFG_ITLINE27_SR_USART1_GLB_Msk (0x1UL << SYSCFG_ITLINE27_SR_USART1_GLB_Pos)

#define	SYSCFG_ITLINE27_SR_USART1_GLB SYSCFG_ITLINE27_SR_USART1_GLB_Msk

#define	SYSCFG_ITLINE28_SR_USART2_GLB_Pos (0U)

#define	SYSCFG_ITLINE28_SR_USART2_GLB_Msk (0x1UL << SYSCFG_ITLINE28_SR_USART2_GLB_Pos)

#define	SYSCFG_ITLINE28_SR_USART2_GLB SYSCFG_ITLINE28_SR_USART2_GLB_Msk

#define	TIM_CR1_CEN_Pos (0U)

#define	TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos)

#define	TIM_CR1_CEN TIM_CR1_CEN_Msk

#define	TIM_CR1_UDIS_Pos (1U)

#define	TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos)

#define	TIM_CR1_UDIS TIM_CR1_UDIS_Msk

#define	TIM_CR1_URS_Pos (2U)

#define	TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos)

#define	TIM_CR1_URS TIM_CR1_URS_Msk

#define	TIM_CR1_OPM_Pos (3U)

#define	TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos)

#define	TIM_CR1_OPM TIM_CR1_OPM_Msk

#define	TIM_CR1_DIR_Pos (4U)

#define	TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos)

#define	TIM_CR1_DIR TIM_CR1_DIR_Msk

#define	TIM_CR1_CMS_Pos (5U)

#define	TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos)

#define	TIM_CR1_CMS TIM_CR1_CMS_Msk

#define	TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos)

#define	TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos)

#define	TIM_CR1_ARPE_Pos (7U)

#define	TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos)

#define	TIM_CR1_ARPE TIM_CR1_ARPE_Msk

#define	TIM_CR1_CKD_Pos (8U)

#define	TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos)

#define	TIM_CR1_CKD TIM_CR1_CKD_Msk

#define	TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos)

#define	TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos)

#define	TIM_CR1_UIFREMAP_Pos (11U)

#define	TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos)

#define	TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk

#define	TIM_CR2_CCPC_Pos (0U)

#define	TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos)

#define	TIM_CR2_CCPC TIM_CR2_CCPC_Msk

#define	TIM_CR2_CCUS_Pos (2U)

#define	TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos)

#define	TIM_CR2_CCUS TIM_CR2_CCUS_Msk

#define	TIM_CR2_CCDS_Pos (3U)

#define	TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos)

#define	TIM_CR2_CCDS TIM_CR2_CCDS_Msk

#define	TIM_CR2_MMS_Pos (4U)

#define	TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos)

#define	TIM_CR2_MMS TIM_CR2_MMS_Msk

#define	TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos)

#define	TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos)

#define	TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos)

#define	TIM_CR2_TI1S_Pos (7U)

#define	TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos)

#define	TIM_CR2_TI1S TIM_CR2_TI1S_Msk

#define	TIM_CR2_OIS1_Pos (8U)

#define	TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos)

#define	TIM_CR2_OIS1 TIM_CR2_OIS1_Msk

#define	TIM_CR2_OIS1N_Pos (9U)

#define	TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos)

#define	TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk

#define	TIM_CR2_OIS2_Pos (10U)

#define	TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos)

#define	TIM_CR2_OIS2 TIM_CR2_OIS2_Msk

#define	TIM_CR2_OIS2N_Pos (11U)

#define	TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos)

#define	TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk

#define	TIM_CR2_OIS3_Pos (12U)

#define	TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos)

#define	TIM_CR2_OIS3 TIM_CR2_OIS3_Msk

#define	TIM_CR2_OIS3N_Pos (13U)

#define	TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos)

#define	TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk

#define	TIM_CR2_OIS4_Pos (14U)

#define	TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos)

#define	TIM_CR2_OIS4 TIM_CR2_OIS4_Msk

#define	TIM_CR2_OIS5_Pos (16U)

#define	TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos)

#define	TIM_CR2_OIS5 TIM_CR2_OIS5_Msk

#define	TIM_CR2_OIS6_Pos (18U)

#define	TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos)

#define	TIM_CR2_OIS6 TIM_CR2_OIS6_Msk

#define	TIM_CR2_MMS2_Pos (20U)

#define	TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos)

#define	TIM_CR2_MMS2 TIM_CR2_MMS2_Msk

#define	TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos)

#define	TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos)

#define	TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos)

#define	TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos)

#define	TIM_SMCR_SMS_Pos (0U)

#define	TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos)

#define	TIM_SMCR_SMS TIM_SMCR_SMS_Msk

#define	TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos)

#define	TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos)

#define	TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos)

#define	TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos)

#define	TIM_SMCR_OCCS_Pos (3U)

#define	TIM_SMCR_OCCS_Msk (0x1UL << TIM_SMCR_OCCS_Pos)

#define	TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk

#define	TIM_SMCR_TS_Pos (4U)

#define	TIM_SMCR_TS_Msk (0x30007UL << TIM_SMCR_TS_Pos)

#define	TIM_SMCR_TS TIM_SMCR_TS_Msk

#define	TIM_SMCR_TS_0 (0x00001UL << TIM_SMCR_TS_Pos)

#define	TIM_SMCR_TS_1 (0x00002UL << TIM_SMCR_TS_Pos)

#define	TIM_SMCR_TS_2 (0x00004UL << TIM_SMCR_TS_Pos)

#define	TIM_SMCR_TS_3 (0x10000UL << TIM_SMCR_TS_Pos)

#define	TIM_SMCR_TS_4 (0x20000UL << TIM_SMCR_TS_Pos)

#define	TIM_SMCR_MSM_Pos (7U)

#define	TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos)

#define	TIM_SMCR_MSM TIM_SMCR_MSM_Msk

#define	TIM_SMCR_ETF_Pos (8U)

#define	TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos)

#define	TIM_SMCR_ETF TIM_SMCR_ETF_Msk

#define	TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos)

#define	TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos)

#define	TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos)

#define	TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos)

#define	TIM_SMCR_ETPS_Pos (12U)

#define	TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos)

#define	TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk

#define	TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos)

#define	TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos)

#define	TIM_SMCR_ECE_Pos (14U)

#define	TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos)

#define	TIM_SMCR_ECE TIM_SMCR_ECE_Msk

#define	TIM_SMCR_ETP_Pos (15U)

#define	TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos)

#define	TIM_SMCR_ETP TIM_SMCR_ETP_Msk

#define	TIM_DIER_UIE_Pos (0U)

#define	TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos)

#define	TIM_DIER_UIE TIM_DIER_UIE_Msk

#define	TIM_DIER_CC1IE_Pos (1U)

#define	TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos)

#define	TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk

#define	TIM_DIER_CC2IE_Pos (2U)

#define	TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos)

#define	TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk

#define	TIM_DIER_CC3IE_Pos (3U)

#define	TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos)

#define	TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk

#define	TIM_DIER_CC4IE_Pos (4U)

#define	TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos)

#define	TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk

#define	TIM_DIER_COMIE_Pos (5U)

#define	TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos)

#define	TIM_DIER_COMIE TIM_DIER_COMIE_Msk

#define	TIM_DIER_TIE_Pos (6U)

#define	TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos)

#define	TIM_DIER_TIE TIM_DIER_TIE_Msk

#define	TIM_DIER_BIE_Pos (7U)

#define	TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos)

#define	TIM_DIER_BIE TIM_DIER_BIE_Msk

#define	TIM_DIER_UDE_Pos (8U)

#define	TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos)

#define	TIM_DIER_UDE TIM_DIER_UDE_Msk

#define	TIM_DIER_CC1DE_Pos (9U)

#define	TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos)

#define	TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk

#define	TIM_DIER_CC2DE_Pos (10U)

#define	TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos)

#define	TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk

#define	TIM_DIER_CC3DE_Pos (11U)

#define	TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos)

#define	TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk

#define	TIM_DIER_CC4DE_Pos (12U)

#define	TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos)

#define	TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk

#define	TIM_DIER_COMDE_Pos (13U)

#define	TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos)

#define	TIM_DIER_COMDE TIM_DIER_COMDE_Msk

#define	TIM_DIER_TDE_Pos (14U)

#define	TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos)

#define	TIM_DIER_TDE TIM_DIER_TDE_Msk

#define	TIM_SR_UIF_Pos (0U)

#define	TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos)

#define	TIM_SR_UIF TIM_SR_UIF_Msk

#define	TIM_SR_CC1IF_Pos (1U)

#define	TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos)

#define	TIM_SR_CC1IF TIM_SR_CC1IF_Msk

#define	TIM_SR_CC2IF_Pos (2U)

#define	TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos)

#define	TIM_SR_CC2IF TIM_SR_CC2IF_Msk

#define	TIM_SR_CC3IF_Pos (3U)

#define	TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos)

#define	TIM_SR_CC3IF TIM_SR_CC3IF_Msk

#define	TIM_SR_CC4IF_Pos (4U)

#define	TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos)

#define	TIM_SR_CC4IF TIM_SR_CC4IF_Msk

#define	TIM_SR_COMIF_Pos (5U)

#define	TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos)

#define	TIM_SR_COMIF TIM_SR_COMIF_Msk

#define	TIM_SR_TIF_Pos (6U)

#define	TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos)

#define	TIM_SR_TIF TIM_SR_TIF_Msk

#define	TIM_SR_BIF_Pos (7U)

#define	TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos)

#define	TIM_SR_BIF TIM_SR_BIF_Msk

#define	TIM_SR_B2IF_Pos (8U)

#define	TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos)

#define	TIM_SR_B2IF TIM_SR_B2IF_Msk

#define	TIM_SR_CC1OF_Pos (9U)

#define	TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos)

#define	TIM_SR_CC1OF TIM_SR_CC1OF_Msk

#define	TIM_SR_CC2OF_Pos (10U)

#define	TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos)

#define	TIM_SR_CC2OF TIM_SR_CC2OF_Msk

#define	TIM_SR_CC3OF_Pos (11U)

#define	TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos)

#define	TIM_SR_CC3OF TIM_SR_CC3OF_Msk

#define	TIM_SR_CC4OF_Pos (12U)

#define	TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos)

#define	TIM_SR_CC4OF TIM_SR_CC4OF_Msk

#define	TIM_SR_SBIF_Pos (13U)

#define	TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos)

#define	TIM_SR_SBIF TIM_SR_SBIF_Msk

#define	TIM_SR_CC5IF_Pos (16U)

#define	TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos)

#define	TIM_SR_CC5IF TIM_SR_CC5IF_Msk

#define	TIM_SR_CC6IF_Pos (17U)

#define	TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos)

#define	TIM_SR_CC6IF TIM_SR_CC6IF_Msk

#define	TIM_EGR_UG_Pos (0U)

#define	TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos)

#define	TIM_EGR_UG TIM_EGR_UG_Msk

#define	TIM_EGR_CC1G_Pos (1U)

#define	TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos)

#define	TIM_EGR_CC1G TIM_EGR_CC1G_Msk

#define	TIM_EGR_CC2G_Pos (2U)

#define	TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos)

#define	TIM_EGR_CC2G TIM_EGR_CC2G_Msk

#define	TIM_EGR_CC3G_Pos (3U)

#define	TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos)

#define	TIM_EGR_CC3G TIM_EGR_CC3G_Msk

#define	TIM_EGR_CC4G_Pos (4U)

#define	TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos)

#define	TIM_EGR_CC4G TIM_EGR_CC4G_Msk

#define	TIM_EGR_COMG_Pos (5U)

#define	TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos)

#define	TIM_EGR_COMG TIM_EGR_COMG_Msk

#define	TIM_EGR_TG_Pos (6U)

#define	TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos)

#define	TIM_EGR_TG TIM_EGR_TG_Msk

#define	TIM_EGR_BG_Pos (7U)

#define	TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos)

#define	TIM_EGR_BG TIM_EGR_BG_Msk

#define	TIM_EGR_B2G_Pos (8U)

#define	TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos)

#define	TIM_EGR_B2G TIM_EGR_B2G_Msk

#define	TIM_CCMR1_CC1S_Pos (0U)

#define	TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos)

#define	TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk

#define	TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos)

#define	TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos)

#define	TIM_CCMR1_OC1FE_Pos (2U)

#define	TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos)

#define	TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk

#define	TIM_CCMR1_OC1PE_Pos (3U)

#define	TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos)

#define	TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk

#define	TIM_CCMR1_OC1M_Pos (4U)

#define	TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos)

#define	TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk

#define	TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos)

#define	TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos)

#define	TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos)

#define	TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos)

#define	TIM_CCMR1_OC1CE_Pos (7U)

#define	TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos)

#define	TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk

#define	TIM_CCMR1_CC2S_Pos (8U)

#define	TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos)

#define	TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk

#define	TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos)

#define	TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos)

#define	TIM_CCMR1_OC2FE_Pos (10U)

#define	TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos)

#define	TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk

#define	TIM_CCMR1_OC2PE_Pos (11U)

#define	TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos)

#define	TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk

#define	TIM_CCMR1_OC2M_Pos (12U)

#define	TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos)

#define	TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk

#define	TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos)

#define	TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos)

#define	TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos)

#define	TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos)

#define	TIM_CCMR1_OC2CE_Pos (15U)

#define	TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos)

#define	TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk

#define	TIM_CCMR1_IC1PSC_Pos (2U)

#define	TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos)

#define	TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk

#define	TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos)

#define	TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos)

#define	TIM_CCMR1_IC1F_Pos (4U)

#define	TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos)

#define	TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk

#define	TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos)

#define	TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos)

#define	TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos)

#define	TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos)

#define	TIM_CCMR1_IC2PSC_Pos (10U)

#define	TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos)

#define	TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk

#define	TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos)

#define	TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos)

#define	TIM_CCMR1_IC2F_Pos (12U)

#define	TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos)

#define	TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk

#define	TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos)

#define	TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos)

#define	TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos)

#define	TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos)

#define	TIM_CCMR2_CC3S_Pos (0U)

#define	TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos)

#define	TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk

#define	TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos)

#define	TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos)

#define	TIM_CCMR2_OC3FE_Pos (2U)

#define	TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos)

#define	TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk

#define	TIM_CCMR2_OC3PE_Pos (3U)

#define	TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos)

#define	TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk

#define	TIM_CCMR2_OC3M_Pos (4U)

#define	TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos)

#define	TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk

#define	TIM_CCMR2_OC3M_0 (0x0001UL << TIM_CCMR2_OC3M_Pos)

#define	TIM_CCMR2_OC3M_1 (0x0002UL << TIM_CCMR2_OC3M_Pos)

#define	TIM_CCMR2_OC3M_2 (0x0004UL << TIM_CCMR2_OC3M_Pos)

#define	TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos)

#define	TIM_CCMR2_OC3CE_Pos (7U)

#define	TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos)

#define	TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk

#define	TIM_CCMR2_CC4S_Pos (8U)

#define	TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos)

#define	TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk

#define	TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos)

#define	TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos)

#define	TIM_CCMR2_OC4FE_Pos (10U)

#define	TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos)

#define	TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk

#define	TIM_CCMR2_OC4PE_Pos (11U)

#define	TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos)

#define	TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk

#define	TIM_CCMR2_OC4M_Pos (12U)

#define	TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos)

#define	TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk

#define	TIM_CCMR2_OC4M_0 (0x0001UL << TIM_CCMR2_OC4M_Pos)

#define	TIM_CCMR2_OC4M_1 (0x0002UL << TIM_CCMR2_OC4M_Pos)

#define	TIM_CCMR2_OC4M_2 (0x0004UL << TIM_CCMR2_OC4M_Pos)

#define	TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos)

#define	TIM_CCMR2_OC4CE_Pos (15U)

#define	TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos)

#define	TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk

#define	TIM_CCMR2_IC3PSC_Pos (2U)

#define	TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos)

#define	TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk

#define	TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos)

#define	TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos)

#define	TIM_CCMR2_IC3F_Pos (4U)

#define	TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos)

#define	TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk

#define	TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos)

#define	TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos)

#define	TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos)

#define	TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos)

#define	TIM_CCMR2_IC4PSC_Pos (10U)

#define	TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos)

#define	TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk

#define	TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos)

#define	TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos)

#define	TIM_CCMR2_IC4F_Pos (12U)

#define	TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos)

#define	TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk

#define	TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos)

#define	TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos)

#define	TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos)

#define	TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos)

#define	TIM_CCMR3_OC5FE_Pos (2U)

#define	TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos)

#define	TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk

#define	TIM_CCMR3_OC5PE_Pos (3U)

#define	TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos)

#define	TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk

#define	TIM_CCMR3_OC5M_Pos (4U)

#define	TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos)

#define	TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk

#define	TIM_CCMR3_OC5M_0 (0x0001UL << TIM_CCMR3_OC5M_Pos)

#define	TIM_CCMR3_OC5M_1 (0x0002UL << TIM_CCMR3_OC5M_Pos)

#define	TIM_CCMR3_OC5M_2 (0x0004UL << TIM_CCMR3_OC5M_Pos)

#define	TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos)

#define	TIM_CCMR3_OC5CE_Pos (7U)

#define	TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos)

#define	TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk

#define	TIM_CCMR3_OC6FE_Pos (10U)

#define	TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos)

#define	TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk

#define	TIM_CCMR3_OC6PE_Pos (11U)

#define	TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos)

#define	TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk

#define	TIM_CCMR3_OC6M_Pos (12U)

#define	TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos)

#define	TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk

#define	TIM_CCMR3_OC6M_0 (0x0001UL << TIM_CCMR3_OC6M_Pos)

#define	TIM_CCMR3_OC6M_1 (0x0002UL << TIM_CCMR3_OC6M_Pos)

#define	TIM_CCMR3_OC6M_2 (0x0004UL << TIM_CCMR3_OC6M_Pos)

#define	TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos)

#define	TIM_CCMR3_OC6CE_Pos (15U)

#define	TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos)

#define	TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk

#define	TIM_CCER_CC1E_Pos (0U)

#define	TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos)

#define	TIM_CCER_CC1E TIM_CCER_CC1E_Msk

#define	TIM_CCER_CC1P_Pos (1U)

#define	TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos)

#define	TIM_CCER_CC1P TIM_CCER_CC1P_Msk

#define	TIM_CCER_CC1NE_Pos (2U)

#define	TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos)

#define	TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk

#define	TIM_CCER_CC1NP_Pos (3U)

#define	TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos)

#define	TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk

#define	TIM_CCER_CC2E_Pos (4U)

#define	TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos)

#define	TIM_CCER_CC2E TIM_CCER_CC2E_Msk

#define	TIM_CCER_CC2P_Pos (5U)

#define	TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos)

#define	TIM_CCER_CC2P TIM_CCER_CC2P_Msk

#define	TIM_CCER_CC2NE_Pos (6U)

#define	TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos)

#define	TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk

#define	TIM_CCER_CC2NP_Pos (7U)

#define	TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos)

#define	TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk

#define	TIM_CCER_CC3E_Pos (8U)

#define	TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos)

#define	TIM_CCER_CC3E TIM_CCER_CC3E_Msk

#define	TIM_CCER_CC3P_Pos (9U)

#define	TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos)

#define	TIM_CCER_CC3P TIM_CCER_CC3P_Msk

#define	TIM_CCER_CC3NE_Pos (10U)

#define	TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos)

#define	TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk

#define	TIM_CCER_CC3NP_Pos (11U)

#define	TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos)

#define	TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk

#define	TIM_CCER_CC4E_Pos (12U)

#define	TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos)

#define	TIM_CCER_CC4E TIM_CCER_CC4E_Msk

#define	TIM_CCER_CC4P_Pos (13U)

#define	TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos)

#define	TIM_CCER_CC4P TIM_CCER_CC4P_Msk

#define	TIM_CCER_CC4NP_Pos (15U)

#define	TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos)

#define	TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk

#define	TIM_CCER_CC5E_Pos (16U)

#define	TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos)

#define	TIM_CCER_CC5E TIM_CCER_CC5E_Msk

#define	TIM_CCER_CC5P_Pos (17U)

#define	TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos)

#define	TIM_CCER_CC5P TIM_CCER_CC5P_Msk

#define	TIM_CCER_CC6E_Pos (20U)

#define	TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos)

#define	TIM_CCER_CC6E TIM_CCER_CC6E_Msk

#define	TIM_CCER_CC6P_Pos (21U)

#define	TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos)

#define	TIM_CCER_CC6P TIM_CCER_CC6P_Msk

#define	TIM_CNT_CNT_Pos (0U)

#define	TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)

#define	TIM_CNT_CNT TIM_CNT_CNT_Msk

#define	TIM_CNT_UIFCPY_Pos (31U)

#define	TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos)

#define	TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk

#define	TIM_PSC_PSC_Pos (0U)

#define	TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos)

#define	TIM_PSC_PSC TIM_PSC_PSC_Msk

#define	TIM_ARR_ARR_Pos (0U)

#define	TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)

#define	TIM_ARR_ARR TIM_ARR_ARR_Msk

#define	TIM_RCR_REP_Pos (0U)

#define	TIM_RCR_REP_Msk (0xFFFFUL << TIM_RCR_REP_Pos)

#define	TIM_RCR_REP TIM_RCR_REP_Msk

#define	TIM_CCR1_CCR1_Pos (0U)

#define	TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos)

#define	TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk

#define	TIM_CCR2_CCR2_Pos (0U)

#define	TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos)

#define	TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk

#define	TIM_CCR3_CCR3_Pos (0U)

#define	TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos)

#define	TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk

#define	TIM_CCR4_CCR4_Pos (0U)

#define	TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos)

#define	TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk

#define	TIM_CCR5_CCR5_Pos (0U)

#define	TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)

#define	TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk

#define	TIM_CCR5_GC5C1_Pos (29U)

#define	TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos)

#define	TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk

#define	TIM_CCR5_GC5C2_Pos (30U)

#define	TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos)

#define	TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk

#define	TIM_CCR5_GC5C3_Pos (31U)

#define	TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos)

#define	TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk

#define	TIM_CCR6_CCR6_Pos (0U)

#define	TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos)

#define	TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk

#define	TIM_BDTR_DTG_Pos (0U)

#define	TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_DTG TIM_BDTR_DTG_Msk

#define	TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_LOCK_Pos (8U)

#define	TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos)

#define	TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk

#define	TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos)

#define	TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos)

#define	TIM_BDTR_OSSI_Pos (10U)

#define	TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos)

#define	TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk

#define	TIM_BDTR_OSSR_Pos (11U)

#define	TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos)

#define	TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk

#define	TIM_BDTR_BKE_Pos (12U)

#define	TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos)

#define	TIM_BDTR_BKE TIM_BDTR_BKE_Msk

#define	TIM_BDTR_BKP_Pos (13U)

#define	TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos)

#define	TIM_BDTR_BKP TIM_BDTR_BKP_Msk

#define	TIM_BDTR_AOE_Pos (14U)

#define	TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos)

#define	TIM_BDTR_AOE TIM_BDTR_AOE_Msk

#define	TIM_BDTR_MOE_Pos (15U)

#define	TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos)

#define	TIM_BDTR_MOE TIM_BDTR_MOE_Msk

#define	TIM_BDTR_BKF_Pos (16U)

#define	TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos)

#define	TIM_BDTR_BKF TIM_BDTR_BKF_Msk

#define	TIM_BDTR_BK2F_Pos (20U)

#define	TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos)

#define	TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk

#define	TIM_BDTR_BK2E_Pos (24U)

#define	TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos)

#define	TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk

#define	TIM_BDTR_BK2P_Pos (25U)

#define	TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos)

#define	TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk

#define	TIM_BDTR_BKDSRM_Pos (26U)

#define	TIM_BDTR_BKDSRM_Msk (0x1UL << TIM_BDTR_BKDSRM_Pos)

#define	TIM_BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk

#define	TIM_BDTR_BK2DSRM_Pos (27U)

#define	TIM_BDTR_BK2DSRM_Msk (0x1UL << TIM_BDTR_BK2DSRM_Pos)

#define	TIM_BDTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk

#define	TIM_BDTR_BKBID_Pos (28U)

#define	TIM_BDTR_BKBID_Msk (0x1UL << TIM_BDTR_BKBID_Pos)

#define	TIM_BDTR_BKBID TIM_BDTR_BKBID_Msk

#define	TIM_BDTR_BK2BID_Pos (29U)

#define	TIM_BDTR_BK2BID_Msk (0x1UL << TIM_BDTR_BK2BID_Pos)

#define	TIM_BDTR_BK2BID TIM_BDTR_BK2BID_Msk

#define	TIM_DCR_DBA_Pos (0U)

#define	TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos)

#define	TIM_DCR_DBA TIM_DCR_DBA_Msk

#define	TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos)

#define	TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos)

#define	TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos)

#define	TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos)

#define	TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos)

#define	TIM_DCR_DBL_Pos (8U)

#define	TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos)

#define	TIM_DCR_DBL TIM_DCR_DBL_Msk

#define	TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos)

#define	TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos)

#define	TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos)

#define	TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos)

#define	TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos)

#define	TIM_DMAR_DMAB_Pos (0U)

#define	TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos)

#define	TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk

#define	TIM1_OR1_OCREF_CLR_Pos (0U)

#define	TIM1_OR1_OCREF_CLR_Msk (0x1UL << TIM1_OR1_OCREF_CLR_Pos)

#define	TIM1_OR1_OCREF_CLR TIM1_OR1_OCREF_CLR_Msk

#define	TIM1_AF1_BKINE_Pos (0U)

#define	TIM1_AF1_BKINE_Msk (0x1UL << TIM1_AF1_BKINE_Pos)

#define	TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk

#define	TIM1_AF1_BKCMP1E_Pos (1U)

#define	TIM1_AF1_BKCMP1E_Msk (0x1UL << TIM1_AF1_BKCMP1E_Pos)

#define	TIM1_AF1_BKCMP1E TIM1_AF1_BKCMP1E_Msk

#define	TIM1_AF1_BKCMP2E_Pos (2U)

#define	TIM1_AF1_BKCMP2E_Msk (0x1UL << TIM1_AF1_BKCMP2E_Pos)

#define	TIM1_AF1_BKCMP2E TIM1_AF1_BKCMP2E_Msk

#define	TIM1_AF1_BKINP_Pos (9U)

#define	TIM1_AF1_BKINP_Msk (0x1UL << TIM1_AF1_BKINP_Pos)

#define	TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk

#define	TIM1_AF1_BKCMP1P_Pos (10U)

#define	TIM1_AF1_BKCMP1P_Msk (0x1UL << TIM1_AF1_BKCMP1P_Pos)

#define	TIM1_AF1_BKCMP1P TIM1_AF1_BKCMP1P_Msk

#define	TIM1_AF1_BKCMP2P_Pos (11U)

#define	TIM1_AF1_BKCMP2P_Msk (0x1UL << TIM1_AF1_BKCMP2P_Pos)

#define	TIM1_AF1_BKCMP2P TIM1_AF1_BKCMP2P_Msk

#define	TIM1_AF1_ETRSEL_Pos (14U)

#define	TIM1_AF1_ETRSEL_Msk (0xFUL << TIM1_AF1_ETRSEL_Pos)

#define	TIM1_AF1_ETRSEL TIM1_AF1_ETRSEL_Msk

#define	TIM1_AF1_ETRSEL_0 (0x1UL << TIM1_AF1_ETRSEL_Pos)

#define	TIM1_AF1_ETRSEL_1 (0x2UL << TIM1_AF1_ETRSEL_Pos)

#define	TIM1_AF1_ETRSEL_2 (0x4UL << TIM1_AF1_ETRSEL_Pos)

#define	TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos)

#define	TIM1_AF2_BK2INE_Pos (0U)

#define	TIM1_AF2_BK2INE_Msk (0x1UL << TIM1_AF2_BK2INE_Pos)

#define	TIM1_AF2_BK2INE TIM1_AF2_BK2INE_Msk

#define	TIM1_AF2_BK2CMP1E_Pos (1U)

#define	TIM1_AF2_BK2CMP1E_Msk (0x1UL << TIM1_AF2_BK2CMP1E_Pos)

#define	TIM1_AF2_BK2CMP1E TIM1_AF2_BK2CMP1E_Msk

#define	TIM1_AF2_BK2CMP2E_Pos (2U)

#define	TIM1_AF2_BK2CMP2E_Msk (0x1UL << TIM1_AF2_BK2CMP2E_Pos)

#define	TIM1_AF2_BK2CMP2E TIM1_AF2_BK2CMP2E_Msk

#define	TIM1_AF2_BK2INP_Pos (9U)

#define	TIM1_AF2_BK2INP_Msk (0x1UL << TIM1_AF2_BK2INP_Pos)

#define	TIM1_AF2_BK2INP TIM1_AF2_BK2INP_Msk

#define	TIM1_AF2_BK2CMP1P_Pos (10U)

#define	TIM1_AF2_BK2CMP1P_Msk (0x1UL << TIM1_AF2_BK2CMP1P_Pos)

#define	TIM1_AF2_BK2CMP1P TIM1_AF2_BK2CMP1P_Msk

#define	TIM1_AF2_BK2CMP2P_Pos (11U)

#define	TIM1_AF2_BK2CMP2P_Msk (0x1UL << TIM1_AF2_BK2CMP2P_Pos)

#define	TIM1_AF2_BK2CMP2P TIM1_AF2_BK2CMP2P_Msk

#define	TIM3_OR1_OCREF_CLR_Pos (0U)

#define	TIM3_OR1_OCREF_CLR_Msk (0x1UL << TIM3_OR1_OCREF_CLR_Pos)

#define	TIM3_OR1_OCREF_CLR TIM3_OR1_OCREF_CLR_Msk

#define	TIM3_AF1_ETRSEL_Pos (14U)

#define	TIM3_AF1_ETRSEL_Msk (0xFUL << TIM3_AF1_ETRSEL_Pos)

#define	TIM3_AF1_ETRSEL TIM3_AF1_ETRSEL_Msk

#define	TIM3_AF1_ETRSEL_0 (0x1UL << TIM3_AF1_ETRSEL_Pos)

#define	TIM3_AF1_ETRSEL_1 (0x2UL << TIM3_AF1_ETRSEL_Pos)

#define	TIM3_AF1_ETRSEL_2 (0x4UL << TIM3_AF1_ETRSEL_Pos)

#define	TIM3_AF1_ETRSEL_3 (0x8UL << TIM3_AF1_ETRSEL_Pos)

#define	TIM14_AF1_ETRSEL_Pos (14U)

#define	TIM14_AF1_ETRSEL_Msk (0xFUL << TIM14_AF1_ETRSEL_Pos)

#define	TIM14_AF1_ETRSEL TIM14_AF1_ETRSEL_Msk

#define	TIM14_AF1_ETRSEL_0 (0x1UL << TIM14_AF1_ETRSEL_Pos)

#define	TIM14_AF1_ETRSEL_1 (0x2UL << TIM14_AF1_ETRSEL_Pos)

#define	TIM14_AF1_ETRSEL_2 (0x4UL << TIM14_AF1_ETRSEL_Pos)

#define	TIM14_AF1_ETRSEL_3 (0x8UL << TIM14_AF1_ETRSEL_Pos)

#define	TIM16_AF1_BKINE_Pos (0U)

#define	TIM16_AF1_BKINE_Msk (0x1UL << TIM16_AF1_BKINE_Pos)

#define	TIM16_AF1_BKINE TIM16_AF1_BKINE_Msk

#define	TIM16_AF1_BKCMP1E_Pos (1U)

#define	TIM16_AF1_BKCMP1E_Msk (0x1UL << TIM16_AF1_BKCMP1E_Pos)

#define	TIM16_AF1_BKCMP1E TIM16_AF1_BKCMP1E_Msk

#define	TIM16_AF1_BKCMP2E_Pos (2U)

#define	TIM16_AF1_BKCMP2E_Msk (0x1UL << TIM16_AF1_BKCMP2E_Pos)

#define	TIM16_AF1_BKCMP2E TIM16_AF1_BKCMP2E_Msk

#define	TIM16_AF1_BKINP_Pos (9U)

#define	TIM16_AF1_BKINP_Msk (0x1UL << TIM16_AF1_BKINP_Pos)

#define	TIM16_AF1_BKINP TIM16_AF1_BKINP_Msk

#define	TIM16_AF1_BKCMP1P_Pos (10U)

#define	TIM16_AF1_BKCMP1P_Msk (0x1UL << TIM16_AF1_BKCMP1P_Pos)

#define	TIM16_AF1_BKCMP1P TIM16_AF1_BKCMP1P_Msk

#define	TIM16_AF1_BKCMP2P_Pos (11U)

#define	TIM16_AF1_BKCMP2P_Msk (0x1UL << TIM16_AF1_BKCMP2P_Pos)

#define	TIM16_AF1_BKCMP2P TIM16_AF1_BKCMP2P_Msk

#define	TIM17_AF1_BKINE_Pos (0U)

#define	TIM17_AF1_BKINE_Msk (0x1UL << TIM17_AF1_BKINE_Pos)

#define	TIM17_AF1_BKINE TIM17_AF1_BKINE_Msk

#define	TIM17_AF1_BKCMP1E_Pos (1U)

#define	TIM17_AF1_BKCMP1E_Msk (0x1UL << TIM17_AF1_BKCMP1E_Pos)

#define	TIM17_AF1_BKCMP1E TIM17_AF1_BKCMP1E_Msk

#define	TIM17_AF1_BKCMP2E_Pos (2U)

#define	TIM17_AF1_BKCMP2E_Msk (0x1UL << TIM17_AF1_BKCMP2E_Pos)

#define	TIM17_AF1_BKCMP2E TIM17_AF1_BKCMP2E_Msk

#define	TIM17_AF1_BKINP_Pos (9U)

#define	TIM17_AF1_BKINP_Msk (0x1UL << TIM17_AF1_BKINP_Pos)

#define	TIM17_AF1_BKINP TIM17_AF1_BKINP_Msk

#define	TIM17_AF1_BKCMP1P_Pos (10U)

#define	TIM17_AF1_BKCMP1P_Msk (0x1UL << TIM17_AF1_BKCMP1P_Pos)

#define	TIM17_AF1_BKCMP1P TIM17_AF1_BKCMP1P_Msk

#define	TIM17_AF1_BKCMP2P_Pos (11U)

#define	TIM17_AF1_BKCMP2P_Msk (0x1UL << TIM17_AF1_BKCMP2P_Pos)

#define	TIM17_AF1_BKCMP2P TIM17_AF1_BKCMP2P_Msk

#define	TIM_TISEL_TI1SEL_Pos (0U)

#define	TIM_TISEL_TI1SEL_Msk (0xFUL << TIM_TISEL_TI1SEL_Pos)

#define	TIM_TISEL_TI1SEL TIM_TISEL_TI1SEL_Msk

#define	TIM_TISEL_TI1SEL_0 (0x1UL << TIM_TISEL_TI1SEL_Pos)

#define	TIM_TISEL_TI1SEL_1 (0x2UL << TIM_TISEL_TI1SEL_Pos)

#define	TIM_TISEL_TI1SEL_2 (0x4UL << TIM_TISEL_TI1SEL_Pos)

#define	TIM_TISEL_TI1SEL_3 (0x8UL << TIM_TISEL_TI1SEL_Pos)

#define	TIM_TISEL_TI2SEL_Pos (8U)

#define	TIM_TISEL_TI2SEL_Msk (0xFUL << TIM_TISEL_TI2SEL_Pos)

#define	TIM_TISEL_TI2SEL TIM_TISEL_TI2SEL_Msk

#define	TIM_TISEL_TI2SEL_0 (0x1UL << TIM_TISEL_TI2SEL_Pos)

#define	TIM_TISEL_TI2SEL_1 (0x2UL << TIM_TISEL_TI2SEL_Pos)

#define	TIM_TISEL_TI2SEL_2 (0x4UL << TIM_TISEL_TI2SEL_Pos)

#define	TIM_TISEL_TI2SEL_3 (0x8UL << TIM_TISEL_TI2SEL_Pos)

#define	TIM_TISEL_TI3SEL_Pos (16U)

#define	TIM_TISEL_TI3SEL_Msk (0xFUL << TIM_TISEL_TI3SEL_Pos)

#define	TIM_TISEL_TI3SEL TIM_TISEL_TI3SEL_Msk

#define	TIM_TISEL_TI3SEL_0 (0x1UL << TIM_TISEL_TI3SEL_Pos)

#define	TIM_TISEL_TI3SEL_1 (0x2UL << TIM_TISEL_TI3SEL_Pos)

#define	TIM_TISEL_TI3SEL_2 (0x4UL << TIM_TISEL_TI3SEL_Pos)

#define	TIM_TISEL_TI3SEL_3 (0x8UL << TIM_TISEL_TI3SEL_Pos)

#define	TIM_TISEL_TI4SEL_Pos (24U)

#define	TIM_TISEL_TI4SEL_Msk (0xFUL << TIM_TISEL_TI4SEL_Pos)

#define	TIM_TISEL_TI4SEL TIM_TISEL_TI4SEL_Msk

#define	TIM_TISEL_TI4SEL_0 (0x1UL << TIM_TISEL_TI4SEL_Pos)

#define	TIM_TISEL_TI4SEL_1 (0x2UL << TIM_TISEL_TI4SEL_Pos)

#define	TIM_TISEL_TI4SEL_2 (0x4UL << TIM_TISEL_TI4SEL_Pos)

#define	TIM_TISEL_TI4SEL_3 (0x8UL << TIM_TISEL_TI4SEL_Pos)

#define	USART_CR1_UE_Pos (0U)

#define	USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos)

#define	USART_CR1_UE USART_CR1_UE_Msk

#define	USART_CR1_UESM_Pos (1U)

#define	USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos)

#define	USART_CR1_UESM USART_CR1_UESM_Msk

#define	USART_CR1_RE_Pos (2U)

#define	USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos)

#define	USART_CR1_RE USART_CR1_RE_Msk

#define	USART_CR1_TE_Pos (3U)

#define	USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos)

#define	USART_CR1_TE USART_CR1_TE_Msk

#define	USART_CR1_IDLEIE_Pos (4U)

#define	USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos)

#define	USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk

#define	USART_CR1_RXNEIE_RXFNEIE_Pos (5U)

#define	USART_CR1_RXNEIE_RXFNEIE_Msk (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos)

#define	USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE_Msk

#define	USART_CR1_TCIE_Pos (6U)

#define	USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos)

#define	USART_CR1_TCIE USART_CR1_TCIE_Msk

#define	USART_CR1_TXEIE_TXFNFIE_Pos (7U)

#define	USART_CR1_TXEIE_TXFNFIE_Msk (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos)

#define	USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE_Msk

#define	USART_CR1_PEIE_Pos (8U)

#define	USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos)

#define	USART_CR1_PEIE USART_CR1_PEIE_Msk

#define	USART_CR1_PS_Pos (9U)

#define	USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos)

#define	USART_CR1_PS USART_CR1_PS_Msk

#define	USART_CR1_PCE_Pos (10U)

#define	USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos)

#define	USART_CR1_PCE USART_CR1_PCE_Msk

#define	USART_CR1_WAKE_Pos (11U)

#define	USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos)

#define	USART_CR1_WAKE USART_CR1_WAKE_Msk

#define	USART_CR1_M_Pos (12U)

#define	USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos)

#define	USART_CR1_M USART_CR1_M_Msk

#define	USART_CR1_M0_Pos (12U)

#define	USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos)

#define	USART_CR1_M0 USART_CR1_M0_Msk

#define	USART_CR1_MME_Pos (13U)

#define	USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos)

#define	USART_CR1_MME USART_CR1_MME_Msk

#define	USART_CR1_CMIE_Pos (14U)

#define	USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos)

#define	USART_CR1_CMIE USART_CR1_CMIE_Msk

#define	USART_CR1_OVER8_Pos (15U)

#define	USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos)

#define	USART_CR1_OVER8 USART_CR1_OVER8_Msk

#define	USART_CR1_DEDT_Pos (16U)

#define	USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos)

#define	USART_CR1_DEDT USART_CR1_DEDT_Msk

#define	USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos)

#define	USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos)

#define	USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos)

#define	USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos)

#define	USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos)

#define	USART_CR1_DEAT_Pos (21U)

#define	USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos)

#define	USART_CR1_DEAT USART_CR1_DEAT_Msk

#define	USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos)

#define	USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos)

#define	USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos)

#define	USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos)

#define	USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos)

#define	USART_CR1_RTOIE_Pos (26U)

#define	USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos)

#define	USART_CR1_RTOIE USART_CR1_RTOIE_Msk

#define	USART_CR1_EOBIE_Pos (27U)

#define	USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos)

#define	USART_CR1_EOBIE USART_CR1_EOBIE_Msk

#define	USART_CR1_M1_Pos (28U)

#define	USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos)

#define	USART_CR1_M1 USART_CR1_M1_Msk

#define	USART_CR1_FIFOEN_Pos (29U)

#define	USART_CR1_FIFOEN_Msk (0x1UL << USART_CR1_FIFOEN_Pos)

#define	USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk

#define	USART_CR1_TXFEIE_Pos (30U)

#define	USART_CR1_TXFEIE_Msk (0x1UL << USART_CR1_TXFEIE_Pos)

#define	USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk

#define	USART_CR1_RXFFIE_Pos (31U)

#define	USART_CR1_RXFFIE_Msk (0x1UL << USART_CR1_RXFFIE_Pos)

#define	USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk

#define	USART_CR2_SLVEN_Pos (0U)

#define	USART_CR2_SLVEN_Msk (0x1UL << USART_CR2_SLVEN_Pos)

#define	USART_CR2_SLVEN USART_CR2_SLVEN_Msk

#define	USART_CR2_DIS_NSS_Pos (3U)

#define	USART_CR2_DIS_NSS_Msk (0x1UL << USART_CR2_DIS_NSS_Pos)

#define	USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk

#define	USART_CR2_ADDM7_Pos (4U)

#define	USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos)

#define	USART_CR2_ADDM7 USART_CR2_ADDM7_Msk

#define	USART_CR2_LBDL_Pos (5U)

#define	USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos)

#define	USART_CR2_LBDL USART_CR2_LBDL_Msk

#define	USART_CR2_LBDIE_Pos (6U)

#define	USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos)

#define	USART_CR2_LBDIE USART_CR2_LBDIE_Msk

#define	USART_CR2_LBCL_Pos (8U)

#define	USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos)

#define	USART_CR2_LBCL USART_CR2_LBCL_Msk

#define	USART_CR2_CPHA_Pos (9U)

#define	USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos)

#define	USART_CR2_CPHA USART_CR2_CPHA_Msk

#define	USART_CR2_CPOL_Pos (10U)

#define	USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos)

#define	USART_CR2_CPOL USART_CR2_CPOL_Msk

#define	USART_CR2_CLKEN_Pos (11U)

#define	USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos)

#define	USART_CR2_CLKEN USART_CR2_CLKEN_Msk

#define	USART_CR2_STOP_Pos (12U)

#define	USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos)

#define	USART_CR2_STOP USART_CR2_STOP_Msk

#define	USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos)

#define	USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos)

#define	USART_CR2_LINEN_Pos (14U)

#define	USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos)

#define	USART_CR2_LINEN USART_CR2_LINEN_Msk

#define	USART_CR2_SWAP_Pos (15U)

#define	USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos)

#define	USART_CR2_SWAP USART_CR2_SWAP_Msk

#define	USART_CR2_RXINV_Pos (16U)

#define	USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos)

#define	USART_CR2_RXINV USART_CR2_RXINV_Msk

#define	USART_CR2_TXINV_Pos (17U)

#define	USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos)

#define	USART_CR2_TXINV USART_CR2_TXINV_Msk

#define	USART_CR2_DATAINV_Pos (18U)

#define	USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos)

#define	USART_CR2_DATAINV USART_CR2_DATAINV_Msk

#define	USART_CR2_MSBFIRST_Pos (19U)

#define	USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos)

#define	USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk

#define	USART_CR2_ABREN_Pos (20U)

#define	USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos)

#define	USART_CR2_ABREN USART_CR2_ABREN_Msk

#define	USART_CR2_ABRMODE_Pos (21U)

#define	USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos)

#define	USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk

#define	USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos)

#define	USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos)

#define	USART_CR2_RTOEN_Pos (23U)

#define	USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos)

#define	USART_CR2_RTOEN USART_CR2_RTOEN_Msk

#define	USART_CR2_ADD_Pos (24U)

#define	USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos)

#define	USART_CR2_ADD USART_CR2_ADD_Msk

#define	USART_CR3_EIE_Pos (0U)

#define	USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos)

#define	USART_CR3_EIE USART_CR3_EIE_Msk

#define	USART_CR3_IREN_Pos (1U)

#define	USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos)

#define	USART_CR3_IREN USART_CR3_IREN_Msk

#define	USART_CR3_IRLP_Pos (2U)

#define	USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos)

#define	USART_CR3_IRLP USART_CR3_IRLP_Msk

#define	USART_CR3_HDSEL_Pos (3U)

#define	USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos)

#define	USART_CR3_HDSEL USART_CR3_HDSEL_Msk

#define	USART_CR3_NACK_Pos (4U)

#define	USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos)

#define	USART_CR3_NACK USART_CR3_NACK_Msk

#define	USART_CR3_SCEN_Pos (5U)

#define	USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos)

#define	USART_CR3_SCEN USART_CR3_SCEN_Msk

#define	USART_CR3_DMAR_Pos (6U)

#define	USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos)

#define	USART_CR3_DMAR USART_CR3_DMAR_Msk

#define	USART_CR3_DMAT_Pos (7U)

#define	USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos)

#define	USART_CR3_DMAT USART_CR3_DMAT_Msk

#define	USART_CR3_RTSE_Pos (8U)

#define	USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos)

#define	USART_CR3_RTSE USART_CR3_RTSE_Msk

#define	USART_CR3_CTSE_Pos (9U)

#define	USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos)

#define	USART_CR3_CTSE USART_CR3_CTSE_Msk

#define	USART_CR3_CTSIE_Pos (10U)

#define	USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos)

#define	USART_CR3_CTSIE USART_CR3_CTSIE_Msk

#define	USART_CR3_ONEBIT_Pos (11U)

#define	USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos)

#define	USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk

#define	USART_CR3_OVRDIS_Pos (12U)

#define	USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos)

#define	USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk

#define	USART_CR3_DDRE_Pos (13U)

#define	USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos)

#define	USART_CR3_DDRE USART_CR3_DDRE_Msk

#define	USART_CR3_DEM_Pos (14U)

#define	USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos)

#define	USART_CR3_DEM USART_CR3_DEM_Msk

#define	USART_CR3_DEP_Pos (15U)

#define	USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos)

#define	USART_CR3_DEP USART_CR3_DEP_Msk

#define	USART_CR3_SCARCNT_Pos (17U)

#define	USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos)

#define	USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk

#define	USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos)

#define	USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos)

#define	USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos)

#define	USART_CR3_WUS_Pos (20U)

#define	USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos)

#define	USART_CR3_WUS USART_CR3_WUS_Msk

#define	USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos)

#define	USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos)

#define	USART_CR3_WUFIE_Pos (22U)

#define	USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos)

#define	USART_CR3_WUFIE USART_CR3_WUFIE_Msk

#define	USART_CR3_TXFTIE_Pos (23U)

#define	USART_CR3_TXFTIE_Msk (0x1UL << USART_CR3_TXFTIE_Pos)

#define	USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk

#define	USART_CR3_TCBGTIE_Pos (24U)

#define	USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos)

#define	USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk

#define	USART_CR3_RXFTCFG_Pos (25U)

#define	USART_CR3_RXFTCFG_Msk (0x7UL << USART_CR3_RXFTCFG_Pos)

#define	USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk

#define	USART_CR3_RXFTCFG_0 (0x1UL << USART_CR3_RXFTCFG_Pos)

#define	USART_CR3_RXFTCFG_1 (0x2UL << USART_CR3_RXFTCFG_Pos)

#define	USART_CR3_RXFTCFG_2 (0x4UL << USART_CR3_RXFTCFG_Pos)

#define	USART_CR3_RXFTIE_Pos (28U)

#define	USART_CR3_RXFTIE_Msk (0x1UL << USART_CR3_RXFTIE_Pos)

#define	USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk

#define	USART_CR3_TXFTCFG_Pos (29U)

#define	USART_CR3_TXFTCFG_Msk (0x7UL << USART_CR3_TXFTCFG_Pos)

#define	USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk

#define	USART_CR3_TXFTCFG_0 (0x1UL << USART_CR3_TXFTCFG_Pos)

#define	USART_CR3_TXFTCFG_1 (0x2UL << USART_CR3_TXFTCFG_Pos)

#define	USART_CR3_TXFTCFG_2 (0x4UL << USART_CR3_TXFTCFG_Pos)

#define	USART_BRR_BRR ((uint16_t)0xFFFF)

#define	USART_GTPR_PSC_Pos (0U)

#define	USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos)

#define	USART_GTPR_PSC USART_GTPR_PSC_Msk

#define	USART_GTPR_GT_Pos (8U)

#define	USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos)

#define	USART_GTPR_GT USART_GTPR_GT_Msk

#define	USART_RTOR_RTO_Pos (0U)

#define	USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos)

#define	USART_RTOR_RTO USART_RTOR_RTO_Msk

#define	USART_RTOR_BLEN_Pos (24U)

#define	USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos)

#define	USART_RTOR_BLEN USART_RTOR_BLEN_Msk

#define	USART_RQR_ABRRQ ((uint16_t)0x0001)

#define	USART_RQR_SBKRQ ((uint16_t)0x0002)

#define	USART_RQR_MMRQ ((uint16_t)0x0004)

#define	USART_RQR_RXFRQ ((uint16_t)0x0008)

#define	USART_RQR_TXFRQ ((uint16_t)0x0010)

#define	USART_ISR_PE_Pos (0U)

#define	USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos)

#define	USART_ISR_PE USART_ISR_PE_Msk

#define	USART_ISR_FE_Pos (1U)

#define	USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos)

#define	USART_ISR_FE USART_ISR_FE_Msk

#define	USART_ISR_NE_Pos (2U)

#define	USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos)

#define	USART_ISR_NE USART_ISR_NE_Msk

#define	USART_ISR_ORE_Pos (3U)

#define	USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos)

#define	USART_ISR_ORE USART_ISR_ORE_Msk

#define	USART_ISR_IDLE_Pos (4U)

#define	USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos)

#define	USART_ISR_IDLE USART_ISR_IDLE_Msk

#define	USART_ISR_RXNE_RXFNE_Pos (5U)

#define	USART_ISR_RXNE_RXFNE_Msk (0x1UL << USART_ISR_RXNE_RXFNE_Pos)

#define	USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE_Msk

#define	USART_ISR_TC_Pos (6U)

#define	USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos)

#define	USART_ISR_TC USART_ISR_TC_Msk

#define	USART_ISR_TXE_TXFNF_Pos (7U)

#define	USART_ISR_TXE_TXFNF_Msk (0x1UL << USART_ISR_TXE_TXFNF_Pos)

#define	USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF_Msk

#define	USART_ISR_LBDF_Pos (8U)

#define	USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos)

#define	USART_ISR_LBDF USART_ISR_LBDF_Msk

#define	USART_ISR_CTSIF_Pos (9U)

#define	USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos)

#define	USART_ISR_CTSIF USART_ISR_CTSIF_Msk

#define	USART_ISR_CTS_Pos (10U)

#define	USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos)

#define	USART_ISR_CTS USART_ISR_CTS_Msk

#define	USART_ISR_RTOF_Pos (11U)

#define	USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos)

#define	USART_ISR_RTOF USART_ISR_RTOF_Msk

#define	USART_ISR_EOBF_Pos (12U)

#define	USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos)

#define	USART_ISR_EOBF USART_ISR_EOBF_Msk

#define	USART_ISR_UDR_Pos (13U)

#define	USART_ISR_UDR_Msk (0x1UL << USART_ISR_UDR_Pos)

#define	USART_ISR_UDR USART_ISR_UDR_Msk

#define	USART_ISR_ABRE_Pos (14U)

#define	USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos)

#define	USART_ISR_ABRE USART_ISR_ABRE_Msk

#define	USART_ISR_ABRF_Pos (15U)

#define	USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos)

#define	USART_ISR_ABRF USART_ISR_ABRF_Msk

#define	USART_ISR_BUSY_Pos (16U)

#define	USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos)

#define	USART_ISR_BUSY USART_ISR_BUSY_Msk

#define	USART_ISR_CMF_Pos (17U)

#define	USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos)

#define	USART_ISR_CMF USART_ISR_CMF_Msk

#define	USART_ISR_SBKF_Pos (18U)

#define	USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos)

#define	USART_ISR_SBKF USART_ISR_SBKF_Msk

#define	USART_ISR_RWU_Pos (19U)

#define	USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos)

#define	USART_ISR_RWU USART_ISR_RWU_Msk

#define	USART_ISR_WUF_Pos (20U)

#define	USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos)

#define	USART_ISR_WUF USART_ISR_WUF_Msk

#define	USART_ISR_TEACK_Pos (21U)

#define	USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos)

#define	USART_ISR_TEACK USART_ISR_TEACK_Msk

#define	USART_ISR_REACK_Pos (22U)

#define	USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos)

#define	USART_ISR_REACK USART_ISR_REACK_Msk

#define	USART_ISR_TXFE_Pos (23U)

#define	USART_ISR_TXFE_Msk (0x1UL << USART_ISR_TXFE_Pos)

#define	USART_ISR_TXFE USART_ISR_TXFE_Msk

#define	USART_ISR_RXFF_Pos (24U)

#define	USART_ISR_RXFF_Msk (0x1UL << USART_ISR_RXFF_Pos)

#define	USART_ISR_RXFF USART_ISR_RXFF_Msk

#define	USART_ISR_TCBGT_Pos (25U)

#define	USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos)

#define	USART_ISR_TCBGT USART_ISR_TCBGT_Msk

#define	USART_ISR_RXFT_Pos (26U)

#define	USART_ISR_RXFT_Msk (0x1UL << USART_ISR_RXFT_Pos)

#define	USART_ISR_RXFT USART_ISR_RXFT_Msk

#define	USART_ISR_TXFT_Pos (27U)

#define	USART_ISR_TXFT_Msk (0x1UL << USART_ISR_TXFT_Pos)

#define	USART_ISR_TXFT USART_ISR_TXFT_Msk

#define	USART_ICR_PECF_Pos (0U)

#define	USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos)

#define	USART_ICR_PECF USART_ICR_PECF_Msk

#define	USART_ICR_FECF_Pos (1U)

#define	USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos)

#define	USART_ICR_FECF USART_ICR_FECF_Msk

#define	USART_ICR_NECF_Pos (2U)

#define	USART_ICR_NECF_Msk (0x1UL << USART_ICR_NECF_Pos)

#define	USART_ICR_NECF USART_ICR_NECF_Msk

#define	USART_ICR_ORECF_Pos (3U)

#define	USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos)

#define	USART_ICR_ORECF USART_ICR_ORECF_Msk

#define	USART_ICR_IDLECF_Pos (4U)

#define	USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos)

#define	USART_ICR_IDLECF USART_ICR_IDLECF_Msk

#define	USART_ICR_TXFECF_Pos (5U)

#define	USART_ICR_TXFECF_Msk (0x1UL << USART_ICR_TXFECF_Pos)

#define	USART_ICR_TXFECF USART_ICR_TXFECF_Msk

#define	USART_ICR_TCCF_Pos (6U)

#define	USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos)

#define	USART_ICR_TCCF USART_ICR_TCCF_Msk

#define	USART_ICR_TCBGTCF_Pos (7U)

#define	USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos)

#define	USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk

#define	USART_ICR_LBDCF_Pos (8U)

#define	USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos)

#define	USART_ICR_LBDCF USART_ICR_LBDCF_Msk

#define	USART_ICR_CTSCF_Pos (9U)

#define	USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos)

#define	USART_ICR_CTSCF USART_ICR_CTSCF_Msk

#define	USART_ICR_RTOCF_Pos (11U)

#define	USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos)

#define	USART_ICR_RTOCF USART_ICR_RTOCF_Msk

#define	USART_ICR_EOBCF_Pos (12U)

#define	USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos)

#define	USART_ICR_EOBCF USART_ICR_EOBCF_Msk

#define	USART_ICR_UDRCF_Pos (13U)

#define	USART_ICR_UDRCF_Msk (0x1UL << USART_ICR_UDRCF_Pos)

#define	USART_ICR_UDRCF USART_ICR_UDRCF_Msk

#define	USART_ICR_CMCF_Pos (17U)

#define	USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos)

#define	USART_ICR_CMCF USART_ICR_CMCF_Msk

#define	USART_ICR_WUCF_Pos (20U)

#define	USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos)

#define	USART_ICR_WUCF USART_ICR_WUCF_Msk

#define	USART_RDR_RDR_Pos (0U)

#define	USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos)

#define	USART_RDR_RDR USART_RDR_RDR_Msk

#define	USART_TDR_TDR_Pos (0U)

#define	USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos)

#define	USART_TDR_TDR USART_TDR_TDR_Msk

#define	USART_PRESC_PRESCALER_Pos (0U)

#define	USART_PRESC_PRESCALER_Msk (0xFUL << USART_PRESC_PRESCALER_Pos)

#define	USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk

#define	USART_PRESC_PRESCALER_0 (0x1UL << USART_PRESC_PRESCALER_Pos)

#define	USART_PRESC_PRESCALER_1 (0x2UL << USART_PRESC_PRESCALER_Pos)

#define	USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos)

#define	USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos)

#define	WWDG_CR_T_Pos (0U)

#define	WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos)

#define	WWDG_CR_T WWDG_CR_T_Msk

#define	WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos)

#define	WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos)

#define	WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos)

#define	WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos)

#define	WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos)

#define	WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos)

#define	WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos)

#define	WWDG_CR_WDGA_Pos (7U)

#define	WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos)

#define	WWDG_CR_WDGA WWDG_CR_WDGA_Msk

#define	WWDG_CFR_W_Pos (0U)

#define	WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos)

#define	WWDG_CFR_W WWDG_CFR_W_Msk

#define	WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos)

#define	WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos)

#define	WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos)

#define	WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos)

#define	WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos)

#define	WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos)

#define	WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos)

#define	WWDG_CFR_WDGTB_Pos (11U)

#define	WWDG_CFR_WDGTB_Msk (0x7UL << WWDG_CFR_WDGTB_Pos)

#define	WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk

#define	WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos)

#define	WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos)

#define	WWDG_CFR_WDGTB_2 (0x4UL << WWDG_CFR_WDGTB_Pos)

#define	WWDG_CFR_EWI_Pos (9U)

#define	WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos)

#define	WWDG_CFR_EWI WWDG_CFR_EWI_Msk

#define	WWDG_SR_EWIF_Pos (0U)

#define	WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos)

#define	WWDG_SR_EWIF WWDG_SR_EWIF_Msk

#define	DBG_IDCODE_DEV_ID_Pos (0U)

#define	DBG_IDCODE_DEV_ID_Msk (0xFFFUL << DBG_IDCODE_DEV_ID_Pos)

#define	DBG_IDCODE_DEV_ID DBG_IDCODE_DEV_ID_Msk

#define	DBG_IDCODE_REV_ID_Pos (16U)

#define	DBG_IDCODE_REV_ID_Msk (0xFFFFUL << DBG_IDCODE_REV_ID_Pos)

#define	DBG_IDCODE_REV_ID DBG_IDCODE_REV_ID_Msk

#define	DBG_CR_DBG_STOP_Pos (1U)

#define	DBG_CR_DBG_STOP_Msk (0x1UL << DBG_CR_DBG_STOP_Pos)

#define	DBG_CR_DBG_STOP DBG_CR_DBG_STOP_Msk

#define	DBG_CR_DBG_STANDBY_Pos (2U)

#define	DBG_CR_DBG_STANDBY_Msk (0x1UL << DBG_CR_DBG_STANDBY_Pos)

#define	DBG_CR_DBG_STANDBY DBG_CR_DBG_STANDBY_Msk

#define	DBG_APB_FZ1_DBG_TIM3_STOP_Pos (1U)

#define	DBG_APB_FZ1_DBG_TIM3_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_TIM3_STOP_Pos)

#define	DBG_APB_FZ1_DBG_TIM3_STOP DBG_APB_FZ1_DBG_TIM3_STOP_Msk

#define	DBG_APB_FZ1_DBG_RTC_STOP_Pos (10U)

#define	DBG_APB_FZ1_DBG_RTC_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_RTC_STOP_Pos)

#define	DBG_APB_FZ1_DBG_RTC_STOP DBG_APB_FZ1_DBG_RTC_STOP_Msk

#define	DBG_APB_FZ1_DBG_WWDG_STOP_Pos (11U)

#define	DBG_APB_FZ1_DBG_WWDG_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_WWDG_STOP_Pos)

#define	DBG_APB_FZ1_DBG_WWDG_STOP DBG_APB_FZ1_DBG_WWDG_STOP_Msk

#define	DBG_APB_FZ1_DBG_IWDG_STOP_Pos (12U)

#define	DBG_APB_FZ1_DBG_IWDG_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_IWDG_STOP_Pos)

#define	DBG_APB_FZ1_DBG_IWDG_STOP DBG_APB_FZ1_DBG_IWDG_STOP_Msk

#define	DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Pos (21U)

#define	DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Pos)

#define	DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Msk

#define	DBG_APB_FZ2_DBG_TIM1_STOP_Pos (11U)

#define	DBG_APB_FZ2_DBG_TIM1_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM1_STOP_Pos)

#define	DBG_APB_FZ2_DBG_TIM1_STOP DBG_APB_FZ2_DBG_TIM1_STOP_Msk

#define	DBG_APB_FZ2_DBG_TIM14_STOP_Pos (15U)

#define	DBG_APB_FZ2_DBG_TIM14_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM14_STOP_Pos)

#define	DBG_APB_FZ2_DBG_TIM14_STOP DBG_APB_FZ2_DBG_TIM14_STOP_Msk

#define	DBG_APB_FZ2_DBG_TIM16_STOP_Pos (17U)

#define	DBG_APB_FZ2_DBG_TIM16_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM16_STOP_Pos)

#define	DBG_APB_FZ2_DBG_TIM16_STOP DBG_APB_FZ2_DBG_TIM16_STOP_Msk

#define	DBG_APB_FZ2_DBG_TIM17_STOP_Pos (18U)

#define	DBG_APB_FZ2_DBG_TIM17_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM17_STOP_Pos)

#define	DBG_APB_FZ2_DBG_TIM17_STOP DBG_APB_FZ2_DBG_TIM17_STOP_Msk

Detailed Description

Macro Definition Documentation

◆ ADC_AWD1TR_HT1

#define ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk

ADC Analog watchdog 1 threshold high

◆ ADC_AWD1TR_HT1_0

#define ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos)

0x00010000

◆ ADC_AWD1TR_HT1_1

#define ADC_AWD1TR_HT1_1 (0x002UL << ADC_AWD1TR_HT1_Pos)

0x00020000

◆ ADC_AWD1TR_HT1_10

#define ADC_AWD1TR_HT1_10 (0x400UL << ADC_AWD1TR_HT1_Pos)

0x04000000

◆ ADC_AWD1TR_HT1_11

#define ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos)

0x08000000

◆ ADC_AWD1TR_HT1_2

#define ADC_AWD1TR_HT1_2 (0x004UL << ADC_AWD1TR_HT1_Pos)

0x00040000

◆ ADC_AWD1TR_HT1_3

#define ADC_AWD1TR_HT1_3 (0x008UL << ADC_AWD1TR_HT1_Pos)

0x00080000

◆ ADC_AWD1TR_HT1_4

#define ADC_AWD1TR_HT1_4 (0x010UL << ADC_AWD1TR_HT1_Pos)

0x00100000

◆ ADC_AWD1TR_HT1_5

#define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos)

0x00200000

◆ ADC_AWD1TR_HT1_6

#define ADC_AWD1TR_HT1_6 (0x040UL << ADC_AWD1TR_HT1_Pos)

0x00400000

◆ ADC_AWD1TR_HT1_7

#define ADC_AWD1TR_HT1_7 (0x080UL << ADC_AWD1TR_HT1_Pos)

0x00800000

◆ ADC_AWD1TR_HT1_8

#define ADC_AWD1TR_HT1_8 (0x100UL << ADC_AWD1TR_HT1_Pos)

0x01000000

◆ ADC_AWD1TR_HT1_9

#define ADC_AWD1TR_HT1_9 (0x200UL << ADC_AWD1TR_HT1_Pos)

0x02000000

◆ ADC_AWD1TR_HT1_Msk

#define ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos)

0x0FFF0000

◆ ADC_AWD1TR_HT1_Pos

#define ADC_AWD1TR_HT1_Pos (16U)

◆ ADC_AWD1TR_LT1

#define ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk

ADC analog watchdog 1 threshold low

◆ ADC_AWD1TR_LT1_0

#define ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos)

0x00000001

◆ ADC_AWD1TR_LT1_1

#define ADC_AWD1TR_LT1_1 (0x002UL << ADC_AWD1TR_LT1_Pos)

0x00000002

◆ ADC_AWD1TR_LT1_10

#define ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos)

0x00000400

◆ ADC_AWD1TR_LT1_11

#define ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos)

0x00000800

◆ ADC_AWD1TR_LT1_2

#define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos)

0x00000004

◆ ADC_AWD1TR_LT1_3

#define ADC_AWD1TR_LT1_3 (0x008UL << ADC_AWD1TR_LT1_Pos)

0x00000008

◆ ADC_AWD1TR_LT1_4

#define ADC_AWD1TR_LT1_4 (0x010UL << ADC_AWD1TR_LT1_Pos)

0x00000010

◆ ADC_AWD1TR_LT1_5

#define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos)

0x00000020

◆ ADC_AWD1TR_LT1_6

#define ADC_AWD1TR_LT1_6 (0x040UL << ADC_AWD1TR_LT1_Pos)

0x00000040

◆ ADC_AWD1TR_LT1_7

#define ADC_AWD1TR_LT1_7 (0x080UL << ADC_AWD1TR_LT1_Pos)

0x00000080

◆ ADC_AWD1TR_LT1_8

#define ADC_AWD1TR_LT1_8 (0x100UL << ADC_AWD1TR_LT1_Pos)

0x00000100

◆ ADC_AWD1TR_LT1_9

#define ADC_AWD1TR_LT1_9 (0x200UL << ADC_AWD1TR_LT1_Pos)

0x00000200

◆ ADC_AWD1TR_LT1_Msk

#define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos)

0x00000FFF

◆ ADC_AWD1TR_LT1_Pos

#define ADC_AWD1TR_LT1_Pos (0U)

◆ ADC_AWD2CR_AWD2CH

#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk

ADC analog watchdog 2 monitored channel selection

◆ ADC_AWD2CR_AWD2CH_0

#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)

0x00000001

◆ ADC_AWD2CR_AWD2CH_1

#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)

0x00000002

◆ ADC_AWD2CR_AWD2CH_10

#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)

0x00000400

◆ ADC_AWD2CR_AWD2CH_11

#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)

0x00000800

◆ ADC_AWD2CR_AWD2CH_12

#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)

0x00001000

◆ ADC_AWD2CR_AWD2CH_13

#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)

0x00002000

◆ ADC_AWD2CR_AWD2CH_14

#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)

0x00004000

◆ ADC_AWD2CR_AWD2CH_15

#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)

0x00008000

◆ ADC_AWD2CR_AWD2CH_16

#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)

0x00010000

◆ ADC_AWD2CR_AWD2CH_17

#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)

0x00020000

◆ ADC_AWD2CR_AWD2CH_18

#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)

0x00040000

◆ ADC_AWD2CR_AWD2CH_2

#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)

0x00000004

◆ ADC_AWD2CR_AWD2CH_3

#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)

0x00000008

◆ ADC_AWD2CR_AWD2CH_4

#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)

0x00000010

◆ ADC_AWD2CR_AWD2CH_5

#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)

0x00000020

◆ ADC_AWD2CR_AWD2CH_6

#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)

0x00000040

◆ ADC_AWD2CR_AWD2CH_7

#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)

0x00000080

◆ ADC_AWD2CR_AWD2CH_8

#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)

0x00000100

◆ ADC_AWD2CR_AWD2CH_9

#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)

0x00000200

◆ ADC_AWD2CR_AWD2CH_Msk

#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos)

0x0007FFFF

◆ ADC_AWD2CR_AWD2CH_Pos

#define ADC_AWD2CR_AWD2CH_Pos (0U)

◆ ADC_AWD2TR_HT2

#define ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk

ADC analog watchdog 2 threshold high

◆ ADC_AWD2TR_HT2_0

#define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos)

0x00010000

◆ ADC_AWD2TR_HT2_1

#define ADC_AWD2TR_HT2_1 (0x002UL << ADC_AWD2TR_HT2_Pos)

0x00020000

◆ ADC_AWD2TR_HT2_10

#define ADC_AWD2TR_HT2_10 (0x400UL << ADC_AWD2TR_HT2_Pos)

0x04000000

◆ ADC_AWD2TR_HT2_11

#define ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos)

0x08000000

◆ ADC_AWD2TR_HT2_2

#define ADC_AWD2TR_HT2_2 (0x004UL << ADC_AWD2TR_HT2_Pos)

0x00040000

◆ ADC_AWD2TR_HT2_3

#define ADC_AWD2TR_HT2_3 (0x008UL << ADC_AWD2TR_HT2_Pos)

0x00080000

◆ ADC_AWD2TR_HT2_4

#define ADC_AWD2TR_HT2_4 (0x010UL << ADC_AWD2TR_HT2_Pos)

0x00100000

◆ ADC_AWD2TR_HT2_5

#define ADC_AWD2TR_HT2_5 (0x020UL << ADC_AWD2TR_HT2_Pos)

0x00200000

◆ ADC_AWD2TR_HT2_6

#define ADC_AWD2TR_HT2_6 (0x040UL << ADC_AWD2TR_HT2_Pos)

0x00400000

◆ ADC_AWD2TR_HT2_7

#define ADC_AWD2TR_HT2_7 (0x080UL << ADC_AWD2TR_HT2_Pos)

0x00800000

◆ ADC_AWD2TR_HT2_8

#define ADC_AWD2TR_HT2_8 (0x100UL << ADC_AWD2TR_HT2_Pos)

0x01000000

◆ ADC_AWD2TR_HT2_9

#define ADC_AWD2TR_HT2_9 (0x200UL << ADC_AWD2TR_HT2_Pos)

0x02000000

◆ ADC_AWD2TR_HT2_Msk

#define ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos)

0x0FFF0000

◆ ADC_AWD2TR_HT2_Pos

#define ADC_AWD2TR_HT2_Pos (16U)

◆ ADC_AWD2TR_LT2

#define ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk

ADC analog watchdog 2 threshold low

◆ ADC_AWD2TR_LT2_0

#define ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos)

0x00000001

◆ ADC_AWD2TR_LT2_1

#define ADC_AWD2TR_LT2_1 (0x002UL << ADC_AWD2TR_LT2_Pos)

0x00000002

◆ ADC_AWD2TR_LT2_10

#define ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos)

0x00000400

◆ ADC_AWD2TR_LT2_11

#define ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos)

0x00000800

◆ ADC_AWD2TR_LT2_2

#define ADC_AWD2TR_LT2_2 (0x004UL << ADC_AWD2TR_LT2_Pos)

0x00000004

◆ ADC_AWD2TR_LT2_3

#define ADC_AWD2TR_LT2_3 (0x008UL << ADC_AWD2TR_LT2_Pos)

0x00000008

◆ ADC_AWD2TR_LT2_4

#define ADC_AWD2TR_LT2_4 (0x010UL << ADC_AWD2TR_LT2_Pos)

0x00000010

◆ ADC_AWD2TR_LT2_5

#define ADC_AWD2TR_LT2_5 (0x020UL << ADC_AWD2TR_LT2_Pos)

0x00000020

◆ ADC_AWD2TR_LT2_6

#define ADC_AWD2TR_LT2_6 (0x040UL << ADC_AWD2TR_LT2_Pos)

0x00000040

◆ ADC_AWD2TR_LT2_7

#define ADC_AWD2TR_LT2_7 (0x080UL << ADC_AWD2TR_LT2_Pos)

0x00000080

◆ ADC_AWD2TR_LT2_8

#define ADC_AWD2TR_LT2_8 (0x100UL << ADC_AWD2TR_LT2_Pos)

0x00000100

◆ ADC_AWD2TR_LT2_9

#define ADC_AWD2TR_LT2_9 (0x200UL << ADC_AWD2TR_LT2_Pos)

0x00000200

◆ ADC_AWD2TR_LT2_Msk

#define ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos)

0x00000FFF

◆ ADC_AWD2TR_LT2_Pos

#define ADC_AWD2TR_LT2_Pos (0U)

◆ ADC_AWD3CR_AWD3CH

#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk

ADC analog watchdog 3 monitored channel selection

◆ ADC_AWD3CR_AWD3CH_0

#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)

0x00000001

◆ ADC_AWD3CR_AWD3CH_1

#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)

0x00000002

◆ ADC_AWD3CR_AWD3CH_10

#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)

0x00000400

◆ ADC_AWD3CR_AWD3CH_11

#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)

0x00000800

◆ ADC_AWD3CR_AWD3CH_12

#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)

0x00001000

◆ ADC_AWD3CR_AWD3CH_13

#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)

0x00002000

◆ ADC_AWD3CR_AWD3CH_14

#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)

0x00004000

◆ ADC_AWD3CR_AWD3CH_15

#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)

0x00008000

◆ ADC_AWD3CR_AWD3CH_16

#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)

0x00010000

◆ ADC_AWD3CR_AWD3CH_17

#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)

0x00020000

◆ ADC_AWD3CR_AWD3CH_18

#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)

0x00040000

◆ ADC_AWD3CR_AWD3CH_2

#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)

0x00000004

◆ ADC_AWD3CR_AWD3CH_3

#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)

0x00000008

◆ ADC_AWD3CR_AWD3CH_4

#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)

0x00000010

◆ ADC_AWD3CR_AWD3CH_5

#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)

0x00000020

◆ ADC_AWD3CR_AWD3CH_6

#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)

0x00000040

◆ ADC_AWD3CR_AWD3CH_7

#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)

0x00000080

◆ ADC_AWD3CR_AWD3CH_8

#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)

0x00000100

◆ ADC_AWD3CR_AWD3CH_9

#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)

0x00000200

◆ ADC_AWD3CR_AWD3CH_Msk

#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos)

0x0007FFFF

◆ ADC_AWD3CR_AWD3CH_Pos

#define ADC_AWD3CR_AWD3CH_Pos (0U)

◆ ADC_AWD3TR_HT3

#define ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk

ADC analog watchdog 3 threshold high

◆ ADC_AWD3TR_HT3_0

#define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos)

0x00010000

◆ ADC_AWD3TR_HT3_1

#define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos)

0x00020000

◆ ADC_AWD3TR_HT3_10

#define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos)

0x04000000

◆ ADC_AWD3TR_HT3_11

#define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos)

0x08000000

◆ ADC_AWD3TR_HT3_2

#define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos)

0x00040000

◆ ADC_AWD3TR_HT3_3

#define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos)

0x00080000

◆ ADC_AWD3TR_HT3_4

#define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos)

0x00100000

◆ ADC_AWD3TR_HT3_5

#define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos)

0x00200000

◆ ADC_AWD3TR_HT3_6

#define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos)

0x00400000

◆ ADC_AWD3TR_HT3_7

#define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos)

0x00800000

◆ ADC_AWD3TR_HT3_8

#define ADC_AWD3TR_HT3_8 (0x100UL << ADC_AWD3TR_HT3_Pos)

0x01000000

◆ ADC_AWD3TR_HT3_9

#define ADC_AWD3TR_HT3_9 (0x200UL << ADC_AWD3TR_HT3_Pos)

0x02000000

◆ ADC_AWD3TR_HT3_Msk

#define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos)

0x0FFF0000

◆ ADC_AWD3TR_HT3_Pos

#define ADC_AWD3TR_HT3_Pos (16U)

◆ ADC_AWD3TR_LT3

#define ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk

ADC analog watchdog 3 threshold low

◆ ADC_AWD3TR_LT3_0

#define ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos)

0x00000001

◆ ADC_AWD3TR_LT3_1

#define ADC_AWD3TR_LT3_1 (0x002UL << ADC_AWD3TR_LT3_Pos)

0x00000002

◆ ADC_AWD3TR_LT3_10

#define ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos)

0x00000400

◆ ADC_AWD3TR_LT3_11

#define ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos)

0x00000800

◆ ADC_AWD3TR_LT3_2

#define ADC_AWD3TR_LT3_2 (0x004UL << ADC_AWD3TR_LT3_Pos)

0x00000004

◆ ADC_AWD3TR_LT3_3

#define ADC_AWD3TR_LT3_3 (0x008UL << ADC_AWD3TR_LT3_Pos)

0x00000008

◆ ADC_AWD3TR_LT3_4

#define ADC_AWD3TR_LT3_4 (0x010UL << ADC_AWD3TR_LT3_Pos)

0x00000010

◆ ADC_AWD3TR_LT3_5

#define ADC_AWD3TR_LT3_5 (0x020UL << ADC_AWD3TR_LT3_Pos)

0x00000020

◆ ADC_AWD3TR_LT3_6

#define ADC_AWD3TR_LT3_6 (0x040UL << ADC_AWD3TR_LT3_Pos)

0x00000040

◆ ADC_AWD3TR_LT3_7

#define ADC_AWD3TR_LT3_7 (0x080UL << ADC_AWD3TR_LT3_Pos)

0x00000080

◆ ADC_AWD3TR_LT3_8

#define ADC_AWD3TR_LT3_8 (0x100UL << ADC_AWD3TR_LT3_Pos)

0x00000100

◆ ADC_AWD3TR_LT3_9

#define ADC_AWD3TR_LT3_9 (0x200UL << ADC_AWD3TR_LT3_Pos)

0x00000200

◆ ADC_AWD3TR_LT3_Msk

#define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos)

0x00000FFF

◆ ADC_AWD3TR_LT3_Pos

#define ADC_AWD3TR_LT3_Pos (0U)

◆ ADC_CALFACT_CALFACT

#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk

ADC calibration factor in single-ended mode

◆ ADC_CALFACT_CALFACT_0

#define ADC_CALFACT_CALFACT_0 (0x01UL << ADC_CALFACT_CALFACT_Pos)

0x00000001

◆ ADC_CALFACT_CALFACT_1

#define ADC_CALFACT_CALFACT_1 (0x02UL << ADC_CALFACT_CALFACT_Pos)

0x00000002

◆ ADC_CALFACT_CALFACT_2

#define ADC_CALFACT_CALFACT_2 (0x04UL << ADC_CALFACT_CALFACT_Pos)

0x00000004

◆ ADC_CALFACT_CALFACT_3

#define ADC_CALFACT_CALFACT_3 (0x08UL << ADC_CALFACT_CALFACT_Pos)

0x00000008

◆ ADC_CALFACT_CALFACT_4

#define ADC_CALFACT_CALFACT_4 (0x10UL << ADC_CALFACT_CALFACT_Pos)

0x00000010

◆ ADC_CALFACT_CALFACT_5

#define ADC_CALFACT_CALFACT_5 (0x20UL << ADC_CALFACT_CALFACT_Pos)

0x00000020

◆ ADC_CALFACT_CALFACT_6

#define ADC_CALFACT_CALFACT_6 (0x40UL << ADC_CALFACT_CALFACT_Pos)

0x00000040

◆ ADC_CALFACT_CALFACT_Msk

#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos)

0x0000007F

◆ ADC_CALFACT_CALFACT_Pos

#define ADC_CALFACT_CALFACT_Pos (0U)

◆ ADC_CCR_LFMEN

#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk

Legacy feature, useless on STM32G0 (ADC common clock low frequency mode is automatically managed by ADC peripheral on STM32G0)

◆ ADC_CCR_LFMEN_Msk

#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos)

0x02000000

◆ ADC_CCR_LFMEN_Pos

#define ADC_CCR_LFMEN_Pos (25U)

◆ ADC_CCR_PRESC

#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk

ADC common clock prescaler, only for clock source asynchronous

◆ ADC_CCR_PRESC_0

#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos)

0x00040000

◆ ADC_CCR_PRESC_1

#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos)

0x00080000

◆ ADC_CCR_PRESC_2

#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos)

0x00100000

◆ ADC_CCR_PRESC_3

#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos)

0x00200000

◆ ADC_CCR_PRESC_Msk

#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos)

0x003C0000

◆ ADC_CCR_PRESC_Pos

#define ADC_CCR_PRESC_Pos (18U)

◆ ADC_CCR_TSEN

#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk

ADC internal path to temperature sensor enable

◆ ADC_CCR_TSEN_Msk

#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos)

0x00800000

◆ ADC_CCR_TSEN_Pos

#define ADC_CCR_TSEN_Pos (23U)

◆ ADC_CCR_VBATEN

#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk

ADC internal path to battery voltage enable

◆ ADC_CCR_VBATEN_Msk

#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos)

0x01000000

◆ ADC_CCR_VBATEN_Pos

#define ADC_CCR_VBATEN_Pos (24U)

◆ ADC_CCR_VREFEN

#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk

ADC internal path to VrefInt enable

◆ ADC_CCR_VREFEN_Msk

#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos)

0x00400000

◆ ADC_CCR_VREFEN_Pos

#define ADC_CCR_VREFEN_Pos (22U)

◆ ADC_CFGR1_ALIGN

#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk

ADC data alignment

◆ ADC_CFGR1_ALIGN_Msk

#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos)

0x00000020

◆ ADC_CFGR1_ALIGN_Pos

#define ADC_CFGR1_ALIGN_Pos (5U)

◆ ADC_CFGR1_AUTDLY

#define ADC_CFGR1_AUTDLY (ADC_CFGR1_WAIT)

◆ ADC_CFGR1_AUTOFF

#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk

ADC low power auto power off

◆ ADC_CFGR1_AUTOFF_Msk

#define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos)

0x00008000

◆ ADC_CFGR1_AUTOFF_Pos

#define ADC_CFGR1_AUTOFF_Pos (15U)

◆ ADC_CFGR1_AWD1CH

#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk

ADC analog watchdog 1 monitored channel selection

◆ ADC_CFGR1_AWD1CH_0

#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos)

0x04000000

◆ ADC_CFGR1_AWD1CH_1

#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos)

0x08000000

◆ ADC_CFGR1_AWD1CH_2

#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos)

0x10000000

◆ ADC_CFGR1_AWD1CH_3

#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos)

0x20000000

◆ ADC_CFGR1_AWD1CH_4

#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos)

0x40000000

◆ ADC_CFGR1_AWD1CH_Msk

#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos)

0x7C000000

◆ ADC_CFGR1_AWD1CH_Pos

#define ADC_CFGR1_AWD1CH_Pos (26U)

◆ ADC_CFGR1_AWD1EN

#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk

ADC analog watchdog 1 enable on scope ADC group regular

◆ ADC_CFGR1_AWD1EN_Msk

#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos)

0x00800000

◆ ADC_CFGR1_AWD1EN_Pos

#define ADC_CFGR1_AWD1EN_Pos (23U)

◆ ADC_CFGR1_AWD1SGL

#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk

ADC analog watchdog 1 monitoring a single channel or all channels

◆ ADC_CFGR1_AWD1SGL_Msk

#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos)

0x00400000

◆ ADC_CFGR1_AWD1SGL_Pos

#define ADC_CFGR1_AWD1SGL_Pos (22U)

◆ ADC_CFGR1_CHSELRMOD

#define ADC_CFGR1_CHSELRMOD ADC_CFGR1_CHSELRMOD_Msk

ADC group regular sequencer mode

◆ ADC_CFGR1_CHSELRMOD_Msk

#define ADC_CFGR1_CHSELRMOD_Msk (0x1UL << ADC_CFGR1_CHSELRMOD_Pos)

0x00200000

◆ ADC_CFGR1_CHSELRMOD_Pos

#define ADC_CFGR1_CHSELRMOD_Pos (21U)

◆ ADC_CFGR1_CONT

#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk

ADC group regular continuous conversion mode

◆ ADC_CFGR1_CONT_Msk

#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos)

0x00002000

◆ ADC_CFGR1_CONT_Pos

#define ADC_CFGR1_CONT_Pos (13U)

◆ ADC_CFGR1_DISCEN

#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk

ADC group regular sequencer discontinuous mode

◆ ADC_CFGR1_DISCEN_Msk

#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos)

0x00010000

◆ ADC_CFGR1_DISCEN_Pos

#define ADC_CFGR1_DISCEN_Pos (16U)

◆ ADC_CFGR1_DMACFG

#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk

ADC DMA transfer configuration

◆ ADC_CFGR1_DMACFG_Msk

#define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos)

0x00000002

◆ ADC_CFGR1_DMACFG_Pos

#define ADC_CFGR1_DMACFG_Pos (1U)

◆ ADC_CFGR1_DMAEN

#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk

ADC DMA transfer enable

◆ ADC_CFGR1_DMAEN_Msk

#define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos)

0x00000001

◆ ADC_CFGR1_DMAEN_Pos

#define ADC_CFGR1_DMAEN_Pos (0U)

◆ ADC_CFGR1_EXTEN

#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk

ADC group regular external trigger polarity

◆ ADC_CFGR1_EXTEN_0

#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos)

0x00000400

◆ ADC_CFGR1_EXTEN_1

#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos)

0x00000800

◆ ADC_CFGR1_EXTEN_Msk

#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos)

0x00000C00

◆ ADC_CFGR1_EXTEN_Pos

#define ADC_CFGR1_EXTEN_Pos (10U)

◆ ADC_CFGR1_EXTSEL

#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk

ADC group regular external trigger source

◆ ADC_CFGR1_EXTSEL_0

#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos)

0x00000040

◆ ADC_CFGR1_EXTSEL_1

#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos)

0x00000080

◆ ADC_CFGR1_EXTSEL_2

#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos)

0x00000100

◆ ADC_CFGR1_EXTSEL_Msk

#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos)

0x000001C0

◆ ADC_CFGR1_EXTSEL_Pos

#define ADC_CFGR1_EXTSEL_Pos (6U)

◆ ADC_CFGR1_OVRMOD

#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk

ADC group regular overrun configuration

◆ ADC_CFGR1_OVRMOD_Msk

#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos)

0x00001000

◆ ADC_CFGR1_OVRMOD_Pos

#define ADC_CFGR1_OVRMOD_Pos (12U)

◆ ADC_CFGR1_RES

#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk

ADC data resolution

◆ ADC_CFGR1_RES_0

#define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos)

0x00000008

◆ ADC_CFGR1_RES_1

#define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos)

0x00000010

◆ ADC_CFGR1_RES_Msk

#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos)

0x00000018

◆ ADC_CFGR1_RES_Pos

#define ADC_CFGR1_RES_Pos (3U)

◆ ADC_CFGR1_SCANDIR

#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk

ADC group regular sequencer scan direction

◆ ADC_CFGR1_SCANDIR_Msk

#define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos)

0x00000004

◆ ADC_CFGR1_SCANDIR_Pos

#define ADC_CFGR1_SCANDIR_Pos (2U)

◆ ADC_CFGR1_WAIT

#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk

ADC low power auto wait

◆ ADC_CFGR1_WAIT_Msk

#define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos)

0x00004000

◆ ADC_CFGR1_WAIT_Pos

#define ADC_CFGR1_WAIT_Pos (14U)

◆ ADC_CFGR2_CKMODE

#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk

ADC clock source and prescaler (prescaler only for clock source synchronous)

◆ ADC_CFGR2_CKMODE_0

#define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos)

0x40000000

◆ ADC_CFGR2_CKMODE_1

#define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos)

0x80000000

◆ ADC_CFGR2_CKMODE_Msk

#define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos)

0xC0000000

◆ ADC_CFGR2_CKMODE_Pos

#define ADC_CFGR2_CKMODE_Pos (30U)

◆ ADC_CFGR2_LFTRIG

#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk

ADC low frequency trigger mode

◆ ADC_CFGR2_LFTRIG_Msk

#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos)

0x20000000

◆ ADC_CFGR2_LFTRIG_Pos

#define ADC_CFGR2_LFTRIG_Pos (29U)

◆ ADC_CFGR2_OVSE

#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk

ADC oversampler enable on scope ADC group regular

◆ ADC_CFGR2_OVSE_Msk

#define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos)

0x00000001

◆ ADC_CFGR2_OVSE_Pos

#define ADC_CFGR2_OVSE_Pos (0U)

◆ ADC_CFGR2_OVSR

#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk

ADC oversampling ratio

◆ ADC_CFGR2_OVSR_0

#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos)

0x00000004

◆ ADC_CFGR2_OVSR_1

#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos)

0x00000008

◆ ADC_CFGR2_OVSR_2

#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos)

0x00000010

◆ ADC_CFGR2_OVSR_Msk

#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos)

0x0000001C

◆ ADC_CFGR2_OVSR_Pos

#define ADC_CFGR2_OVSR_Pos (2U)

◆ ADC_CFGR2_OVSS

#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk

ADC oversampling shift

◆ ADC_CFGR2_OVSS_0

#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos)

0x00000020

◆ ADC_CFGR2_OVSS_1

#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos)

0x00000040

◆ ADC_CFGR2_OVSS_2

#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos)

0x00000080

◆ ADC_CFGR2_OVSS_3

#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos)

0x00000100

◆ ADC_CFGR2_OVSS_Msk

#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos)

0x000001E0

◆ ADC_CFGR2_OVSS_Pos

#define ADC_CFGR2_OVSS_Pos (5U)

◆ ADC_CFGR2_TOVS

#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk

ADC oversampling discontinuous mode (triggered mode) for ADC group regular

◆ ADC_CFGR2_TOVS_Msk

#define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos)

0x00000200

◆ ADC_CFGR2_TOVS_Pos

#define ADC_CFGR2_TOVS_Pos (9U)

◆ ADC_CHSELR_CHSEL

#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk

ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset

◆ ADC_CHSELR_CHSEL0

#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk

ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset

◆ ADC_CHSELR_CHSEL0_Msk

#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos)

0x00000001

◆ ADC_CHSELR_CHSEL0_Pos

#define ADC_CHSELR_CHSEL0_Pos (0U)

◆ ADC_CHSELR_CHSEL1

#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk

ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset

◆ ADC_CHSELR_CHSEL10

#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk

ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset

◆ ADC_CHSELR_CHSEL10_Msk

#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos)

0x00000400

◆ ADC_CHSELR_CHSEL10_Pos

#define ADC_CHSELR_CHSEL10_Pos (10U)

◆ ADC_CHSELR_CHSEL11

#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk

ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset

◆ ADC_CHSELR_CHSEL11_Msk

#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos)

0x00000800

◆ ADC_CHSELR_CHSEL11_Pos

#define ADC_CHSELR_CHSEL11_Pos (11U)

◆ ADC_CHSELR_CHSEL12

#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk

ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset

◆ ADC_CHSELR_CHSEL12_Msk

#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos)

0x00001000

◆ ADC_CHSELR_CHSEL12_Pos

#define ADC_CHSELR_CHSEL12_Pos (12U)

◆ ADC_CHSELR_CHSEL13

#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk

ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset

◆ ADC_CHSELR_CHSEL13_Msk

#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos)

0x00002000

◆ ADC_CHSELR_CHSEL13_Pos

#define ADC_CHSELR_CHSEL13_Pos (13U)

◆ ADC_CHSELR_CHSEL14

#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk

ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset

◆ ADC_CHSELR_CHSEL14_Msk

#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos)

0x00004000

◆ ADC_CHSELR_CHSEL14_Pos

#define ADC_CHSELR_CHSEL14_Pos (14U)

◆ ADC_CHSELR_CHSEL15

#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk

ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset

◆ ADC_CHSELR_CHSEL15_Msk

#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos)

0x00008000

◆ ADC_CHSELR_CHSEL15_Pos

#define ADC_CHSELR_CHSEL15_Pos (15U)

◆ ADC_CHSELR_CHSEL16

#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk

ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset

◆ ADC_CHSELR_CHSEL16_Msk

#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos)

0x00010000

◆ ADC_CHSELR_CHSEL16_Pos

#define ADC_CHSELR_CHSEL16_Pos (16U)

◆ ADC_CHSELR_CHSEL17

#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk

ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset

◆ ADC_CHSELR_CHSEL17_Msk

#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos)

0x00020000

◆ ADC_CHSELR_CHSEL17_Pos

#define ADC_CHSELR_CHSEL17_Pos (17U)

◆ ADC_CHSELR_CHSEL18

#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk

ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset

◆ ADC_CHSELR_CHSEL18_Msk

#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos)

0x00040000

◆ ADC_CHSELR_CHSEL18_Pos

#define ADC_CHSELR_CHSEL18_Pos (18U)

◆ ADC_CHSELR_CHSEL1_Msk

#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos)

0x00000002

◆ ADC_CHSELR_CHSEL1_Pos

#define ADC_CHSELR_CHSEL1_Pos (1U)

◆ ADC_CHSELR_CHSEL2

#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk

ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset

◆ ADC_CHSELR_CHSEL2_Msk

#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos)

0x00000004

◆ ADC_CHSELR_CHSEL2_Pos

#define ADC_CHSELR_CHSEL2_Pos (2U)

◆ ADC_CHSELR_CHSEL3

#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk

ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset

◆ ADC_CHSELR_CHSEL3_Msk

#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos)

0x00000008

◆ ADC_CHSELR_CHSEL3_Pos

#define ADC_CHSELR_CHSEL3_Pos (3U)

◆ ADC_CHSELR_CHSEL4

#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk

ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset

◆ ADC_CHSELR_CHSEL4_Msk

#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos)

0x00000010

◆ ADC_CHSELR_CHSEL4_Pos

#define ADC_CHSELR_CHSEL4_Pos (4U)

◆ ADC_CHSELR_CHSEL5

#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk

ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset

◆ ADC_CHSELR_CHSEL5_Msk

#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos)

0x00000020

◆ ADC_CHSELR_CHSEL5_Pos

#define ADC_CHSELR_CHSEL5_Pos (5U)

◆ ADC_CHSELR_CHSEL6

#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk

ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset

◆ ADC_CHSELR_CHSEL6_Msk

#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos)

0x00000040

◆ ADC_CHSELR_CHSEL6_Pos

#define ADC_CHSELR_CHSEL6_Pos (6U)

◆ ADC_CHSELR_CHSEL7

#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk

ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset

◆ ADC_CHSELR_CHSEL7_Msk

#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos)

0x00000080

◆ ADC_CHSELR_CHSEL7_Pos

#define ADC_CHSELR_CHSEL7_Pos (7U)

◆ ADC_CHSELR_CHSEL8

#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk

ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset

◆ ADC_CHSELR_CHSEL8_Msk

#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos)

0x00000100

◆ ADC_CHSELR_CHSEL8_Pos

#define ADC_CHSELR_CHSEL8_Pos (8U)

◆ ADC_CHSELR_CHSEL9

#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk

ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset

◆ ADC_CHSELR_CHSEL9_Msk

#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos)

0x00000200

◆ ADC_CHSELR_CHSEL9_Pos

#define ADC_CHSELR_CHSEL9_Pos (9U)

◆ ADC_CHSELR_CHSEL_Msk

#define ADC_CHSELR_CHSEL_Msk (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos)

0x0007FFFF

◆ ADC_CHSELR_CHSEL_Pos

#define ADC_CHSELR_CHSEL_Pos (0U)

◆ ADC_CHSELR_SQ1

#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk

ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set

◆ ADC_CHSELR_SQ1_0

#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos)

0x00000001

◆ ADC_CHSELR_SQ1_1

#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos)

0x00000002

◆ ADC_CHSELR_SQ1_2

#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos)

0x00000004

◆ ADC_CHSELR_SQ1_3

#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos)

0x00000008

◆ ADC_CHSELR_SQ1_Msk

#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos)

0x0000000F

◆ ADC_CHSELR_SQ1_Pos

#define ADC_CHSELR_SQ1_Pos (0U)

◆ ADC_CHSELR_SQ2

#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk

ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set

◆ ADC_CHSELR_SQ2_0

#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos)

0x00000010

◆ ADC_CHSELR_SQ2_1

#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos)

0x00000020

◆ ADC_CHSELR_SQ2_2

#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos)

0x00000040

◆ ADC_CHSELR_SQ2_3

#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos)

0x00000080

◆ ADC_CHSELR_SQ2_Msk

#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos)

0x000000F0

◆ ADC_CHSELR_SQ2_Pos

#define ADC_CHSELR_SQ2_Pos (4U)

◆ ADC_CHSELR_SQ3

#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk

ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set

◆ ADC_CHSELR_SQ3_0

#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos)

0x00000100

◆ ADC_CHSELR_SQ3_1

#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos)

0x00000200

◆ ADC_CHSELR_SQ3_2

#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos)

0x00000400

◆ ADC_CHSELR_SQ3_3

#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos)

0x00000800

◆ ADC_CHSELR_SQ3_Msk

#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos)

0x00000F00

◆ ADC_CHSELR_SQ3_Pos

#define ADC_CHSELR_SQ3_Pos (8U)

◆ ADC_CHSELR_SQ4

#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk

ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set

◆ ADC_CHSELR_SQ4_0

#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos)

0x00001000

◆ ADC_CHSELR_SQ4_1

#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos)

0x00002000

◆ ADC_CHSELR_SQ4_2

#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos)

0x00004000

◆ ADC_CHSELR_SQ4_3

#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos)

0x00008000

◆ ADC_CHSELR_SQ4_Msk

#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos)

0x0000F000

◆ ADC_CHSELR_SQ4_Pos

#define ADC_CHSELR_SQ4_Pos (12U)

◆ ADC_CHSELR_SQ5

#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk

ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set

◆ ADC_CHSELR_SQ5_0

#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos)

0x00010000

◆ ADC_CHSELR_SQ5_1

#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos)

0x00020000

◆ ADC_CHSELR_SQ5_2

#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos)

0x00040000

◆ ADC_CHSELR_SQ5_3

#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos)

0x00080000

◆ ADC_CHSELR_SQ5_Msk

#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos)

0x000F0000

◆ ADC_CHSELR_SQ5_Pos

#define ADC_CHSELR_SQ5_Pos (16U)

◆ ADC_CHSELR_SQ6

#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk

ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set

◆ ADC_CHSELR_SQ6_0

#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos)

0x00100000

◆ ADC_CHSELR_SQ6_1

#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos)

0x00200000

◆ ADC_CHSELR_SQ6_2

#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos)

0x00400000

◆ ADC_CHSELR_SQ6_3

#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos)

0x00800000

◆ ADC_CHSELR_SQ6_Msk

#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos)

0x00F00000

◆ ADC_CHSELR_SQ6_Pos

#define ADC_CHSELR_SQ6_Pos (20U)

◆ ADC_CHSELR_SQ7

#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk

ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set

◆ ADC_CHSELR_SQ7_0

#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos)

0x01000000

◆ ADC_CHSELR_SQ7_1

#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos)

0x02000000

◆ ADC_CHSELR_SQ7_2

#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos)

0x04000000

◆ ADC_CHSELR_SQ7_3

#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos)

0x08000000

◆ ADC_CHSELR_SQ7_Msk

#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos)

0x0F000000

◆ ADC_CHSELR_SQ7_Pos

#define ADC_CHSELR_SQ7_Pos (24U)

◆ ADC_CHSELR_SQ8

#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk

ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set

◆ ADC_CHSELR_SQ8_0

#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos)

0x10000000

◆ ADC_CHSELR_SQ8_1

#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos)

0x20000000

◆ ADC_CHSELR_SQ8_2

#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos)

0x40000000

◆ ADC_CHSELR_SQ8_3

#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos)

0x80000000

◆ ADC_CHSELR_SQ8_Msk

#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos)

0xF0000000

◆ ADC_CHSELR_SQ8_Pos

#define ADC_CHSELR_SQ8_Pos (28U)

◆ ADC_CHSELR_SQ_ALL

#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk

ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set

◆ ADC_CHSELR_SQ_ALL_Msk

#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos)

0xFFFFFFFF

◆ ADC_CHSELR_SQ_ALL_Pos

#define ADC_CHSELR_SQ_ALL_Pos (0U)

◆ ADC_CR_ADCAL

#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk

ADC calibration

◆ ADC_CR_ADCAL_Msk

#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos)

0x80000000

◆ ADC_CR_ADCAL_Pos

#define ADC_CR_ADCAL_Pos (31U)

◆ ADC_CR_ADDIS

#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk

ADC disable

◆ ADC_CR_ADDIS_Msk

#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos)

0x00000002

◆ ADC_CR_ADDIS_Pos

#define ADC_CR_ADDIS_Pos (1U)

◆ ADC_CR_ADEN

#define ADC_CR_ADEN ADC_CR_ADEN_Msk

ADC enable

◆ ADC_CR_ADEN_Msk

#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos)

0x00000001

◆ ADC_CR_ADEN_Pos

#define ADC_CR_ADEN_Pos (0U)

◆ ADC_CR_ADSTART

#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk

ADC group regular conversion start

◆ ADC_CR_ADSTART_Msk

#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos)

0x00000004

◆ ADC_CR_ADSTART_Pos

#define ADC_CR_ADSTART_Pos (2U)

◆ ADC_CR_ADSTP

#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk

ADC group regular conversion stop

◆ ADC_CR_ADSTP_Msk

#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos)

0x00000010

◆ ADC_CR_ADSTP_Pos

#define ADC_CR_ADSTP_Pos (4U)

◆ ADC_CR_ADVREGEN

#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk

ADC voltage regulator enable

◆ ADC_CR_ADVREGEN_Msk

#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos)

0x10000000

◆ ADC_CR_ADVREGEN_Pos

#define ADC_CR_ADVREGEN_Pos (28U)

◆ ADC_DR_DATA

#define ADC_DR_DATA ADC_DR_DATA_Msk

ADC group regular conversion data

◆ ADC_DR_DATA_0

#define ADC_DR_DATA_0 (0x0001UL << ADC_DR_DATA_Pos)

0x00000001

◆ ADC_DR_DATA_1

#define ADC_DR_DATA_1 (0x0002UL << ADC_DR_DATA_Pos)

0x00000002

◆ ADC_DR_DATA_10

#define ADC_DR_DATA_10 (0x0400UL << ADC_DR_DATA_Pos)

0x00000400

◆ ADC_DR_DATA_11

#define ADC_DR_DATA_11 (0x0800UL << ADC_DR_DATA_Pos)

0x00000800

◆ ADC_DR_DATA_12

#define ADC_DR_DATA_12 (0x1000UL << ADC_DR_DATA_Pos)

0x00001000

◆ ADC_DR_DATA_13

#define ADC_DR_DATA_13 (0x2000UL << ADC_DR_DATA_Pos)

0x00002000

◆ ADC_DR_DATA_14

#define ADC_DR_DATA_14 (0x4000UL << ADC_DR_DATA_Pos)

0x00004000

◆ ADC_DR_DATA_15

#define ADC_DR_DATA_15 (0x8000UL << ADC_DR_DATA_Pos)

0x00008000

◆ ADC_DR_DATA_2

#define ADC_DR_DATA_2 (0x0004UL << ADC_DR_DATA_Pos)

0x00000004

◆ ADC_DR_DATA_3

#define ADC_DR_DATA_3 (0x0008UL << ADC_DR_DATA_Pos)

0x00000008

◆ ADC_DR_DATA_4

#define ADC_DR_DATA_4 (0x0010UL << ADC_DR_DATA_Pos)

0x00000010

◆ ADC_DR_DATA_5

#define ADC_DR_DATA_5 (0x0020UL << ADC_DR_DATA_Pos)

0x00000020

◆ ADC_DR_DATA_6

#define ADC_DR_DATA_6 (0x0040UL << ADC_DR_DATA_Pos)

0x00000040

◆ ADC_DR_DATA_7

#define ADC_DR_DATA_7 (0x0080UL << ADC_DR_DATA_Pos)

0x00000080

◆ ADC_DR_DATA_8

#define ADC_DR_DATA_8 (0x0100UL << ADC_DR_DATA_Pos)

0x00000100

◆ ADC_DR_DATA_9

#define ADC_DR_DATA_9 (0x0200UL << ADC_DR_DATA_Pos)

0x00000200

◆ ADC_DR_DATA_Msk

#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos)

0x0000FFFF

◆ ADC_DR_DATA_Pos

#define ADC_DR_DATA_Pos (0U)

◆ ADC_IER_ADRDYIE

#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk

ADC ready interrupt

◆ ADC_IER_ADRDYIE_Msk

#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos)

0x00000001

◆ ADC_IER_ADRDYIE_Pos

#define ADC_IER_ADRDYIE_Pos (0U)

◆ ADC_IER_AWD1IE

#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk

ADC analog watchdog 1 interrupt

◆ ADC_IER_AWD1IE_Msk

#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos)

0x00000080

◆ ADC_IER_AWD1IE_Pos

#define ADC_IER_AWD1IE_Pos (7U)

◆ ADC_IER_AWD2IE

#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk

ADC analog watchdog 2 interrupt

◆ ADC_IER_AWD2IE_Msk

#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos)

0x00000100

◆ ADC_IER_AWD2IE_Pos

#define ADC_IER_AWD2IE_Pos (8U)

◆ ADC_IER_AWD3IE

#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk

ADC analog watchdog 3 interrupt

◆ ADC_IER_AWD3IE_Msk

#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos)

0x00000200

◆ ADC_IER_AWD3IE_Pos

#define ADC_IER_AWD3IE_Pos (9U)

◆ ADC_IER_CCRDYIE

#define ADC_IER_CCRDYIE ADC_IER_CCRDYIE_Msk

ADC channel configuration ready interrupt

◆ ADC_IER_CCRDYIE_Msk

#define ADC_IER_CCRDYIE_Msk (0x1UL << ADC_IER_CCRDYIE_Pos)

0x00002000

◆ ADC_IER_CCRDYIE_Pos

#define ADC_IER_CCRDYIE_Pos (13U)

◆ ADC_IER_EOCALIE

#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk

ADC end of calibration interrupt

◆ ADC_IER_EOCALIE_Msk

#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos)

0x00000800

◆ ADC_IER_EOCALIE_Pos

#define ADC_IER_EOCALIE_Pos (11U)

◆ ADC_IER_EOCIE

#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk

ADC group regular end of unitary conversion interrupt

◆ ADC_IER_EOCIE_Msk

#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos)

0x00000004

◆ ADC_IER_EOCIE_Pos

#define ADC_IER_EOCIE_Pos (2U)

◆ ADC_IER_EOSEQIE

#define ADC_IER_EOSEQIE (ADC_IER_EOSIE)

◆ ADC_IER_EOSIE

#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk

ADC group regular end of sequence conversions interrupt

◆ ADC_IER_EOSIE_Msk

#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos)

0x00000008

◆ ADC_IER_EOSIE_Pos

#define ADC_IER_EOSIE_Pos (3U)

◆ ADC_IER_EOSMPIE

#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk

ADC group regular end of sampling interrupt

◆ ADC_IER_EOSMPIE_Msk

#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos)

0x00000002

◆ ADC_IER_EOSMPIE_Pos

#define ADC_IER_EOSMPIE_Pos (1U)

◆ ADC_IER_OVRIE

#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk

ADC group regular overrun interrupt

◆ ADC_IER_OVRIE_Msk

#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos)

0x00000010

◆ ADC_IER_OVRIE_Pos

#define ADC_IER_OVRIE_Pos (4U)

◆ ADC_ISR_ADRDY

#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk

ADC ready flag

◆ ADC_ISR_ADRDY_Msk

#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos)

0x00000001

◆ ADC_ISR_ADRDY_Pos

#define ADC_ISR_ADRDY_Pos (0U)

◆ ADC_ISR_AWD1

#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk

ADC analog watchdog 1 flag

◆ ADC_ISR_AWD1_Msk

#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos)

0x00000080

◆ ADC_ISR_AWD1_Pos

#define ADC_ISR_AWD1_Pos (7U)

◆ ADC_ISR_AWD2

#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk

ADC analog watchdog 2 flag

◆ ADC_ISR_AWD2_Msk

#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos)

0x00000100

◆ ADC_ISR_AWD2_Pos

#define ADC_ISR_AWD2_Pos (8U)

◆ ADC_ISR_AWD3

#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk

ADC analog watchdog 3 flag

◆ ADC_ISR_AWD3_Msk

#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos)

0x00000200

◆ ADC_ISR_AWD3_Pos

#define ADC_ISR_AWD3_Pos (9U)

◆ ADC_ISR_CCRDY

#define ADC_ISR_CCRDY ADC_ISR_CCRDY_Msk

ADC channel configuration ready flag

◆ ADC_ISR_CCRDY_Msk

#define ADC_ISR_CCRDY_Msk (0x1UL << ADC_ISR_CCRDY_Pos)

0x00002000

◆ ADC_ISR_CCRDY_Pos

#define ADC_ISR_CCRDY_Pos (13U)

◆ ADC_ISR_EOC

#define ADC_ISR_EOC ADC_ISR_EOC_Msk

ADC group regular end of unitary conversion flag

◆ ADC_ISR_EOC_Msk

#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos)

0x00000004

◆ ADC_ISR_EOC_Pos

#define ADC_ISR_EOC_Pos (2U)

◆ ADC_ISR_EOCAL

#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk

ADC end of calibration flag

◆ ADC_ISR_EOCAL_Msk

#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos)

0x00000800

◆ ADC_ISR_EOCAL_Pos

#define ADC_ISR_EOCAL_Pos (11U)

◆ ADC_ISR_EOS

#define ADC_ISR_EOS ADC_ISR_EOS_Msk

ADC group regular end of sequence conversions flag

◆ ADC_ISR_EOS_Msk

#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos)

0x00000008

◆ ADC_ISR_EOS_Pos

#define ADC_ISR_EOS_Pos (3U)

◆ ADC_ISR_EOSEQ

#define ADC_ISR_EOSEQ (ADC_ISR_EOS)

◆ ADC_ISR_EOSMP

#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk

ADC group regular end of sampling flag

◆ ADC_ISR_EOSMP_Msk

#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos)

0x00000002

◆ ADC_ISR_EOSMP_Pos

#define ADC_ISR_EOSMP_Pos (1U)

◆ ADC_ISR_OVR

#define ADC_ISR_OVR ADC_ISR_OVR_Msk

ADC group regular overrun flag

◆ ADC_ISR_OVR_Msk

#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos)

0x00000010

◆ ADC_ISR_OVR_Pos

#define ADC_ISR_OVR_Pos (4U)

◆ ADC_SMPR_SMP1

#define ADC_SMPR_SMP1 ADC_SMPR_SMP1_Msk

ADC group of channels sampling time 1

◆ ADC_SMPR_SMP1_0

#define ADC_SMPR_SMP1_0 (0x1UL << ADC_SMPR_SMP1_Pos)

0x00000001

◆ ADC_SMPR_SMP1_1

#define ADC_SMPR_SMP1_1 (0x2UL << ADC_SMPR_SMP1_Pos)

0x00000002

◆ ADC_SMPR_SMP1_2

#define ADC_SMPR_SMP1_2 (0x4UL << ADC_SMPR_SMP1_Pos)

0x00000004

◆ ADC_SMPR_SMP1_Msk

#define ADC_SMPR_SMP1_Msk (0x7UL << ADC_SMPR_SMP1_Pos)

0x00000007

◆ ADC_SMPR_SMP1_Pos

#define ADC_SMPR_SMP1_Pos (0U)

◆ ADC_SMPR_SMP2

#define ADC_SMPR_SMP2 ADC_SMPR_SMP2_Msk

ADC group of channels sampling time 2

◆ ADC_SMPR_SMP2_0

#define ADC_SMPR_SMP2_0 (0x1UL << ADC_SMPR_SMP2_Pos)

0x00000010

◆ ADC_SMPR_SMP2_1

#define ADC_SMPR_SMP2_1 (0x2UL << ADC_SMPR_SMP2_Pos)

0x00000020

◆ ADC_SMPR_SMP2_2

#define ADC_SMPR_SMP2_2 (0x4UL << ADC_SMPR_SMP2_Pos)

0x00000040

◆ ADC_SMPR_SMP2_Msk

#define ADC_SMPR_SMP2_Msk (0x7UL << ADC_SMPR_SMP2_Pos)

0x00000070

◆ ADC_SMPR_SMP2_Pos

#define ADC_SMPR_SMP2_Pos (4U)

◆ ADC_SMPR_SMPSEL

#define ADC_SMPR_SMPSEL ADC_SMPR_SMPSEL_Msk

ADC all channels sampling time selection

◆ ADC_SMPR_SMPSEL0

#define ADC_SMPR_SMPSEL0 ADC_SMPR_SMPSEL0_Msk

ADC channel 0 sampling time selection

◆ ADC_SMPR_SMPSEL0_Msk

#define ADC_SMPR_SMPSEL0_Msk (0x1UL << ADC_SMPR_SMPSEL0_Pos)

0x00000100

◆ ADC_SMPR_SMPSEL0_Pos

#define ADC_SMPR_SMPSEL0_Pos (8U)

◆ ADC_SMPR_SMPSEL1

#define ADC_SMPR_SMPSEL1 ADC_SMPR_SMPSEL1_Msk

ADC channel 1 sampling time selection

◆ ADC_SMPR_SMPSEL10

#define ADC_SMPR_SMPSEL10 ADC_SMPR_SMPSEL10_Msk

ADC channel 10 sampling time selection

◆ ADC_SMPR_SMPSEL10_Msk

#define ADC_SMPR_SMPSEL10_Msk (0x1UL << ADC_SMPR_SMPSEL10_Pos)

0x00040000

◆ ADC_SMPR_SMPSEL10_Pos

#define ADC_SMPR_SMPSEL10_Pos (18U)

◆ ADC_SMPR_SMPSEL11

#define ADC_SMPR_SMPSEL11 ADC_SMPR_SMPSEL11_Msk

ADC channel 11 sampling time selection

◆ ADC_SMPR_SMPSEL11_Msk

#define ADC_SMPR_SMPSEL11_Msk (0x1UL << ADC_SMPR_SMPSEL11_Pos)

0x00080000

◆ ADC_SMPR_SMPSEL11_Pos

#define ADC_SMPR_SMPSEL11_Pos (19U)

◆ ADC_SMPR_SMPSEL12

#define ADC_SMPR_SMPSEL12 ADC_SMPR_SMPSEL12_Msk

ADC channel 12 sampling time selection

◆ ADC_SMPR_SMPSEL12_Msk

#define ADC_SMPR_SMPSEL12_Msk (0x1UL << ADC_SMPR_SMPSEL12_Pos)

0x00100000

◆ ADC_SMPR_SMPSEL12_Pos

#define ADC_SMPR_SMPSEL12_Pos (20U)

◆ ADC_SMPR_SMPSEL13

#define ADC_SMPR_SMPSEL13 ADC_SMPR_SMPSEL13_Msk

ADC channel 13 sampling time selection

◆ ADC_SMPR_SMPSEL13_Msk

#define ADC_SMPR_SMPSEL13_Msk (0x1UL << ADC_SMPR_SMPSEL13_Pos)

0x00200000

◆ ADC_SMPR_SMPSEL13_Pos

#define ADC_SMPR_SMPSEL13_Pos (21U)

◆ ADC_SMPR_SMPSEL14

#define ADC_SMPR_SMPSEL14 ADC_SMPR_SMPSEL14_Msk

ADC channel 14 sampling time selection

◆ ADC_SMPR_SMPSEL14_Msk

#define ADC_SMPR_SMPSEL14_Msk (0x1UL << ADC_SMPR_SMPSEL14_Pos)

0x00400000

◆ ADC_SMPR_SMPSEL14_Pos

#define ADC_SMPR_SMPSEL14_Pos (22U)

◆ ADC_SMPR_SMPSEL15

#define ADC_SMPR_SMPSEL15 ADC_SMPR_SMPSEL15_Msk

ADC channel 15 sampling time selection

◆ ADC_SMPR_SMPSEL15_Msk

#define ADC_SMPR_SMPSEL15_Msk (0x1UL << ADC_SMPR_SMPSEL15_Pos)

0x00800000

◆ ADC_SMPR_SMPSEL15_Pos

#define ADC_SMPR_SMPSEL15_Pos (23U)

◆ ADC_SMPR_SMPSEL16

#define ADC_SMPR_SMPSEL16 ADC_SMPR_SMPSEL16_Msk

ADC channel 16 sampling time selection

◆ ADC_SMPR_SMPSEL16_Msk

#define ADC_SMPR_SMPSEL16_Msk (0x1UL << ADC_SMPR_SMPSEL16_Pos)

0x01000000

◆ ADC_SMPR_SMPSEL16_Pos

#define ADC_SMPR_SMPSEL16_Pos (24U)

◆ ADC_SMPR_SMPSEL17

#define ADC_SMPR_SMPSEL17 ADC_SMPR_SMPSEL17_Msk

ADC channel 17 sampling time selection

◆ ADC_SMPR_SMPSEL17_Msk

#define ADC_SMPR_SMPSEL17_Msk (0x1UL << ADC_SMPR_SMPSEL17_Pos)

0x02000000

◆ ADC_SMPR_SMPSEL17_Pos

#define ADC_SMPR_SMPSEL17_Pos (25U)

◆ ADC_SMPR_SMPSEL18

#define ADC_SMPR_SMPSEL18 ADC_SMPR_SMPSEL18_Msk

ADC channel 18 sampling time selection

◆ ADC_SMPR_SMPSEL18_Msk

#define ADC_SMPR_SMPSEL18_Msk (0x1UL << ADC_SMPR_SMPSEL18_Pos)

0x04000000

◆ ADC_SMPR_SMPSEL18_Pos

#define ADC_SMPR_SMPSEL18_Pos (26U)

◆ ADC_SMPR_SMPSEL1_Msk

#define ADC_SMPR_SMPSEL1_Msk (0x1UL << ADC_SMPR_SMPSEL1_Pos)

0x00000200

◆ ADC_SMPR_SMPSEL1_Pos

#define ADC_SMPR_SMPSEL1_Pos (9U)

◆ ADC_SMPR_SMPSEL2

#define ADC_SMPR_SMPSEL2 ADC_SMPR_SMPSEL2_Msk

ADC channel 2 sampling time selection

◆ ADC_SMPR_SMPSEL2_Msk

#define ADC_SMPR_SMPSEL2_Msk (0x1UL << ADC_SMPR_SMPSEL2_Pos)

0x00000400

◆ ADC_SMPR_SMPSEL2_Pos

#define ADC_SMPR_SMPSEL2_Pos (10U)

◆ ADC_SMPR_SMPSEL3

#define ADC_SMPR_SMPSEL3 ADC_SMPR_SMPSEL3_Msk

ADC channel 3 sampling time selection

◆ ADC_SMPR_SMPSEL3_Msk

#define ADC_SMPR_SMPSEL3_Msk (0x1UL << ADC_SMPR_SMPSEL3_Pos)

0x00000800

◆ ADC_SMPR_SMPSEL3_Pos

#define ADC_SMPR_SMPSEL3_Pos (11U)

◆ ADC_SMPR_SMPSEL4

#define ADC_SMPR_SMPSEL4 ADC_SMPR_SMPSEL4_Msk

ADC channel 4 sampling time selection

◆ ADC_SMPR_SMPSEL4_Msk

#define ADC_SMPR_SMPSEL4_Msk (0x1UL << ADC_SMPR_SMPSEL4_Pos)

0x00001000

◆ ADC_SMPR_SMPSEL4_Pos

#define ADC_SMPR_SMPSEL4_Pos (12U)

◆ ADC_SMPR_SMPSEL5

#define ADC_SMPR_SMPSEL5 ADC_SMPR_SMPSEL5_Msk

ADC channel 5 sampling time selection

◆ ADC_SMPR_SMPSEL5_Msk

#define ADC_SMPR_SMPSEL5_Msk (0x1UL << ADC_SMPR_SMPSEL5_Pos)

0x00002000

◆ ADC_SMPR_SMPSEL5_Pos

#define ADC_SMPR_SMPSEL5_Pos (13U)

◆ ADC_SMPR_SMPSEL6

#define ADC_SMPR_SMPSEL6 ADC_SMPR_SMPSEL6_Msk

ADC channel 6 sampling time selection

◆ ADC_SMPR_SMPSEL6_Msk

#define ADC_SMPR_SMPSEL6_Msk (0x1UL << ADC_SMPR_SMPSEL6_Pos)

0x00004000

◆ ADC_SMPR_SMPSEL6_Pos

#define ADC_SMPR_SMPSEL6_Pos (14U)

◆ ADC_SMPR_SMPSEL7

#define ADC_SMPR_SMPSEL7 ADC_SMPR_SMPSEL7_Msk

ADC channel 7 sampling time selection

◆ ADC_SMPR_SMPSEL7_Msk

#define ADC_SMPR_SMPSEL7_Msk (0x1UL << ADC_SMPR_SMPSEL7_Pos)

0x00008000

◆ ADC_SMPR_SMPSEL7_Pos

#define ADC_SMPR_SMPSEL7_Pos (15U)

◆ ADC_SMPR_SMPSEL8

#define ADC_SMPR_SMPSEL8 ADC_SMPR_SMPSEL8_Msk

ADC channel 8 sampling time selection

◆ ADC_SMPR_SMPSEL8_Msk

#define ADC_SMPR_SMPSEL8_Msk (0x1UL << ADC_SMPR_SMPSEL8_Pos)

0x00010000

◆ ADC_SMPR_SMPSEL8_Pos

#define ADC_SMPR_SMPSEL8_Pos (16U)

◆ ADC_SMPR_SMPSEL9

#define ADC_SMPR_SMPSEL9 ADC_SMPR_SMPSEL9_Msk

ADC channel 9 sampling time selection

◆ ADC_SMPR_SMPSEL9_Msk

#define ADC_SMPR_SMPSEL9_Msk (0x1UL << ADC_SMPR_SMPSEL9_Pos)

0x00020000

◆ ADC_SMPR_SMPSEL9_Pos

#define ADC_SMPR_SMPSEL9_Pos (17U)

◆ ADC_SMPR_SMPSEL_Msk

#define ADC_SMPR_SMPSEL_Msk (0x7FFFFUL << ADC_SMPR_SMPSEL_Pos)

0x07FFFF00

◆ ADC_SMPR_SMPSEL_Pos

#define ADC_SMPR_SMPSEL_Pos (8U)

◆ ADC_TR1_HT1

#define ADC_TR1_HT1 ADC_AWD1TR_HT1

◆ ADC_TR1_HT1_0

#define ADC_TR1_HT1_0 ADC_AWD1TR_HT1_0

◆ ADC_TR1_HT1_1

#define ADC_TR1_HT1_1 ADC_AWD1TR_HT1_1

◆ ADC_TR1_HT1_10

#define ADC_TR1_HT1_10 ADC_AWD1TR_HT1_10

◆ ADC_TR1_HT1_11

#define ADC_TR1_HT1_11 ADC_AWD1TR_HT1_11

◆ ADC_TR1_HT1_2

#define ADC_TR1_HT1_2 ADC_AWD1TR_HT1_2

◆ ADC_TR1_HT1_3

#define ADC_TR1_HT1_3 ADC_AWD1TR_HT1_3

◆ ADC_TR1_HT1_4

#define ADC_TR1_HT1_4 ADC_AWD1TR_HT1_4

◆ ADC_TR1_HT1_5

#define ADC_TR1_HT1_5 ADC_AWD1TR_HT1_5

◆ ADC_TR1_HT1_6

#define ADC_TR1_HT1_6 ADC_AWD1TR_HT1_6

◆ ADC_TR1_HT1_7

#define ADC_TR1_HT1_7 ADC_AWD1TR_HT1_7

◆ ADC_TR1_HT1_8

#define ADC_TR1_HT1_8 ADC_AWD1TR_HT1_8

◆ ADC_TR1_HT1_9

#define ADC_TR1_HT1_9 ADC_AWD1TR_HT1_9

◆ ADC_TR1_LT1

#define ADC_TR1_LT1 ADC_AWD1TR_LT1

◆ ADC_TR1_LT1_0

#define ADC_TR1_LT1_0 ADC_AWD1TR_LT1_0

◆ ADC_TR1_LT1_1

#define ADC_TR1_LT1_1 ADC_AWD1TR_LT1_1

◆ ADC_TR1_LT1_10

#define ADC_TR1_LT1_10 ADC_AWD1TR_LT1_10

◆ ADC_TR1_LT1_11

#define ADC_TR1_LT1_11 ADC_AWD1TR_LT1_11

◆ ADC_TR1_LT1_2

#define ADC_TR1_LT1_2 ADC_AWD1TR_LT1_2

◆ ADC_TR1_LT1_3

#define ADC_TR1_LT1_3 ADC_AWD1TR_LT1_3

◆ ADC_TR1_LT1_4

#define ADC_TR1_LT1_4 ADC_AWD1TR_LT1_4

◆ ADC_TR1_LT1_5

#define ADC_TR1_LT1_5 ADC_AWD1TR_LT1_5

◆ ADC_TR1_LT1_6

#define ADC_TR1_LT1_6 ADC_AWD1TR_LT1_6

◆ ADC_TR1_LT1_7

#define ADC_TR1_LT1_7 ADC_AWD1TR_LT1_7

◆ ADC_TR1_LT1_8

#define ADC_TR1_LT1_8 ADC_AWD1TR_LT1_8

◆ ADC_TR1_LT1_9

#define ADC_TR1_LT1_9 ADC_AWD1TR_LT1_9

◆ ADC_TR2_HT2

#define ADC_TR2_HT2 ADC_AWD2TR_HT2

◆ ADC_TR2_HT2_0

#define ADC_TR2_HT2_0 ADC_AWD2TR_HT2_0

◆ ADC_TR2_HT2_1

#define ADC_TR2_HT2_1 ADC_AWD2TR_HT2_1

◆ ADC_TR2_HT2_10

#define ADC_TR2_HT2_10 ADC_AWD2TR_HT2_10

◆ ADC_TR2_HT2_11

#define ADC_TR2_HT2_11 ADC_AWD2TR_HT2_11

◆ ADC_TR2_HT2_2

#define ADC_TR2_HT2_2 ADC_AWD2TR_HT2_2

◆ ADC_TR2_HT2_3

#define ADC_TR2_HT2_3 ADC_AWD2TR_HT2_3

◆ ADC_TR2_HT2_4

#define ADC_TR2_HT2_4 ADC_AWD2TR_HT2_4

◆ ADC_TR2_HT2_5

#define ADC_TR2_HT2_5 ADC_AWD2TR_HT2_5

◆ ADC_TR2_HT2_6

#define ADC_TR2_HT2_6 ADC_AWD2TR_HT2_6

◆ ADC_TR2_HT2_7

#define ADC_TR2_HT2_7 ADC_AWD2TR_HT2_7

◆ ADC_TR2_HT2_8

#define ADC_TR2_HT2_8 ADC_AWD2TR_HT2_8

◆ ADC_TR2_HT2_9

#define ADC_TR2_HT2_9 ADC_AWD2TR_HT2_9

◆ ADC_TR2_LT2

#define ADC_TR2_LT2 ADC_AWD2TR_LT2

◆ ADC_TR2_LT2_0

#define ADC_TR2_LT2_0 ADC_AWD2TR_LT2_0

◆ ADC_TR2_LT2_1

#define ADC_TR2_LT2_1 ADC_AWD2TR_LT2_1

◆ ADC_TR2_LT2_10

#define ADC_TR2_LT2_10 ADC_AWD2TR_LT2_10

◆ ADC_TR2_LT2_11

#define ADC_TR2_LT2_11 ADC_AWD2TR_LT2_11

◆ ADC_TR2_LT2_2

#define ADC_TR2_LT2_2 ADC_AWD2TR_LT2_2

◆ ADC_TR2_LT2_3

#define ADC_TR2_LT2_3 ADC_AWD2TR_LT2_3

◆ ADC_TR2_LT2_4

#define ADC_TR2_LT2_4 ADC_AWD2TR_LT2_4

◆ ADC_TR2_LT2_5

#define ADC_TR2_LT2_5 ADC_AWD2TR_LT2_5

◆ ADC_TR2_LT2_6

#define ADC_TR2_LT2_6 ADC_AWD2TR_LT2_6

◆ ADC_TR2_LT2_7

#define ADC_TR2_LT2_7 ADC_AWD2TR_LT2_7

◆ ADC_TR2_LT2_8

#define ADC_TR2_LT2_8 ADC_AWD2TR_LT2_8

◆ ADC_TR2_LT2_9

#define ADC_TR2_LT2_9 ADC_AWD2TR_LT2_9

◆ ADC_TR3_HT3

#define ADC_TR3_HT3 ADC_AWD3TR_HT3

◆ ADC_TR3_HT3_0

#define ADC_TR3_HT3_0 ADC_AWD3TR_HT3_0

◆ ADC_TR3_HT3_1

#define ADC_TR3_HT3_1 ADC_AWD3TR_HT3_1

◆ ADC_TR3_HT3_10

#define ADC_TR3_HT3_10 ADC_AWD3TR_HT3_10

◆ ADC_TR3_HT3_11

#define ADC_TR3_HT3_11 ADC_AWD3TR_HT3_11

◆ ADC_TR3_HT3_2

#define ADC_TR3_HT3_2 ADC_AWD3TR_HT3_2

◆ ADC_TR3_HT3_3

#define ADC_TR3_HT3_3 ADC_AWD3TR_HT3_3

◆ ADC_TR3_HT3_4

#define ADC_TR3_HT3_4 ADC_AWD3TR_HT3_4

◆ ADC_TR3_HT3_5

#define ADC_TR3_HT3_5 ADC_AWD3TR_HT3_5

◆ ADC_TR3_HT3_6

#define ADC_TR3_HT3_6 ADC_AWD3TR_HT3_6

◆ ADC_TR3_HT3_7

#define ADC_TR3_HT3_7 ADC_AWD3TR_HT3_7

◆ ADC_TR3_HT3_8

#define ADC_TR3_HT3_8 ADC_AWD3TR_HT3_8

◆ ADC_TR3_HT3_9

#define ADC_TR3_HT3_9 ADC_AWD3TR_HT3_9

◆ ADC_TR3_LT3

#define ADC_TR3_LT3 ADC_AWD3TR_LT3

◆ ADC_TR3_LT3_0

#define ADC_TR3_LT3_0 ADC_AWD3TR_LT3_0

◆ ADC_TR3_LT3_1

#define ADC_TR3_LT3_1 ADC_AWD3TR_LT3_1

◆ ADC_TR3_LT3_10

#define ADC_TR3_LT3_10 ADC_AWD3TR_LT3_10

◆ ADC_TR3_LT3_11

#define ADC_TR3_LT3_11 ADC_AWD3TR_LT3_11

◆ ADC_TR3_LT3_2

#define ADC_TR3_LT3_2 ADC_AWD3TR_LT3_2

◆ ADC_TR3_LT3_3

#define ADC_TR3_LT3_3 ADC_AWD3TR_LT3_3

◆ ADC_TR3_LT3_4

#define ADC_TR3_LT3_4 ADC_AWD3TR_LT3_4

◆ ADC_TR3_LT3_5

#define ADC_TR3_LT3_5 ADC_AWD3TR_LT3_5

◆ ADC_TR3_LT3_6

#define ADC_TR3_LT3_6 ADC_AWD3TR_LT3_6

◆ ADC_TR3_LT3_7

#define ADC_TR3_LT3_7 ADC_AWD3TR_LT3_7

◆ ADC_TR3_LT3_8

#define ADC_TR3_LT3_8 ADC_AWD3TR_LT3_8

◆ ADC_TR3_LT3_9

#define ADC_TR3_LT3_9 ADC_AWD3TR_LT3_9

◆ CRC_CR_POLYSIZE

#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk

Polynomial size bits

◆ CRC_CR_POLYSIZE_0

#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos)

0x00000008

◆ CRC_CR_POLYSIZE_1

#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos)

0x00000010

◆ CRC_CR_POLYSIZE_Msk

#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos)

0x00000018

◆ CRC_CR_POLYSIZE_Pos

#define CRC_CR_POLYSIZE_Pos (3U)

◆ CRC_CR_RESET

#define CRC_CR_RESET CRC_CR_RESET_Msk

RESET the CRC computation unit bit

◆ CRC_CR_RESET_Msk

#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos)

0x00000001

◆ CRC_CR_RESET_Pos

#define CRC_CR_RESET_Pos (0U)

◆ CRC_CR_REV_IN

#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk

REV_IN Reverse Input Data bits

◆ CRC_CR_REV_IN_0

#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos)

0x00000020

◆ CRC_CR_REV_IN_1

#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos)

0x00000040

◆ CRC_CR_REV_IN_Msk

#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos)

0x00000060

◆ CRC_CR_REV_IN_Pos

#define CRC_CR_REV_IN_Pos (5U)

◆ CRC_CR_REV_OUT

#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk

REV_OUT Reverse Output Data bits

◆ CRC_CR_REV_OUT_Msk

#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos)

0x00000080

◆ CRC_CR_REV_OUT_Pos

#define CRC_CR_REV_OUT_Pos (7U)

◆ CRC_DR_DR

#define CRC_DR_DR CRC_DR_DR_Msk

Data register bits

◆ CRC_DR_DR_Msk

#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos)

0xFFFFFFFF

◆ CRC_DR_DR_Pos

#define CRC_DR_DR_Pos (0U)

◆ CRC_IDR_IDR

#define CRC_IDR_IDR CRC_IDR_IDR_Msk

General-purpose 32-bits data register bits

◆ CRC_IDR_IDR_Msk

#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)

0xFFFFFFFF

◆ CRC_IDR_IDR_Pos

#define CRC_IDR_IDR_Pos (0U)

◆ CRC_INIT_INIT

#define CRC_INIT_INIT CRC_INIT_INIT_Msk

Initial CRC value bits

◆ CRC_INIT_INIT_Msk

#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)

0xFFFFFFFF

◆ CRC_INIT_INIT_Pos

#define CRC_INIT_INIT_Pos (0U)

◆ CRC_POL_POL

#define CRC_POL_POL CRC_POL_POL_Msk

Coefficients of the polynomial

◆ CRC_POL_POL_Msk

#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos)

0xFFFFFFFF

◆ CRC_POL_POL_Pos

#define CRC_POL_POL_Pos (0U)

◆ DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP

#define DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Msk

◆ DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Msk

#define DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Pos)

0x00200000

◆ DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Pos

#define DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Pos (21U)

◆ DBG_APB_FZ1_DBG_IWDG_STOP

#define DBG_APB_FZ1_DBG_IWDG_STOP DBG_APB_FZ1_DBG_IWDG_STOP_Msk

◆ DBG_APB_FZ1_DBG_IWDG_STOP_Msk

#define DBG_APB_FZ1_DBG_IWDG_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_IWDG_STOP_Pos)

0x00001000

◆ DBG_APB_FZ1_DBG_IWDG_STOP_Pos

#define DBG_APB_FZ1_DBG_IWDG_STOP_Pos (12U)

◆ DBG_APB_FZ1_DBG_RTC_STOP

#define DBG_APB_FZ1_DBG_RTC_STOP DBG_APB_FZ1_DBG_RTC_STOP_Msk

◆ DBG_APB_FZ1_DBG_RTC_STOP_Msk

#define DBG_APB_FZ1_DBG_RTC_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_RTC_STOP_Pos)

0x00000400

◆ DBG_APB_FZ1_DBG_RTC_STOP_Pos

#define DBG_APB_FZ1_DBG_RTC_STOP_Pos (10U)

◆ DBG_APB_FZ1_DBG_TIM3_STOP

#define DBG_APB_FZ1_DBG_TIM3_STOP DBG_APB_FZ1_DBG_TIM3_STOP_Msk

◆ DBG_APB_FZ1_DBG_TIM3_STOP_Msk

#define DBG_APB_FZ1_DBG_TIM3_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_TIM3_STOP_Pos)

0x00000002

◆ DBG_APB_FZ1_DBG_TIM3_STOP_Pos

#define DBG_APB_FZ1_DBG_TIM3_STOP_Pos (1U)

◆ DBG_APB_FZ1_DBG_WWDG_STOP

#define DBG_APB_FZ1_DBG_WWDG_STOP DBG_APB_FZ1_DBG_WWDG_STOP_Msk

◆ DBG_APB_FZ1_DBG_WWDG_STOP_Msk

#define DBG_APB_FZ1_DBG_WWDG_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_WWDG_STOP_Pos)

0x00000800

◆ DBG_APB_FZ1_DBG_WWDG_STOP_Pos

#define DBG_APB_FZ1_DBG_WWDG_STOP_Pos (11U)

◆ DBG_APB_FZ2_DBG_TIM14_STOP

#define DBG_APB_FZ2_DBG_TIM14_STOP DBG_APB_FZ2_DBG_TIM14_STOP_Msk

◆ DBG_APB_FZ2_DBG_TIM14_STOP_Msk

#define DBG_APB_FZ2_DBG_TIM14_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM14_STOP_Pos)

0x00008000

◆ DBG_APB_FZ2_DBG_TIM14_STOP_Pos

#define DBG_APB_FZ2_DBG_TIM14_STOP_Pos (15U)

◆ DBG_APB_FZ2_DBG_TIM16_STOP

#define DBG_APB_FZ2_DBG_TIM16_STOP DBG_APB_FZ2_DBG_TIM16_STOP_Msk

◆ DBG_APB_FZ2_DBG_TIM16_STOP_Msk

#define DBG_APB_FZ2_DBG_TIM16_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM16_STOP_Pos)

0x00020000

◆ DBG_APB_FZ2_DBG_TIM16_STOP_Pos

#define DBG_APB_FZ2_DBG_TIM16_STOP_Pos (17U)

◆ DBG_APB_FZ2_DBG_TIM17_STOP

#define DBG_APB_FZ2_DBG_TIM17_STOP DBG_APB_FZ2_DBG_TIM17_STOP_Msk

◆ DBG_APB_FZ2_DBG_TIM17_STOP_Msk

#define DBG_APB_FZ2_DBG_TIM17_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM17_STOP_Pos)

0x00040000

◆ DBG_APB_FZ2_DBG_TIM17_STOP_Pos

#define DBG_APB_FZ2_DBG_TIM17_STOP_Pos (18U)

◆ DBG_APB_FZ2_DBG_TIM1_STOP

#define DBG_APB_FZ2_DBG_TIM1_STOP DBG_APB_FZ2_DBG_TIM1_STOP_Msk

◆ DBG_APB_FZ2_DBG_TIM1_STOP_Msk

#define DBG_APB_FZ2_DBG_TIM1_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM1_STOP_Pos)

0x00000800

◆ DBG_APB_FZ2_DBG_TIM1_STOP_Pos

#define DBG_APB_FZ2_DBG_TIM1_STOP_Pos (11U)

◆ DBG_CR_DBG_STANDBY

#define DBG_CR_DBG_STANDBY DBG_CR_DBG_STANDBY_Msk

◆ DBG_CR_DBG_STANDBY_Msk

#define DBG_CR_DBG_STANDBY_Msk (0x1UL << DBG_CR_DBG_STANDBY_Pos)

0x00000004

◆ DBG_CR_DBG_STANDBY_Pos

#define DBG_CR_DBG_STANDBY_Pos (2U)

◆ DBG_CR_DBG_STOP

#define DBG_CR_DBG_STOP DBG_CR_DBG_STOP_Msk

◆ DBG_CR_DBG_STOP_Msk

#define DBG_CR_DBG_STOP_Msk (0x1UL << DBG_CR_DBG_STOP_Pos)

0x00000002

◆ DBG_CR_DBG_STOP_Pos

#define DBG_CR_DBG_STOP_Pos (1U)

◆ DBG_IDCODE_DEV_ID

#define DBG_IDCODE_DEV_ID DBG_IDCODE_DEV_ID_Msk

◆ DBG_IDCODE_DEV_ID_Msk

#define DBG_IDCODE_DEV_ID_Msk (0xFFFUL << DBG_IDCODE_DEV_ID_Pos)

0x00000FFF

◆ DBG_IDCODE_DEV_ID_Pos

#define DBG_IDCODE_DEV_ID_Pos (0U)

◆ DBG_IDCODE_REV_ID

#define DBG_IDCODE_REV_ID DBG_IDCODE_REV_ID_Msk

◆ DBG_IDCODE_REV_ID_Msk

#define DBG_IDCODE_REV_ID_Msk (0xFFFFUL << DBG_IDCODE_REV_ID_Pos)

0xFFFF0000

◆ DBG_IDCODE_REV_ID_Pos

#define DBG_IDCODE_REV_ID_Pos (16U)

◆ DMA_CCR_CIRC

#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk

Circular mode

◆ DMA_CCR_CIRC_Msk

#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos)

0x00000020

◆ DMA_CCR_CIRC_Pos

#define DMA_CCR_CIRC_Pos (5U)

◆ DMA_CCR_DIR

#define DMA_CCR_DIR DMA_CCR_DIR_Msk

Data transfer direction

◆ DMA_CCR_DIR_Msk

#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos)

0x00000010

◆ DMA_CCR_DIR_Pos

#define DMA_CCR_DIR_Pos (4U)

◆ DMA_CCR_EN

#define DMA_CCR_EN DMA_CCR_EN_Msk

Channel enable

◆ DMA_CCR_EN_Msk

#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos)

0x00000001

◆ DMA_CCR_EN_Pos

#define DMA_CCR_EN_Pos (0U)

◆ DMA_CCR_HTIE

#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk

Half Transfer interrupt enable

◆ DMA_CCR_HTIE_Msk

#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos)

0x00000004

◆ DMA_CCR_HTIE_Pos

#define DMA_CCR_HTIE_Pos (2U)

◆ DMA_CCR_MEM2MEM

#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk

Memory to memory mode

◆ DMA_CCR_MEM2MEM_Msk

#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos)

0x00004000

◆ DMA_CCR_MEM2MEM_Pos

#define DMA_CCR_MEM2MEM_Pos (14U)

◆ DMA_CCR_MINC

#define DMA_CCR_MINC DMA_CCR_MINC_Msk

Memory increment mode

◆ DMA_CCR_MINC_Msk

#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos)

0x00000080

◆ DMA_CCR_MINC_Pos

#define DMA_CCR_MINC_Pos (7U)

◆ DMA_CCR_MSIZE

#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk

MSIZE[1:0] bits (Memory size)

◆ DMA_CCR_MSIZE_0

#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos)

0x00000400

◆ DMA_CCR_MSIZE_1

#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos)

0x00000800

◆ DMA_CCR_MSIZE_Msk

#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos)

0x00000C00

◆ DMA_CCR_MSIZE_Pos

#define DMA_CCR_MSIZE_Pos (10U)

◆ DMA_CCR_PINC

#define DMA_CCR_PINC DMA_CCR_PINC_Msk

Peripheral increment mode

◆ DMA_CCR_PINC_Msk

#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos)

0x00000040

◆ DMA_CCR_PINC_Pos

#define DMA_CCR_PINC_Pos (6U)

◆ DMA_CCR_PL

#define DMA_CCR_PL DMA_CCR_PL_Msk

PL[1:0] bits(Channel Priority level)

◆ DMA_CCR_PL_0

#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos)

0x00001000

◆ DMA_CCR_PL_1

#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos)

0x00002000

◆ DMA_CCR_PL_Msk

#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos)

0x00003000

◆ DMA_CCR_PL_Pos

#define DMA_CCR_PL_Pos (12U)

◆ DMA_CCR_PSIZE

#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk

PSIZE[1:0] bits (Peripheral size)

◆ DMA_CCR_PSIZE_0

#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos)

0x00000100

◆ DMA_CCR_PSIZE_1

#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos)

0x00000200

◆ DMA_CCR_PSIZE_Msk

#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos)

0x00000300

◆ DMA_CCR_PSIZE_Pos

#define DMA_CCR_PSIZE_Pos (8U)

◆ DMA_CCR_TCIE

#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk

Transfer complete interrupt enable

◆ DMA_CCR_TCIE_Msk

#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos)

0x00000002

◆ DMA_CCR_TCIE_Pos

#define DMA_CCR_TCIE_Pos (1U)

◆ DMA_CCR_TEIE

#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk

Transfer error interrupt enable

◆ DMA_CCR_TEIE_Msk

#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos)

0x00000008

◆ DMA_CCR_TEIE_Pos

#define DMA_CCR_TEIE_Pos (3U)

◆ DMA_CMAR_MA

#define DMA_CMAR_MA DMA_CMAR_MA_Msk

Memory Address

◆ DMA_CMAR_MA_Msk

#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)

0xFFFFFFFF

◆ DMA_CMAR_MA_Pos

#define DMA_CMAR_MA_Pos (0U)

◆ DMA_CNDTR_NDT

#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk

Number of data to Transfer

◆ DMA_CNDTR_NDT_Msk

#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos)

0x0000FFFF

◆ DMA_CNDTR_NDT_Pos

#define DMA_CNDTR_NDT_Pos (0U)

◆ DMA_CPAR_PA

#define DMA_CPAR_PA DMA_CPAR_PA_Msk

Peripheral Address

◆ DMA_CPAR_PA_Msk

#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)

0xFFFFFFFF

◆ DMA_CPAR_PA_Pos

#define DMA_CPAR_PA_Pos (0U)

◆ DMA_IFCR_CGIF1

#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk

Channel 1 Global interrupt clearr

◆ DMA_IFCR_CGIF1_Msk

#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos)

0x00000001

◆ DMA_IFCR_CGIF1_Pos

#define DMA_IFCR_CGIF1_Pos (0U)

◆ DMA_IFCR_CGIF2

#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk

Channel 2 Global interrupt clear

◆ DMA_IFCR_CGIF2_Msk

#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos)

0x00000010

◆ DMA_IFCR_CGIF2_Pos

#define DMA_IFCR_CGIF2_Pos (4U)

◆ DMA_IFCR_CGIF3

#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk

Channel 3 Global interrupt clear

◆ DMA_IFCR_CGIF3_Msk

#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos)

0x00000100

◆ DMA_IFCR_CGIF3_Pos

#define DMA_IFCR_CGIF3_Pos (8U)

◆ DMA_IFCR_CGIF4

#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk

Channel 4 Global interrupt clear

◆ DMA_IFCR_CGIF4_Msk

#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos)

0x00001000

◆ DMA_IFCR_CGIF4_Pos

#define DMA_IFCR_CGIF4_Pos (12U)

◆ DMA_IFCR_CGIF5

#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk

Channel 5 Global interrupt clear

◆ DMA_IFCR_CGIF5_Msk

#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos)

0x00010000

◆ DMA_IFCR_CGIF5_Pos

#define DMA_IFCR_CGIF5_Pos (16U)

◆ DMA_IFCR_CGIF6

#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk

Channel 6 Global interrupt clear

◆ DMA_IFCR_CGIF6_Msk

#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos)

0x00100000

◆ DMA_IFCR_CGIF6_Pos

#define DMA_IFCR_CGIF6_Pos (20U)

◆ DMA_IFCR_CGIF7

#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk

Channel 7 Global interrupt clear

◆ DMA_IFCR_CGIF7_Msk

#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos)

0x01000000

◆ DMA_IFCR_CGIF7_Pos

#define DMA_IFCR_CGIF7_Pos (24U)

◆ DMA_IFCR_CHTIF1

#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk

Channel 1 Half Transfer clear

◆ DMA_IFCR_CHTIF1_Msk

#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos)

0x00000004

◆ DMA_IFCR_CHTIF1_Pos

#define DMA_IFCR_CHTIF1_Pos (2U)

◆ DMA_IFCR_CHTIF2

#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk

Channel 2 Half Transfer clear

◆ DMA_IFCR_CHTIF2_Msk

#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos)

0x00000040

◆ DMA_IFCR_CHTIF2_Pos

#define DMA_IFCR_CHTIF2_Pos (6U)

◆ DMA_IFCR_CHTIF3

#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk

Channel 3 Half Transfer clear

◆ DMA_IFCR_CHTIF3_Msk

#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos)

0x00000400

◆ DMA_IFCR_CHTIF3_Pos

#define DMA_IFCR_CHTIF3_Pos (10U)

◆ DMA_IFCR_CHTIF4

#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk

Channel 4 Half Transfer clear

◆ DMA_IFCR_CHTIF4_Msk

#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos)

0x00004000

◆ DMA_IFCR_CHTIF4_Pos

#define DMA_IFCR_CHTIF4_Pos (14U)

◆ DMA_IFCR_CHTIF5

#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk

Channel 5 Half Transfer clear

◆ DMA_IFCR_CHTIF5_Msk

#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos)

0x00040000

◆ DMA_IFCR_CHTIF5_Pos

#define DMA_IFCR_CHTIF5_Pos (18U)

◆ DMA_IFCR_CHTIF6

#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk

Channel 6 Half Transfer clear

◆ DMA_IFCR_CHTIF6_Msk

#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos)

0x00400000

◆ DMA_IFCR_CHTIF6_Pos

#define DMA_IFCR_CHTIF6_Pos (22U)

◆ DMA_IFCR_CHTIF7

#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk

Channel 7 Half Transfer clear

◆ DMA_IFCR_CHTIF7_Msk

#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos)

0x04000000

◆ DMA_IFCR_CHTIF7_Pos

#define DMA_IFCR_CHTIF7_Pos (26U)

◆ DMA_IFCR_CTCIF1

#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk

Channel 1 Transfer Complete clear

◆ DMA_IFCR_CTCIF1_Msk

#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos)

0x00000002

◆ DMA_IFCR_CTCIF1_Pos

#define DMA_IFCR_CTCIF1_Pos (1U)

◆ DMA_IFCR_CTCIF2

#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk

Channel 2 Transfer Complete clear

◆ DMA_IFCR_CTCIF2_Msk

#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos)

0x00000020

◆ DMA_IFCR_CTCIF2_Pos

#define DMA_IFCR_CTCIF2_Pos (5U)

◆ DMA_IFCR_CTCIF3

#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk

Channel 3 Transfer Complete clear

◆ DMA_IFCR_CTCIF3_Msk

#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos)

0x00000200

◆ DMA_IFCR_CTCIF3_Pos

#define DMA_IFCR_CTCIF3_Pos (9U)

◆ DMA_IFCR_CTCIF4

#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk

Channel 4 Transfer Complete clear

◆ DMA_IFCR_CTCIF4_Msk

#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos)

0x00002000

◆ DMA_IFCR_CTCIF4_Pos

#define DMA_IFCR_CTCIF4_Pos (13U)

◆ DMA_IFCR_CTCIF5

#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk

Channel 5 Transfer Complete clear

◆ DMA_IFCR_CTCIF5_Msk

#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos)

0x00020000

◆ DMA_IFCR_CTCIF5_Pos

#define DMA_IFCR_CTCIF5_Pos (17U)

◆ DMA_IFCR_CTCIF6

#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk

Channel 6 Transfer Complete clear

◆ DMA_IFCR_CTCIF6_Msk

#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos)

0x00200000

◆ DMA_IFCR_CTCIF6_Pos

#define DMA_IFCR_CTCIF6_Pos (21U)

◆ DMA_IFCR_CTCIF7

#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk

Channel 7 Transfer Complete clear

◆ DMA_IFCR_CTCIF7_Msk

#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos)

0x02000000

◆ DMA_IFCR_CTCIF7_Pos

#define DMA_IFCR_CTCIF7_Pos (25U)

◆ DMA_IFCR_CTEIF1

#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk

Channel 1 Transfer Error clear

◆ DMA_IFCR_CTEIF1_Msk

#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos)

0x00000008

◆ DMA_IFCR_CTEIF1_Pos

#define DMA_IFCR_CTEIF1_Pos (3U)

◆ DMA_IFCR_CTEIF2

#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk

Channel 2 Transfer Error clear

◆ DMA_IFCR_CTEIF2_Msk

#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos)

0x00000080

◆ DMA_IFCR_CTEIF2_Pos

#define DMA_IFCR_CTEIF2_Pos (7U)

◆ DMA_IFCR_CTEIF3

#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk

Channel 3 Transfer Error clear

◆ DMA_IFCR_CTEIF3_Msk

#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos)

0x00000800

◆ DMA_IFCR_CTEIF3_Pos

#define DMA_IFCR_CTEIF3_Pos (11U)

◆ DMA_IFCR_CTEIF4

#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk

Channel 4 Transfer Error clear

◆ DMA_IFCR_CTEIF4_Msk

#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos)

0x00008000

◆ DMA_IFCR_CTEIF4_Pos

#define DMA_IFCR_CTEIF4_Pos (15U)

◆ DMA_IFCR_CTEIF5

#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk

Channel 5 Transfer Error clear

◆ DMA_IFCR_CTEIF5_Msk

#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos)

0x00080000

◆ DMA_IFCR_CTEIF5_Pos

#define DMA_IFCR_CTEIF5_Pos (19U)

◆ DMA_IFCR_CTEIF6

#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk

Channel 6 Transfer Error clear

◆ DMA_IFCR_CTEIF6_Msk

#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos)

0x00800000

◆ DMA_IFCR_CTEIF6_Pos

#define DMA_IFCR_CTEIF6_Pos (23U)

◆ DMA_IFCR_CTEIF7

#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk

Channel 7 Transfer Error clear

◆ DMA_IFCR_CTEIF7_Msk

#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos)

0x08000000

◆ DMA_IFCR_CTEIF7_Pos

#define DMA_IFCR_CTEIF7_Pos (27U)

◆ DMA_ISR_GIF1

#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk

Channel 1 Global interrupt flag

◆ DMA_ISR_GIF1_Msk

#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos)

0x00000001

◆ DMA_ISR_GIF1_Pos

#define DMA_ISR_GIF1_Pos (0U)

◆ DMA_ISR_GIF2

#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk

Channel 2 Global interrupt flag

◆ DMA_ISR_GIF2_Msk

#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos)

0x00000010

◆ DMA_ISR_GIF2_Pos

#define DMA_ISR_GIF2_Pos (4U)

◆ DMA_ISR_GIF3

#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk

Channel 3 Global interrupt flag

◆ DMA_ISR_GIF3_Msk

#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos)

0x00000100

◆ DMA_ISR_GIF3_Pos

#define DMA_ISR_GIF3_Pos (8U)

◆ DMA_ISR_GIF4

#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk

Channel 4 Global interrupt flag

◆ DMA_ISR_GIF4_Msk

#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos)

0x00001000

◆ DMA_ISR_GIF4_Pos

#define DMA_ISR_GIF4_Pos (12U)

◆ DMA_ISR_GIF5

#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk

Channel 5 Global interrupt flag

◆ DMA_ISR_GIF5_Msk

#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos)

0x00010000

◆ DMA_ISR_GIF5_Pos

#define DMA_ISR_GIF5_Pos (16U)

◆ DMA_ISR_GIF6

#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk

Channel 6 Global interrupt flag

◆ DMA_ISR_GIF6_Msk

#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos)

0x00100000

◆ DMA_ISR_GIF6_Pos

#define DMA_ISR_GIF6_Pos (20U)

◆ DMA_ISR_GIF7

#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk

Channel 7 Global interrupt flag

◆ DMA_ISR_GIF7_Msk

#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos)

0x01000000

◆ DMA_ISR_GIF7_Pos

#define DMA_ISR_GIF7_Pos (24U)

◆ DMA_ISR_HTIF1

#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk

Channel 1 Half Transfer flag

◆ DMA_ISR_HTIF1_Msk

#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos)

0x00000004

◆ DMA_ISR_HTIF1_Pos

#define DMA_ISR_HTIF1_Pos (2U)

◆ DMA_ISR_HTIF2

#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk

Channel 2 Half Transfer flag

◆ DMA_ISR_HTIF2_Msk

#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos)

0x00000040

◆ DMA_ISR_HTIF2_Pos

#define DMA_ISR_HTIF2_Pos (6U)

◆ DMA_ISR_HTIF3

#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk

Channel 3 Half Transfer flag

◆ DMA_ISR_HTIF3_Msk

#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos)

0x00000400

◆ DMA_ISR_HTIF3_Pos

#define DMA_ISR_HTIF3_Pos (10U)

◆ DMA_ISR_HTIF4

#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk

Channel 4 Half Transfer flag

◆ DMA_ISR_HTIF4_Msk

#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos)

0x00004000

◆ DMA_ISR_HTIF4_Pos

#define DMA_ISR_HTIF4_Pos (14U)

◆ DMA_ISR_HTIF5

#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk

Channel 5 Half Transfer flag

◆ DMA_ISR_HTIF5_Msk

#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos)

0x00040000

◆ DMA_ISR_HTIF5_Pos

#define DMA_ISR_HTIF5_Pos (18U)

◆ DMA_ISR_HTIF6

#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk

Channel 6 Half Transfer flag

◆ DMA_ISR_HTIF6_Msk

#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos)

0x00400000

◆ DMA_ISR_HTIF6_Pos

#define DMA_ISR_HTIF6_Pos (22U)

◆ DMA_ISR_HTIF7

#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk

Channel 7 Half Transfer flag

◆ DMA_ISR_HTIF7_Msk

#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos)

0x04000000

◆ DMA_ISR_HTIF7_Pos

#define DMA_ISR_HTIF7_Pos (26U)

◆ DMA_ISR_TCIF1

#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk

Channel 1 Transfer Complete flag

◆ DMA_ISR_TCIF1_Msk

#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos)

0x00000002

◆ DMA_ISR_TCIF1_Pos

#define DMA_ISR_TCIF1_Pos (1U)

◆ DMA_ISR_TCIF2

#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk

Channel 2 Transfer Complete flag

◆ DMA_ISR_TCIF2_Msk

#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos)

0x00000020

◆ DMA_ISR_TCIF2_Pos

#define DMA_ISR_TCIF2_Pos (5U)

◆ DMA_ISR_TCIF3

#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk

Channel 3 Transfer Complete flag

◆ DMA_ISR_TCIF3_Msk

#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos)

0x00000200

◆ DMA_ISR_TCIF3_Pos

#define DMA_ISR_TCIF3_Pos (9U)

◆ DMA_ISR_TCIF4

#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk

Channel 4 Transfer Complete flag

◆ DMA_ISR_TCIF4_Msk

#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos)

0x00002000

◆ DMA_ISR_TCIF4_Pos

#define DMA_ISR_TCIF4_Pos (13U)

◆ DMA_ISR_TCIF5

#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk

Channel 5 Transfer Complete flag

◆ DMA_ISR_TCIF5_Msk

#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos)

0x00020000

◆ DMA_ISR_TCIF5_Pos

#define DMA_ISR_TCIF5_Pos (17U)

◆ DMA_ISR_TCIF6

#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk

Channel 6 Transfer Complete flag

◆ DMA_ISR_TCIF6_Msk

#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos)

0x00200000

◆ DMA_ISR_TCIF6_Pos

#define DMA_ISR_TCIF6_Pos (21U)

◆ DMA_ISR_TCIF7

#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk

Channel 7 Transfer Complete flag

◆ DMA_ISR_TCIF7_Msk

#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos)

0x02000000

◆ DMA_ISR_TCIF7_Pos

#define DMA_ISR_TCIF7_Pos (25U)

◆ DMA_ISR_TEIF1

#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk

Channel 1 Transfer Error flag

◆ DMA_ISR_TEIF1_Msk

#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos)

0x00000008

◆ DMA_ISR_TEIF1_Pos

#define DMA_ISR_TEIF1_Pos (3U)

◆ DMA_ISR_TEIF2

#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk

Channel 2 Transfer Error flag

◆ DMA_ISR_TEIF2_Msk

#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos)

0x00000080

◆ DMA_ISR_TEIF2_Pos

#define DMA_ISR_TEIF2_Pos (7U)

◆ DMA_ISR_TEIF3

#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk

Channel 3 Transfer Error flag

◆ DMA_ISR_TEIF3_Msk

#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos)

0x00000800

◆ DMA_ISR_TEIF3_Pos

#define DMA_ISR_TEIF3_Pos (11U)

◆ DMA_ISR_TEIF4

#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk

Channel 4 Transfer Error flag

◆ DMA_ISR_TEIF4_Msk

#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos)

0x00008000

◆ DMA_ISR_TEIF4_Pos

#define DMA_ISR_TEIF4_Pos (15U)

◆ DMA_ISR_TEIF5

#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk

Channel 5 Transfer Error flag

◆ DMA_ISR_TEIF5_Msk

#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos)

0x00080000

◆ DMA_ISR_TEIF5_Pos

#define DMA_ISR_TEIF5_Pos (19U)

◆ DMA_ISR_TEIF6

#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk

Channel 6 Transfer Error flag

◆ DMA_ISR_TEIF6_Msk

#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos)

0x00800000

◆ DMA_ISR_TEIF6_Pos

#define DMA_ISR_TEIF6_Pos (23U)

◆ DMA_ISR_TEIF7

#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk

Channel 7 Transfer Error flag

◆ DMA_ISR_TEIF7_Msk

#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos)

0x08000000

◆ DMA_ISR_TEIF7_Pos

#define DMA_ISR_TEIF7_Pos (27U)

◆ DMAMUX_CFR_CSOF0

#define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk

Clear Overrun Flag 0

◆ DMAMUX_CFR_CSOF0_Msk

#define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos)

0x00000001

◆ DMAMUX_CFR_CSOF0_Pos

#define DMAMUX_CFR_CSOF0_Pos (0U)

◆ DMAMUX_CFR_CSOF1

#define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk

Clear Overrun Flag 1

◆ DMAMUX_CFR_CSOF1_Msk

#define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos)

0x00000002

◆ DMAMUX_CFR_CSOF1_Pos

#define DMAMUX_CFR_CSOF1_Pos (1U)

◆ DMAMUX_CFR_CSOF2

#define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk

Clear Overrun Flag 2

◆ DMAMUX_CFR_CSOF2_Msk

#define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos)

0x00000004

◆ DMAMUX_CFR_CSOF2_Pos

#define DMAMUX_CFR_CSOF2_Pos (2U)

◆ DMAMUX_CFR_CSOF3

#define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk

Clear Overrun Flag 3

◆ DMAMUX_CFR_CSOF3_Msk

#define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos)

0x00000008

◆ DMAMUX_CFR_CSOF3_Pos

#define DMAMUX_CFR_CSOF3_Pos (3U)

◆ DMAMUX_CFR_CSOF4

#define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk

Clear Overrun Flag 4

◆ DMAMUX_CFR_CSOF4_Msk

#define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos)

0x00000010

◆ DMAMUX_CFR_CSOF4_Pos

#define DMAMUX_CFR_CSOF4_Pos (4U)

◆ DMAMUX_CFR_CSOF5

#define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk

Clear Overrun Flag 5

◆ DMAMUX_CFR_CSOF5_Msk

#define DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos)

0x00000020

◆ DMAMUX_CFR_CSOF5_Pos

#define DMAMUX_CFR_CSOF5_Pos (5U)

◆ DMAMUX_CFR_CSOF6

#define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk

Clear Overrun Flag 6

◆ DMAMUX_CFR_CSOF6_Msk

#define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos)

0x00000040

◆ DMAMUX_CFR_CSOF6_Pos

#define DMAMUX_CFR_CSOF6_Pos (6U)

◆ DMAMUX_CSR_SOF0

#define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk

Synchronization Overrun Flag 0

◆ DMAMUX_CSR_SOF0_Msk

#define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos)

0x00000001

◆ DMAMUX_CSR_SOF0_Pos

#define DMAMUX_CSR_SOF0_Pos (0U)

◆ DMAMUX_CSR_SOF1

#define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk

Synchronization Overrun Flag 1

◆ DMAMUX_CSR_SOF1_Msk

#define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos)

0x00000002

◆ DMAMUX_CSR_SOF1_Pos

#define DMAMUX_CSR_SOF1_Pos (1U)

◆ DMAMUX_CSR_SOF2

#define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk

Synchronization Overrun Flag 2

◆ DMAMUX_CSR_SOF2_Msk

#define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos)

0x00000004

◆ DMAMUX_CSR_SOF2_Pos

#define DMAMUX_CSR_SOF2_Pos (2U)

◆ DMAMUX_CSR_SOF3

#define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk

Synchronization Overrun Flag 3

◆ DMAMUX_CSR_SOF3_Msk

#define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos)

0x00000008

◆ DMAMUX_CSR_SOF3_Pos

#define DMAMUX_CSR_SOF3_Pos (3U)

◆ DMAMUX_CSR_SOF4

#define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk

Synchronization Overrun Flag 4

◆ DMAMUX_CSR_SOF4_Msk

#define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos)

0x00000010

◆ DMAMUX_CSR_SOF4_Pos

#define DMAMUX_CSR_SOF4_Pos (4U)

◆ DMAMUX_CSR_SOF5

#define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk

Synchronization Overrun Flag 5

◆ DMAMUX_CSR_SOF5_Msk

#define DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos)

0x00000020

◆ DMAMUX_CSR_SOF5_Pos

#define DMAMUX_CSR_SOF5_Pos (5U)

◆ DMAMUX_CSR_SOF6

#define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk

Synchronization Overrun Flag 6

◆ DMAMUX_CSR_SOF6_Msk

#define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos)

0x00000040

◆ DMAMUX_CSR_SOF6_Pos

#define DMAMUX_CSR_SOF6_Pos (6U)

◆ DMAMUX_CxCR_DMAREQ_ID

#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk

DMA Request ID

◆ DMAMUX_CxCR_DMAREQ_ID_0

#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)

0x00000001

◆ DMAMUX_CxCR_DMAREQ_ID_1

#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)

0x00000002

◆ DMAMUX_CxCR_DMAREQ_ID_2

#define DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)

0x00000004

◆ DMAMUX_CxCR_DMAREQ_ID_3

#define DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)

0x00000008

◆ DMAMUX_CxCR_DMAREQ_ID_4

#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)

0x00000010

◆ DMAMUX_CxCR_DMAREQ_ID_5

#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)

0x00000020

◆ DMAMUX_CxCR_DMAREQ_ID_6

#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)

0x00000040

◆ DMAMUX_CxCR_DMAREQ_ID_Msk

#define DMAMUX_CxCR_DMAREQ_ID_Msk (0x3FUL << DMAMUX_CxCR_DMAREQ_ID_Pos)

0x0000003F

◆ DMAMUX_CxCR_DMAREQ_ID_Pos

#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)

◆ DMAMUX_CxCR_EGE

#define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk

Event generation interrupt enable

◆ DMAMUX_CxCR_EGE_Msk

#define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos)

0x00000200

◆ DMAMUX_CxCR_EGE_Pos

#define DMAMUX_CxCR_EGE_Pos (9U)

◆ DMAMUX_CxCR_NBREQ

#define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk

Number of request

◆ DMAMUX_CxCR_NBREQ_0

#define DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos)

0x00080000

◆ DMAMUX_CxCR_NBREQ_1

#define DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos)

0x00100000

◆ DMAMUX_CxCR_NBREQ_2

#define DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos)

0x00200000

◆ DMAMUX_CxCR_NBREQ_3

#define DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos)

0x00400000

◆ DMAMUX_CxCR_NBREQ_4

#define DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos)

0x00800000

◆ DMAMUX_CxCR_NBREQ_Msk

#define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)

0x00F80000

◆ DMAMUX_CxCR_NBREQ_Pos

#define DMAMUX_CxCR_NBREQ_Pos (19U)

◆ DMAMUX_CxCR_SE

#define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk

Synchronization enable

◆ DMAMUX_CxCR_SE_Msk

#define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos)

0x00010000

◆ DMAMUX_CxCR_SE_Pos

#define DMAMUX_CxCR_SE_Pos (16U)

◆ DMAMUX_CxCR_SOIE

#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk

Synchro overrun interrupt enable

◆ DMAMUX_CxCR_SOIE_Msk

#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos)

0x00000100

◆ DMAMUX_CxCR_SOIE_Pos

#define DMAMUX_CxCR_SOIE_Pos (8U)

◆ DMAMUX_CxCR_SPOL

#define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk

Synchronization polarity

◆ DMAMUX_CxCR_SPOL_0

#define DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos)

0x00020000

◆ DMAMUX_CxCR_SPOL_1

#define DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos)

0x00040000

◆ DMAMUX_CxCR_SPOL_Msk

#define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos)

0x00060000

◆ DMAMUX_CxCR_SPOL_Pos

#define DMAMUX_CxCR_SPOL_Pos (17U)

◆ DMAMUX_CxCR_SYNC_ID

#define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk

Synchronization ID

◆ DMAMUX_CxCR_SYNC_ID_0

#define DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)

0x01000000

◆ DMAMUX_CxCR_SYNC_ID_1

#define DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)

0x02000000

◆ DMAMUX_CxCR_SYNC_ID_2

#define DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)

0x04000000

◆ DMAMUX_CxCR_SYNC_ID_3

#define DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)

0x08000000

◆ DMAMUX_CxCR_SYNC_ID_4

#define DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)

0x10000000

◆ DMAMUX_CxCR_SYNC_ID_Msk

#define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)

0x1F000000

◆ DMAMUX_CxCR_SYNC_ID_Pos

#define DMAMUX_CxCR_SYNC_ID_Pos (24U)

◆ DMAMUX_RGCFR_COF0

#define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk

Clear Overrun flag 0

◆ DMAMUX_RGCFR_COF0_Msk

#define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos)

0x00000001

◆ DMAMUX_RGCFR_COF0_Pos

#define DMAMUX_RGCFR_COF0_Pos (0U)

◆ DMAMUX_RGCFR_COF1

#define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk

Clear Overrun flag 1

◆ DMAMUX_RGCFR_COF1_Msk

#define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos)

0x00000002

◆ DMAMUX_RGCFR_COF1_Pos

#define DMAMUX_RGCFR_COF1_Pos (1U)

◆ DMAMUX_RGCFR_COF2

#define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk

Clear Overrun flag 2

◆ DMAMUX_RGCFR_COF2_Msk

#define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos)

0x00000004

◆ DMAMUX_RGCFR_COF2_Pos

#define DMAMUX_RGCFR_COF2_Pos (2U)

◆ DMAMUX_RGCFR_COF3

#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk

Clear Overrun flag 3

◆ DMAMUX_RGCFR_COF3_Msk

#define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos)

0x00000008

◆ DMAMUX_RGCFR_COF3_Pos

#define DMAMUX_RGCFR_COF3_Pos (3U)

◆ DMAMUX_RGSR_OF0

#define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk

Overrun flag 0

◆ DMAMUX_RGSR_OF0_Msk

#define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos)

0x00000001

◆ DMAMUX_RGSR_OF0_Pos

#define DMAMUX_RGSR_OF0_Pos (0U)

◆ DMAMUX_RGSR_OF1

#define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk

Overrun flag 1

◆ DMAMUX_RGSR_OF1_Msk

#define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos)

0x00000002

◆ DMAMUX_RGSR_OF1_Pos

#define DMAMUX_RGSR_OF1_Pos (1U)

◆ DMAMUX_RGSR_OF2

#define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk

Overrun flag 2

◆ DMAMUX_RGSR_OF2_Msk

#define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos)

0x00000004

◆ DMAMUX_RGSR_OF2_Pos

#define DMAMUX_RGSR_OF2_Pos (2U)

◆ DMAMUX_RGSR_OF3

#define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk

Overrun flag 3

◆ DMAMUX_RGSR_OF3_Msk

#define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos)

0x00000008

◆ DMAMUX_RGSR_OF3_Pos

#define DMAMUX_RGSR_OF3_Pos (3U)

◆ DMAMUX_RGxCR_GE

#define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk

Generation enable

◆ DMAMUX_RGxCR_GE_Msk

#define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos)

0x00010000

◆ DMAMUX_RGxCR_GE_Pos

#define DMAMUX_RGxCR_GE_Pos (16U)

◆ DMAMUX_RGxCR_GNBREQ

#define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk

Number of request

◆ DMAMUX_RGxCR_GNBREQ_0

#define DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)

0x00080000

◆ DMAMUX_RGxCR_GNBREQ_1

#define DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)

0x00100000

◆ DMAMUX_RGxCR_GNBREQ_2

#define DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)

0x00200000

◆ DMAMUX_RGxCR_GNBREQ_3

#define DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)

0x00400000

◆ DMAMUX_RGxCR_GNBREQ_4

#define DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)

0x00800000

◆ DMAMUX_RGxCR_GNBREQ_Msk

#define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)

0x00F80000

◆ DMAMUX_RGxCR_GNBREQ_Pos

#define DMAMUX_RGxCR_GNBREQ_Pos (19U)

◆ DMAMUX_RGxCR_GPOL

#define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk

Generation polarity

◆ DMAMUX_RGxCR_GPOL_0

#define DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos)

0x00020000

◆ DMAMUX_RGxCR_GPOL_1

#define DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos)

0x00040000

◆ DMAMUX_RGxCR_GPOL_Msk

#define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos)

0x00060000

◆ DMAMUX_RGxCR_GPOL_Pos

#define DMAMUX_RGxCR_GPOL_Pos (17U)

◆ DMAMUX_RGxCR_OIE

#define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk

Overrun interrupt enable

◆ DMAMUX_RGxCR_OIE_Msk

#define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos)

0x00000100

◆ DMAMUX_RGxCR_OIE_Pos

#define DMAMUX_RGxCR_OIE_Pos (8U)

◆ DMAMUX_RGxCR_SIG_ID

#define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk

Signal ID

◆ DMAMUX_RGxCR_SIG_ID_0

#define DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)

0x00000001

◆ DMAMUX_RGxCR_SIG_ID_1

#define DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)

0x00000002

◆ DMAMUX_RGxCR_SIG_ID_2

#define DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)

0x00000004

◆ DMAMUX_RGxCR_SIG_ID_3

#define DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)

0x00000008

◆ DMAMUX_RGxCR_SIG_ID_4

#define DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)

0x00000010

◆ DMAMUX_RGxCR_SIG_ID_Msk

#define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)

0x0000001F

◆ DMAMUX_RGxCR_SIG_ID_Pos

#define DMAMUX_RGxCR_SIG_ID_Pos (0U)

◆ EXTI_EMR1_EM0

#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk

Event Mask on line 0

◆ EXTI_EMR1_EM0_Msk

#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos)

0x00000001

◆ EXTI_EMR1_EM0_Pos

#define EXTI_EMR1_EM0_Pos (0U)

◆ EXTI_EMR1_EM1

#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk

Event Mask on line 1

◆ EXTI_EMR1_EM10

#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk

Event Mask on line 10

◆ EXTI_EMR1_EM10_Msk

#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos)

0x00000400

◆ EXTI_EMR1_EM10_Pos

#define EXTI_EMR1_EM10_Pos (10U)

◆ EXTI_EMR1_EM11

#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk

Event Mask on line 11

◆ EXTI_EMR1_EM11_Msk

#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos)

0x00000800

◆ EXTI_EMR1_EM11_Pos

#define EXTI_EMR1_EM11_Pos (11U)

◆ EXTI_EMR1_EM12

#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk

Event Mask on line 12

◆ EXTI_EMR1_EM12_Msk

#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos)

0x00001000

◆ EXTI_EMR1_EM12_Pos

#define EXTI_EMR1_EM12_Pos (12U)

◆ EXTI_EMR1_EM13

#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk

Event Mask on line 13

◆ EXTI_EMR1_EM13_Msk

#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos)

0x00002000

◆ EXTI_EMR1_EM13_Pos

#define EXTI_EMR1_EM13_Pos (13U)

◆ EXTI_EMR1_EM14

#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk

Event Mask on line 14

◆ EXTI_EMR1_EM14_Msk

#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos)

0x00004000

◆ EXTI_EMR1_EM14_Pos

#define EXTI_EMR1_EM14_Pos (14U)

◆ EXTI_EMR1_EM15

#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk

Event Mask on line 15

◆ EXTI_EMR1_EM15_Msk

#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos)

0x00008000

◆ EXTI_EMR1_EM15_Pos

#define EXTI_EMR1_EM15_Pos (15U)

◆ EXTI_EMR1_EM19

#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk

Event Mask on line 19

◆ EXTI_EMR1_EM19_Msk

#define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos)

0x00080000

◆ EXTI_EMR1_EM19_Pos

#define EXTI_EMR1_EM19_Pos (19U)

◆ EXTI_EMR1_EM1_Msk

#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos)

0x00000002

◆ EXTI_EMR1_EM1_Pos

#define EXTI_EMR1_EM1_Pos (1U)

◆ EXTI_EMR1_EM2

#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk

Event Mask on line 2

◆ EXTI_EMR1_EM21

#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk

Event Mask on line 21

◆ EXTI_EMR1_EM21_Msk

#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos)

0x00200000

◆ EXTI_EMR1_EM21_Pos

#define EXTI_EMR1_EM21_Pos (21U)

◆ EXTI_EMR1_EM23

#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk

Event Mask on line 23

◆ EXTI_EMR1_EM23_Msk

#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos)

0x00800000

◆ EXTI_EMR1_EM23_Pos

#define EXTI_EMR1_EM23_Pos (23U)

◆ EXTI_EMR1_EM25

#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk

Event Mask on line 25

◆ EXTI_EMR1_EM25_Msk

#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos)

0x02000000

◆ EXTI_EMR1_EM25_Pos

#define EXTI_EMR1_EM25_Pos (25U)

◆ EXTI_EMR1_EM2_Msk

#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos)

0x00000004

◆ EXTI_EMR1_EM2_Pos

#define EXTI_EMR1_EM2_Pos (2U)

◆ EXTI_EMR1_EM3

#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk

Event Mask on line 3

◆ EXTI_EMR1_EM31

#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk

Event Mask on line 31

◆ EXTI_EMR1_EM31_Msk

#define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos)

0x80000000

◆ EXTI_EMR1_EM31_Pos

#define EXTI_EMR1_EM31_Pos (31U)

◆ EXTI_EMR1_EM3_Msk

#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos)

0x00000008

◆ EXTI_EMR1_EM3_Pos

#define EXTI_EMR1_EM3_Pos (3U)

◆ EXTI_EMR1_EM4

#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk

Event Mask on line 4

◆ EXTI_EMR1_EM4_Msk

#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos)

0x00000010

◆ EXTI_EMR1_EM4_Pos

#define EXTI_EMR1_EM4_Pos (4U)

◆ EXTI_EMR1_EM5

#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk

Event Mask on line 5

◆ EXTI_EMR1_EM5_Msk

#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos)

0x00000020

◆ EXTI_EMR1_EM5_Pos

#define EXTI_EMR1_EM5_Pos (5U)

◆ EXTI_EMR1_EM6

#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk

Event Mask on line 6

◆ EXTI_EMR1_EM6_Msk

#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos)

0x00000040

◆ EXTI_EMR1_EM6_Pos

#define EXTI_EMR1_EM6_Pos (6U)

◆ EXTI_EMR1_EM7

#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk

Event Mask on line 7

◆ EXTI_EMR1_EM7_Msk

#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos)

0x00000080

◆ EXTI_EMR1_EM7_Pos

#define EXTI_EMR1_EM7_Pos (7U)

◆ EXTI_EMR1_EM8

#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk

Event Mask on line 8

◆ EXTI_EMR1_EM8_Msk

#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos)

0x00000100

◆ EXTI_EMR1_EM8_Pos

#define EXTI_EMR1_EM8_Pos (8U)

◆ EXTI_EMR1_EM9

#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk

Event Mask on line 9

◆ EXTI_EMR1_EM9_Msk

#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos)

0x00000200

◆ EXTI_EMR1_EM9_Pos

#define EXTI_EMR1_EM9_Pos (9U)

◆ EXTI_EXTICR1_EXTI0

#define EXTI_EXTICR1_EXTI0 EXTI_EXTICR1_EXTI0_Msk

EXTI 0 configuration

◆ EXTI_EXTICR1_EXTI0_0

#define EXTI_EXTICR1_EXTI0_0 (0x1UL << EXTI_EXTICR1_EXTI0_Pos)

0x00000001

◆ EXTI_EXTICR1_EXTI0_1

#define EXTI_EXTICR1_EXTI0_1 (0x2UL << EXTI_EXTICR1_EXTI0_Pos)

0x00000002

◆ EXTI_EXTICR1_EXTI0_2

#define EXTI_EXTICR1_EXTI0_2 (0x4UL << EXTI_EXTICR1_EXTI0_Pos)

0x00000004

◆ EXTI_EXTICR1_EXTI0_Msk

#define EXTI_EXTICR1_EXTI0_Msk (0x7UL << EXTI_EXTICR1_EXTI0_Pos)

0x00000007

◆ EXTI_EXTICR1_EXTI0_Pos

#define EXTI_EXTICR1_EXTI0_Pos (0U)

◆ EXTI_EXTICR1_EXTI1

#define EXTI_EXTICR1_EXTI1 EXTI_EXTICR1_EXTI1_Msk

EXTI 1 configuration

◆ EXTI_EXTICR1_EXTI1_0

#define EXTI_EXTICR1_EXTI1_0 (0x1UL << EXTI_EXTICR1_EXTI1_Pos)

0x00000100

◆ EXTI_EXTICR1_EXTI1_1

#define EXTI_EXTICR1_EXTI1_1 (0x2UL << EXTI_EXTICR1_EXTI1_Pos)

0x00000200

◆ EXTI_EXTICR1_EXTI1_2

#define EXTI_EXTICR1_EXTI1_2 (0x4UL << EXTI_EXTICR1_EXTI1_Pos)

0x00000400

◆ EXTI_EXTICR1_EXTI1_Msk

#define EXTI_EXTICR1_EXTI1_Msk (0x7UL << EXTI_EXTICR1_EXTI1_Pos)

0x00000700

◆ EXTI_EXTICR1_EXTI1_Pos

#define EXTI_EXTICR1_EXTI1_Pos (8U)

◆ EXTI_EXTICR1_EXTI2

#define EXTI_EXTICR1_EXTI2 EXTI_EXTICR1_EXTI2_Msk

EXTI 2 configuration

◆ EXTI_EXTICR1_EXTI2_0

#define EXTI_EXTICR1_EXTI2_0 (0x1UL << EXTI_EXTICR1_EXTI2_Pos)

0x00010000

◆ EXTI_EXTICR1_EXTI2_1

#define EXTI_EXTICR1_EXTI2_1 (0x2UL << EXTI_EXTICR1_EXTI2_Pos)

0x00020000

◆ EXTI_EXTICR1_EXTI2_2

#define EXTI_EXTICR1_EXTI2_2 (0x4UL << EXTI_EXTICR1_EXTI2_Pos)

0x00040000

◆ EXTI_EXTICR1_EXTI2_Msk

#define EXTI_EXTICR1_EXTI2_Msk (0x7UL << EXTI_EXTICR1_EXTI2_Pos)

0x00070000

◆ EXTI_EXTICR1_EXTI2_Pos

#define EXTI_EXTICR1_EXTI2_Pos (16U)

◆ EXTI_EXTICR1_EXTI3

#define EXTI_EXTICR1_EXTI3 EXTI_EXTICR1_EXTI3_Msk

EXTI 3 configuration

◆ EXTI_EXTICR1_EXTI3_0

#define EXTI_EXTICR1_EXTI3_0 (0x1UL << EXTI_EXTICR1_EXTI3_Pos)

0x01000000

◆ EXTI_EXTICR1_EXTI3_1

#define EXTI_EXTICR1_EXTI3_1 (0x2UL << EXTI_EXTICR1_EXTI3_Pos)

0x02000000

◆ EXTI_EXTICR1_EXTI3_2

#define EXTI_EXTICR1_EXTI3_2 (0x4UL << EXTI_EXTICR1_EXTI3_Pos)

0x04000000

◆ EXTI_EXTICR1_EXTI3_Msk

#define EXTI_EXTICR1_EXTI3_Msk (0x7UL << EXTI_EXTICR1_EXTI3_Pos)

0x07000000

◆ EXTI_EXTICR1_EXTI3_Pos

#define EXTI_EXTICR1_EXTI3_Pos (24U)

◆ EXTI_EXTICR2_EXTI4

#define EXTI_EXTICR2_EXTI4 EXTI_EXTICR2_EXTI4_Msk

EXTI 4 configuration

◆ EXTI_EXTICR2_EXTI4_0

#define EXTI_EXTICR2_EXTI4_0 (0x1UL << EXTI_EXTICR2_EXTI4_Pos)

0x00000001

◆ EXTI_EXTICR2_EXTI4_1

#define EXTI_EXTICR2_EXTI4_1 (0x2UL << EXTI_EXTICR2_EXTI4_Pos)

0x00000002

◆ EXTI_EXTICR2_EXTI4_2

#define EXTI_EXTICR2_EXTI4_2 (0x4UL << EXTI_EXTICR2_EXTI4_Pos)

0x00000004

◆ EXTI_EXTICR2_EXTI4_Msk

#define EXTI_EXTICR2_EXTI4_Msk (0x7UL << EXTI_EXTICR2_EXTI4_Pos)

0x00000007

◆ EXTI_EXTICR2_EXTI4_Pos

#define EXTI_EXTICR2_EXTI4_Pos (0U)

◆ EXTI_EXTICR2_EXTI5

#define EXTI_EXTICR2_EXTI5 EXTI_EXTICR2_EXTI5_Msk

EXTI 5 configuration

◆ EXTI_EXTICR2_EXTI5_0

#define EXTI_EXTICR2_EXTI5_0 (0x1UL << EXTI_EXTICR2_EXTI5_Pos)

0x00000100

◆ EXTI_EXTICR2_EXTI5_1

#define EXTI_EXTICR2_EXTI5_1 (0x2UL << EXTI_EXTICR2_EXTI5_Pos)

0x00000200

◆ EXTI_EXTICR2_EXTI5_2

#define EXTI_EXTICR2_EXTI5_2 (0x4UL << EXTI_EXTICR2_EXTI5_Pos)

0x00000400

◆ EXTI_EXTICR2_EXTI5_Msk

#define EXTI_EXTICR2_EXTI5_Msk (0x7UL << EXTI_EXTICR2_EXTI5_Pos)

0x00000700

◆ EXTI_EXTICR2_EXTI5_Pos

#define EXTI_EXTICR2_EXTI5_Pos (8U)

◆ EXTI_EXTICR2_EXTI6

#define EXTI_EXTICR2_EXTI6 EXTI_EXTICR2_EXTI6_Msk

EXTI 6 configuration

◆ EXTI_EXTICR2_EXTI6_0

#define EXTI_EXTICR2_EXTI6_0 (0x1UL << EXTI_EXTICR2_EXTI6_Pos)

0x00010000

◆ EXTI_EXTICR2_EXTI6_1

#define EXTI_EXTICR2_EXTI6_1 (0x2UL << EXTI_EXTICR2_EXTI6_Pos)

0x00020000

◆ EXTI_EXTICR2_EXTI6_2

#define EXTI_EXTICR2_EXTI6_2 (0x4UL << EXTI_EXTICR2_EXTI6_Pos)

0x00040000

◆ EXTI_EXTICR2_EXTI6_Msk

#define EXTI_EXTICR2_EXTI6_Msk (0x7UL << EXTI_EXTICR2_EXTI6_Pos)

0x00070000

◆ EXTI_EXTICR2_EXTI6_Pos

#define EXTI_EXTICR2_EXTI6_Pos (16U)

◆ EXTI_EXTICR2_EXTI7

#define EXTI_EXTICR2_EXTI7 EXTI_EXTICR2_EXTI7_Msk

EXTI 7 configuration

◆ EXTI_EXTICR2_EXTI7_0

#define EXTI_EXTICR2_EXTI7_0 (0x1UL << EXTI_EXTICR2_EXTI7_Pos)

0x01000000

◆ EXTI_EXTICR2_EXTI7_1

#define EXTI_EXTICR2_EXTI7_1 (0x2UL << EXTI_EXTICR2_EXTI7_Pos)

0x02000000

◆ EXTI_EXTICR2_EXTI7_2

#define EXTI_EXTICR2_EXTI7_2 (0x4UL << EXTI_EXTICR2_EXTI7_Pos)

0x04000000

◆ EXTI_EXTICR2_EXTI7_Msk

#define EXTI_EXTICR2_EXTI7_Msk (0x7UL << EXTI_EXTICR2_EXTI7_Pos)

0x07000000

◆ EXTI_EXTICR2_EXTI7_Pos

#define EXTI_EXTICR2_EXTI7_Pos (24U)

◆ EXTI_EXTICR3_EXTI10

#define EXTI_EXTICR3_EXTI10 EXTI_EXTICR3_EXTI10_Msk

EXTI 10 configuration

◆ EXTI_EXTICR3_EXTI10_0

#define EXTI_EXTICR3_EXTI10_0 (0x1UL << EXTI_EXTICR3_EXTI10_Pos)

0x00010000

◆ EXTI_EXTICR3_EXTI10_1

#define EXTI_EXTICR3_EXTI10_1 (0x2UL << EXTI_EXTICR3_EXTI10_Pos)

0x00020000

◆ EXTI_EXTICR3_EXTI10_2

#define EXTI_EXTICR3_EXTI10_2 (0x4UL << EXTI_EXTICR3_EXTI10_Pos)

0x00040000

◆ EXTI_EXTICR3_EXTI10_Msk

#define EXTI_EXTICR3_EXTI10_Msk (0x7UL << EXTI_EXTICR3_EXTI10_Pos)

0x00070000

◆ EXTI_EXTICR3_EXTI10_Pos

#define EXTI_EXTICR3_EXTI10_Pos (16U)

◆ EXTI_EXTICR3_EXTI11

#define EXTI_EXTICR3_EXTI11 EXTI_EXTICR3_EXTI11_Msk

EXTI 11 configuration

◆ EXTI_EXTICR3_EXTI11_0

#define EXTI_EXTICR3_EXTI11_0 (0x1UL << EXTI_EXTICR3_EXTI11_Pos)

0x01000000

◆ EXTI_EXTICR3_EXTI11_1

#define EXTI_EXTICR3_EXTI11_1 (0x2UL << EXTI_EXTICR3_EXTI11_Pos)

0x02000000

◆ EXTI_EXTICR3_EXTI11_2

#define EXTI_EXTICR3_EXTI11_2 (0x4UL << EXTI_EXTICR3_EXTI11_Pos)

0x04000000

◆ EXTI_EXTICR3_EXTI11_Msk

#define EXTI_EXTICR3_EXTI11_Msk (0x7UL << EXTI_EXTICR3_EXTI11_Pos)

0x07000000

◆ EXTI_EXTICR3_EXTI11_Pos

#define EXTI_EXTICR3_EXTI11_Pos (24U)

◆ EXTI_EXTICR3_EXTI8

#define EXTI_EXTICR3_EXTI8 EXTI_EXTICR3_EXTI8_Msk

EXTI 8 configuration

◆ EXTI_EXTICR3_EXTI8_0

#define EXTI_EXTICR3_EXTI8_0 (0x1UL << EXTI_EXTICR3_EXTI8_Pos)

0x00000001

◆ EXTI_EXTICR3_EXTI8_1

#define EXTI_EXTICR3_EXTI8_1 (0x2UL << EXTI_EXTICR3_EXTI8_Pos)

0x00000002

◆ EXTI_EXTICR3_EXTI8_2

#define EXTI_EXTICR3_EXTI8_2 (0x4UL << EXTI_EXTICR3_EXTI8_Pos)

0x00000004

◆ EXTI_EXTICR3_EXTI8_Msk

#define EXTI_EXTICR3_EXTI8_Msk (0x7UL << EXTI_EXTICR3_EXTI8_Pos)

0x00000007

◆ EXTI_EXTICR3_EXTI8_Pos

#define EXTI_EXTICR3_EXTI8_Pos (0U)

◆ EXTI_EXTICR3_EXTI9

#define EXTI_EXTICR3_EXTI9 EXTI_EXTICR3_EXTI9_Msk

EXTI 9 configuration

◆ EXTI_EXTICR3_EXTI9_0

#define EXTI_EXTICR3_EXTI9_0 (0x1UL << EXTI_EXTICR3_EXTI9_Pos)

0x00000100

◆ EXTI_EXTICR3_EXTI9_1

#define EXTI_EXTICR3_EXTI9_1 (0x2UL << EXTI_EXTICR3_EXTI9_Pos)

0x00000200

◆ EXTI_EXTICR3_EXTI9_2

#define EXTI_EXTICR3_EXTI9_2 (0x4UL << EXTI_EXTICR3_EXTI9_Pos)

0x00000400

◆ EXTI_EXTICR3_EXTI9_Msk

#define EXTI_EXTICR3_EXTI9_Msk (0x7UL << EXTI_EXTICR3_EXTI9_Pos)

0x00000700

◆ EXTI_EXTICR3_EXTI9_Pos

#define EXTI_EXTICR3_EXTI9_Pos (8U)

◆ EXTI_EXTICR4_EXTI12

#define EXTI_EXTICR4_EXTI12 EXTI_EXTICR4_EXTI12_Msk

EXTI 12 configuration

◆ EXTI_EXTICR4_EXTI12_0

#define EXTI_EXTICR4_EXTI12_0 (0x1UL << EXTI_EXTICR4_EXTI12_Pos)

0x00000001

◆ EXTI_EXTICR4_EXTI12_1

#define EXTI_EXTICR4_EXTI12_1 (0x2UL << EXTI_EXTICR4_EXTI12_Pos)

0x00000002

◆ EXTI_EXTICR4_EXTI12_2

#define EXTI_EXTICR4_EXTI12_2 (0x4UL << EXTI_EXTICR4_EXTI12_Pos)

0x00000004

◆ EXTI_EXTICR4_EXTI12_Msk

#define EXTI_EXTICR4_EXTI12_Msk (0x7UL << EXTI_EXTICR4_EXTI12_Pos)

0x00000007

◆ EXTI_EXTICR4_EXTI12_Pos

#define EXTI_EXTICR4_EXTI12_Pos (0U)

◆ EXTI_EXTICR4_EXTI13

#define EXTI_EXTICR4_EXTI13 EXTI_EXTICR4_EXTI13_Msk

EXTI 13 configuration

◆ EXTI_EXTICR4_EXTI13_0

#define EXTI_EXTICR4_EXTI13_0 (0x1UL << EXTI_EXTICR4_EXTI13_Pos)

0x00000100

◆ EXTI_EXTICR4_EXTI13_1

#define EXTI_EXTICR4_EXTI13_1 (0x2UL << EXTI_EXTICR4_EXTI13_Pos)

0x00000200

◆ EXTI_EXTICR4_EXTI13_2

#define EXTI_EXTICR4_EXTI13_2 (0x4UL << EXTI_EXTICR4_EXTI13_Pos)

0x00000400

◆ EXTI_EXTICR4_EXTI13_Msk

#define EXTI_EXTICR4_EXTI13_Msk (0x7UL << EXTI_EXTICR4_EXTI13_Pos)

0x00000700

◆ EXTI_EXTICR4_EXTI13_Pos

#define EXTI_EXTICR4_EXTI13_Pos (8U)

◆ EXTI_EXTICR4_EXTI14

#define EXTI_EXTICR4_EXTI14 EXTI_EXTICR4_EXTI14_Msk

EXTI 14 configuration

◆ EXTI_EXTICR4_EXTI14_0

#define EXTI_EXTICR4_EXTI14_0 (0x1UL << EXTI_EXTICR4_EXTI14_Pos)

0x00010000

◆ EXTI_EXTICR4_EXTI14_1

#define EXTI_EXTICR4_EXTI14_1 (0x2UL << EXTI_EXTICR4_EXTI14_Pos)

0x00020000

◆ EXTI_EXTICR4_EXTI14_2

#define EXTI_EXTICR4_EXTI14_2 (0x4UL << EXTI_EXTICR4_EXTI14_Pos)

0x00040000

◆ EXTI_EXTICR4_EXTI14_Msk

#define EXTI_EXTICR4_EXTI14_Msk (0x7UL << EXTI_EXTICR4_EXTI14_Pos)

0x00070000

◆ EXTI_EXTICR4_EXTI14_Pos

#define EXTI_EXTICR4_EXTI14_Pos (16U)

◆ EXTI_EXTICR4_EXTI15

#define EXTI_EXTICR4_EXTI15 EXTI_EXTICR4_EXTI15_Msk

EXTI 15 configuration

◆ EXTI_EXTICR4_EXTI15_0

#define EXTI_EXTICR4_EXTI15_0 (0x1UL << EXTI_EXTICR4_EXTI15_Pos)

0x01000000

◆ EXTI_EXTICR4_EXTI15_1

#define EXTI_EXTICR4_EXTI15_1 (0x2UL << EXTI_EXTICR4_EXTI15_Pos)

0x02000000

◆ EXTI_EXTICR4_EXTI15_2

#define EXTI_EXTICR4_EXTI15_2 (0x4UL << EXTI_EXTICR4_EXTI15_Pos)

0x04000000

◆ EXTI_EXTICR4_EXTI15_Msk

#define EXTI_EXTICR4_EXTI15_Msk (0x7UL << EXTI_EXTICR4_EXTI15_Pos)

0x07000000

◆ EXTI_EXTICR4_EXTI15_Pos

#define EXTI_EXTICR4_EXTI15_Pos (24U)

◆ EXTI_FPR1_FPIF0

#define EXTI_FPR1_FPIF0 EXTI_FPR1_FPIF0_Msk

Falling Pending Interrupt Flag on line 0

◆ EXTI_FPR1_FPIF0_Msk

#define EXTI_FPR1_FPIF0_Msk (0x1UL << EXTI_FPR1_FPIF0_Pos)

0x00000001

◆ EXTI_FPR1_FPIF0_Pos

#define EXTI_FPR1_FPIF0_Pos (0U)

◆ EXTI_FPR1_FPIF1

#define EXTI_FPR1_FPIF1 EXTI_FPR1_FPIF1_Msk

Falling Pending Interrupt Flag on line 1

◆ EXTI_FPR1_FPIF10

#define EXTI_FPR1_FPIF10 EXTI_FPR1_FPIF10_Msk

Falling Pending Interrupt Flag on line 10

◆ EXTI_FPR1_FPIF10_Msk

#define EXTI_FPR1_FPIF10_Msk (0x1UL << EXTI_FPR1_FPIF10_Pos)

0x00000400

◆ EXTI_FPR1_FPIF10_Pos

#define EXTI_FPR1_FPIF10_Pos (10U)

◆ EXTI_FPR1_FPIF11

#define EXTI_FPR1_FPIF11 EXTI_FPR1_FPIF11_Msk

Falling Pending Interrupt Flag on line 11

◆ EXTI_FPR1_FPIF11_Msk

#define EXTI_FPR1_FPIF11_Msk (0x1UL << EXTI_FPR1_FPIF11_Pos)

0x00000800

◆ EXTI_FPR1_FPIF11_Pos

#define EXTI_FPR1_FPIF11_Pos (11U)

◆ EXTI_FPR1_FPIF12

#define EXTI_FPR1_FPIF12 EXTI_FPR1_FPIF12_Msk

Falling Pending Interrupt Flag on line 12

◆ EXTI_FPR1_FPIF12_Msk

#define EXTI_FPR1_FPIF12_Msk (0x1UL << EXTI_FPR1_FPIF12_Pos)

0x00001000

◆ EXTI_FPR1_FPIF12_Pos

#define EXTI_FPR1_FPIF12_Pos (12U)

◆ EXTI_FPR1_FPIF13

#define EXTI_FPR1_FPIF13 EXTI_FPR1_FPIF13_Msk

Falling Pending Interrupt Flag on line 13

◆ EXTI_FPR1_FPIF13_Msk

#define EXTI_FPR1_FPIF13_Msk (0x1UL << EXTI_FPR1_FPIF13_Pos)

0x00002000

◆ EXTI_FPR1_FPIF13_Pos

#define EXTI_FPR1_FPIF13_Pos (13U)

◆ EXTI_FPR1_FPIF14

#define EXTI_FPR1_FPIF14 EXTI_FPR1_FPIF14_Msk

Falling Pending Interrupt Flag on line 14

◆ EXTI_FPR1_FPIF14_Msk

#define EXTI_FPR1_FPIF14_Msk (0x1UL << EXTI_FPR1_FPIF14_Pos)

0x00004000

◆ EXTI_FPR1_FPIF14_Pos

#define EXTI_FPR1_FPIF14_Pos (14U)

◆ EXTI_FPR1_FPIF15

#define EXTI_FPR1_FPIF15 EXTI_FPR1_FPIF15_Msk

Falling Pending Interrupt Flag on line 15

◆ EXTI_FPR1_FPIF15_Msk

#define EXTI_FPR1_FPIF15_Msk (0x1UL << EXTI_FPR1_FPIF15_Pos)

0x00008000

◆ EXTI_FPR1_FPIF15_Pos

#define EXTI_FPR1_FPIF15_Pos (15U)

◆ EXTI_FPR1_FPIF1_Msk

#define EXTI_FPR1_FPIF1_Msk (0x1UL << EXTI_FPR1_FPIF1_Pos)

0x00000002

◆ EXTI_FPR1_FPIF1_Pos

#define EXTI_FPR1_FPIF1_Pos (1U)

◆ EXTI_FPR1_FPIF2

#define EXTI_FPR1_FPIF2 EXTI_FPR1_FPIF2_Msk

Falling Pending Interrupt Flag on line 2

◆ EXTI_FPR1_FPIF2_Msk

#define EXTI_FPR1_FPIF2_Msk (0x1UL << EXTI_FPR1_FPIF2_Pos)

0x00000004

◆ EXTI_FPR1_FPIF2_Pos

#define EXTI_FPR1_FPIF2_Pos (2U)

◆ EXTI_FPR1_FPIF3

#define EXTI_FPR1_FPIF3 EXTI_FPR1_FPIF3_Msk

Falling Pending Interrupt Flag on line 3

◆ EXTI_FPR1_FPIF3_Msk

#define EXTI_FPR1_FPIF3_Msk (0x1UL << EXTI_FPR1_FPIF3_Pos)

0x00000008

◆ EXTI_FPR1_FPIF3_Pos

#define EXTI_FPR1_FPIF3_Pos (3U)

◆ EXTI_FPR1_FPIF4

#define EXTI_FPR1_FPIF4 EXTI_FPR1_FPIF4_Msk

Falling Pending Interrupt Flag on line 4

◆ EXTI_FPR1_FPIF4_Msk

#define EXTI_FPR1_FPIF4_Msk (0x1UL << EXTI_FPR1_FPIF4_Pos)

0x00000010

◆ EXTI_FPR1_FPIF4_Pos

#define EXTI_FPR1_FPIF4_Pos (4U)

◆ EXTI_FPR1_FPIF5

#define EXTI_FPR1_FPIF5 EXTI_FPR1_FPIF5_Msk

Falling Pending Interrupt Flag on line 5

◆ EXTI_FPR1_FPIF5_Msk

#define EXTI_FPR1_FPIF5_Msk (0x1UL << EXTI_FPR1_FPIF5_Pos)

0x00000020

◆ EXTI_FPR1_FPIF5_Pos

#define EXTI_FPR1_FPIF5_Pos (5U)

◆ EXTI_FPR1_FPIF6

#define EXTI_FPR1_FPIF6 EXTI_FPR1_FPIF6_Msk

Falling Pending Interrupt Flag on line 6

◆ EXTI_FPR1_FPIF6_Msk

#define EXTI_FPR1_FPIF6_Msk (0x1UL << EXTI_FPR1_FPIF6_Pos)

0x00000040

◆ EXTI_FPR1_FPIF6_Pos

#define EXTI_FPR1_FPIF6_Pos (6U)

◆ EXTI_FPR1_FPIF7

#define EXTI_FPR1_FPIF7 EXTI_FPR1_FPIF7_Msk

Falling Pending Interrupt Flag on line 7

◆ EXTI_FPR1_FPIF7_Msk

#define EXTI_FPR1_FPIF7_Msk (0x1UL << EXTI_FPR1_FPIF7_Pos)

0x00000080

◆ EXTI_FPR1_FPIF7_Pos

#define EXTI_FPR1_FPIF7_Pos (7U)

◆ EXTI_FPR1_FPIF8

#define EXTI_FPR1_FPIF8 EXTI_FPR1_FPIF8_Msk

Falling Pending Interrupt Flag on line 8

◆ EXTI_FPR1_FPIF8_Msk

#define EXTI_FPR1_FPIF8_Msk (0x1UL << EXTI_FPR1_FPIF8_Pos)

0x00000100

◆ EXTI_FPR1_FPIF8_Pos

#define EXTI_FPR1_FPIF8_Pos (8U)

◆ EXTI_FPR1_FPIF9

#define EXTI_FPR1_FPIF9 EXTI_FPR1_FPIF9_Msk

Falling Pending Interrupt Flag on line 9

◆ EXTI_FPR1_FPIF9_Msk

#define EXTI_FPR1_FPIF9_Msk (0x1UL << EXTI_FPR1_FPIF9_Pos)

0x00000200

◆ EXTI_FPR1_FPIF9_Pos

#define EXTI_FPR1_FPIF9_Pos (9U)

◆ EXTI_FTSR1_FT0

#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk

Falling trigger configuration for input line 0

◆ EXTI_FTSR1_FT0_Msk

#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos)

0x00000001

◆ EXTI_FTSR1_FT0_Pos

#define EXTI_FTSR1_FT0_Pos (0U)

◆ EXTI_FTSR1_FT1

#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk

Falling trigger configuration for input line 1

◆ EXTI_FTSR1_FT10

#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk

Falling trigger configuration for input line 10

◆ EXTI_FTSR1_FT10_Msk

#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos)

0x00000400

◆ EXTI_FTSR1_FT10_Pos

#define EXTI_FTSR1_FT10_Pos (10U)

◆ EXTI_FTSR1_FT11

#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk

Falling trigger configuration for input line 11

◆ EXTI_FTSR1_FT11_Msk

#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos)

0x00000800

◆ EXTI_FTSR1_FT11_Pos

#define EXTI_FTSR1_FT11_Pos (11U)

◆ EXTI_FTSR1_FT12

#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk

Falling trigger configuration for input line 12

◆ EXTI_FTSR1_FT12_Msk

#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos)

0x00001000

◆ EXTI_FTSR1_FT12_Pos

#define EXTI_FTSR1_FT12_Pos (12U)

◆ EXTI_FTSR1_FT13

#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk

Falling trigger configuration for input line 13

◆ EXTI_FTSR1_FT13_Msk

#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos)

0x00002000

◆ EXTI_FTSR1_FT13_Pos

#define EXTI_FTSR1_FT13_Pos (13U)

◆ EXTI_FTSR1_FT14

#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk

Falling trigger configuration for input line 14

◆ EXTI_FTSR1_FT14_Msk

#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos)

0x00004000

◆ EXTI_FTSR1_FT14_Pos

#define EXTI_FTSR1_FT14_Pos (14U)

◆ EXTI_FTSR1_FT15

#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk

Falling trigger configuration for input line 15

◆ EXTI_FTSR1_FT15_Msk

#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos)

0x00008000

◆ EXTI_FTSR1_FT15_Pos

#define EXTI_FTSR1_FT15_Pos (15U)

◆ EXTI_FTSR1_FT1_Msk

#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos)

0x00000002

◆ EXTI_FTSR1_FT1_Pos

#define EXTI_FTSR1_FT1_Pos (1U)

◆ EXTI_FTSR1_FT2

#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk

Falling trigger configuration for input line 2

◆ EXTI_FTSR1_FT2_Msk

#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos)

0x00000004

◆ EXTI_FTSR1_FT2_Pos

#define EXTI_FTSR1_FT2_Pos (2U)

◆ EXTI_FTSR1_FT3

#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk

Falling trigger configuration for input line 3

◆ EXTI_FTSR1_FT3_Msk

#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos)

0x00000008

◆ EXTI_FTSR1_FT3_Pos

#define EXTI_FTSR1_FT3_Pos (3U)

◆ EXTI_FTSR1_FT4

#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk

Falling trigger configuration for input line 4

◆ EXTI_FTSR1_FT4_Msk

#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos)

0x00000010

◆ EXTI_FTSR1_FT4_Pos

#define EXTI_FTSR1_FT4_Pos (4U)

◆ EXTI_FTSR1_FT5

#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk

Falling trigger configuration for input line 5

◆ EXTI_FTSR1_FT5_Msk

#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos)

0x00000020

◆ EXTI_FTSR1_FT5_Pos

#define EXTI_FTSR1_FT5_Pos (5U)

◆ EXTI_FTSR1_FT6

#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk

Falling trigger configuration for input line 6

◆ EXTI_FTSR1_FT6_Msk

#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos)

0x00000040

◆ EXTI_FTSR1_FT6_Pos

#define EXTI_FTSR1_FT6_Pos (6U)

◆ EXTI_FTSR1_FT7

#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk

Falling trigger configuration for input line 7

◆ EXTI_FTSR1_FT7_Msk

#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos)

0x00000080

◆ EXTI_FTSR1_FT7_Pos

#define EXTI_FTSR1_FT7_Pos (7U)

◆ EXTI_FTSR1_FT8

#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk

Falling trigger configuration for input line 8

◆ EXTI_FTSR1_FT8_Msk

#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos)

0x00000100

◆ EXTI_FTSR1_FT8_Pos

#define EXTI_FTSR1_FT8_Pos (8U)

◆ EXTI_FTSR1_FT9

#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk

Falling trigger configuration for input line 9

◆ EXTI_FTSR1_FT9_Msk

#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos)

0x00000200

◆ EXTI_FTSR1_FT9_Pos

#define EXTI_FTSR1_FT9_Pos (9U)

◆ EXTI_IMR1_IM

#define EXTI_IMR1_IM EXTI_IMR1_IM_Msk

Interrupt Mask All

◆ EXTI_IMR1_IM0

#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk

Interrupt Mask on line 0

◆ EXTI_IMR1_IM0_Msk

#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos)

0x00000001

◆ EXTI_IMR1_IM0_Pos

#define EXTI_IMR1_IM0_Pos (0U)

◆ EXTI_IMR1_IM1

#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk

Interrupt Mask on line 1

◆ EXTI_IMR1_IM10

#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk

Interrupt Mask on line 10

◆ EXTI_IMR1_IM10_Msk

#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos)

0x00000400

◆ EXTI_IMR1_IM10_Pos

#define EXTI_IMR1_IM10_Pos (10U)

◆ EXTI_IMR1_IM11

#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk

Interrupt Mask on line 11

◆ EXTI_IMR1_IM11_Msk

#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos)

0x00000800

◆ EXTI_IMR1_IM11_Pos

#define EXTI_IMR1_IM11_Pos (11U)

◆ EXTI_IMR1_IM12

#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk

Interrupt Mask on line 12

◆ EXTI_IMR1_IM12_Msk

#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos)

0x00001000

◆ EXTI_IMR1_IM12_Pos

#define EXTI_IMR1_IM12_Pos (12U)

◆ EXTI_IMR1_IM13

#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk

Interrupt Mask on line 13

◆ EXTI_IMR1_IM13_Msk

#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos)

0x00002000

◆ EXTI_IMR1_IM13_Pos

#define EXTI_IMR1_IM13_Pos (13U)

◆ EXTI_IMR1_IM14

#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk

Interrupt Mask on line 14

◆ EXTI_IMR1_IM14_Msk

#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos)

0x00004000

◆ EXTI_IMR1_IM14_Pos

#define EXTI_IMR1_IM14_Pos (14U)

◆ EXTI_IMR1_IM15

#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk

Interrupt Mask on line 15

◆ EXTI_IMR1_IM15_Msk

#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos)

0x00008000

◆ EXTI_IMR1_IM15_Pos

#define EXTI_IMR1_IM15_Pos (15U)

◆ EXTI_IMR1_IM19

#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk

Interrupt Mask on line 19

◆ EXTI_IMR1_IM19_Msk

#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos)

0x00080000

◆ EXTI_IMR1_IM19_Pos

#define EXTI_IMR1_IM19_Pos (19U)

◆ EXTI_IMR1_IM1_Msk

#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos)

0x00000002

◆ EXTI_IMR1_IM1_Pos

#define EXTI_IMR1_IM1_Pos (1U)

◆ EXTI_IMR1_IM2

#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk

Interrupt Mask on line 2

◆ EXTI_IMR1_IM21

#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk

Interrupt Mask on line 21

◆ EXTI_IMR1_IM21_Msk

#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos)

0x00200000

◆ EXTI_IMR1_IM21_Pos

#define EXTI_IMR1_IM21_Pos (21U)

◆ EXTI_IMR1_IM23

#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk

Interrupt Mask on line 23

◆ EXTI_IMR1_IM23_Msk

#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos)

0x00800000

◆ EXTI_IMR1_IM23_Pos

#define EXTI_IMR1_IM23_Pos (23U)

◆ EXTI_IMR1_IM25

#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk

Interrupt Mask on line 25

◆ EXTI_IMR1_IM25_Msk

#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos)

0x02000000

◆ EXTI_IMR1_IM25_Pos

#define EXTI_IMR1_IM25_Pos (25U)

◆ EXTI_IMR1_IM2_Msk

#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos)

0x00000004

◆ EXTI_IMR1_IM2_Pos

#define EXTI_IMR1_IM2_Pos (2U)

◆ EXTI_IMR1_IM3

#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk

Interrupt Mask on line 3

◆ EXTI_IMR1_IM31

#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk

Interrupt Mask on line 31

◆ EXTI_IMR1_IM31_Msk

#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos)

0x80000000

◆ EXTI_IMR1_IM31_Pos

#define EXTI_IMR1_IM31_Pos (31U)

◆ EXTI_IMR1_IM3_Msk

#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos)

0x00000008

◆ EXTI_IMR1_IM3_Pos

#define EXTI_IMR1_IM3_Pos (3U)

◆ EXTI_IMR1_IM4

#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk

Interrupt Mask on line 4

◆ EXTI_IMR1_IM4_Msk

#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos)

0x00000010

◆ EXTI_IMR1_IM4_Pos

#define EXTI_IMR1_IM4_Pos (4U)

◆ EXTI_IMR1_IM5

#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk

Interrupt Mask on line 5

◆ EXTI_IMR1_IM5_Msk

#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos)

0x00000020

◆ EXTI_IMR1_IM5_Pos

#define EXTI_IMR1_IM5_Pos (5U)

◆ EXTI_IMR1_IM6

#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk

Interrupt Mask on line 6

◆ EXTI_IMR1_IM6_Msk

#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos)

0x00000040

◆ EXTI_IMR1_IM6_Pos

#define EXTI_IMR1_IM6_Pos (6U)

◆ EXTI_IMR1_IM7

#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk

Interrupt Mask on line 7

◆ EXTI_IMR1_IM7_Msk

#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos)

0x00000080

◆ EXTI_IMR1_IM7_Pos

#define EXTI_IMR1_IM7_Pos (7U)

◆ EXTI_IMR1_IM8

#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk

Interrupt Mask on line 8

◆ EXTI_IMR1_IM8_Msk

#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos)

0x00000100

◆ EXTI_IMR1_IM8_Pos

#define EXTI_IMR1_IM8_Pos (8U)

◆ EXTI_IMR1_IM9

#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk

Interrupt Mask on line 9

◆ EXTI_IMR1_IM9_Msk

#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos)

0x00000200

◆ EXTI_IMR1_IM9_Pos

#define EXTI_IMR1_IM9_Pos (9U)

◆ EXTI_IMR1_IM_Msk

#define EXTI_IMR1_IM_Msk (0x82A8FFFFUL << EXTI_IMR1_IM_Pos)

0x82A8FFFF

◆ EXTI_IMR1_IM_Pos

#define EXTI_IMR1_IM_Pos (0U)

◆ EXTI_RPR1_RPIF0

#define EXTI_RPR1_RPIF0 EXTI_RPR1_RPIF0_Msk

Rising Pending Interrupt Flag on line 0

◆ EXTI_RPR1_RPIF0_Msk

#define EXTI_RPR1_RPIF0_Msk (0x1UL << EXTI_RPR1_RPIF0_Pos)

0x00000001

◆ EXTI_RPR1_RPIF0_Pos

#define EXTI_RPR1_RPIF0_Pos (0U)

◆ EXTI_RPR1_RPIF1

#define EXTI_RPR1_RPIF1 EXTI_RPR1_RPIF1_Msk

Rising Pending Interrupt Flag on line 1

◆ EXTI_RPR1_RPIF10

#define EXTI_RPR1_RPIF10 EXTI_RPR1_RPIF10_Msk

Rising Pending Interrupt Flag on line 10

◆ EXTI_RPR1_RPIF10_Msk

#define EXTI_RPR1_RPIF10_Msk (0x1UL << EXTI_RPR1_RPIF10_Pos)

0x00000400

◆ EXTI_RPR1_RPIF10_Pos

#define EXTI_RPR1_RPIF10_Pos (10U)

◆ EXTI_RPR1_RPIF11

#define EXTI_RPR1_RPIF11 EXTI_RPR1_RPIF11_Msk

Rising Pending Interrupt Flag on line 11

◆ EXTI_RPR1_RPIF11_Msk

#define EXTI_RPR1_RPIF11_Msk (0x1UL << EXTI_RPR1_RPIF11_Pos)

0x00000800

◆ EXTI_RPR1_RPIF11_Pos

#define EXTI_RPR1_RPIF11_Pos (11U)

◆ EXTI_RPR1_RPIF12

#define EXTI_RPR1_RPIF12 EXTI_RPR1_RPIF12_Msk

Rising Pending Interrupt Flag on line 12

◆ EXTI_RPR1_RPIF12_Msk

#define EXTI_RPR1_RPIF12_Msk (0x1UL << EXTI_RPR1_RPIF12_Pos)

0x00001000

◆ EXTI_RPR1_RPIF12_Pos

#define EXTI_RPR1_RPIF12_Pos (12U)

◆ EXTI_RPR1_RPIF13

#define EXTI_RPR1_RPIF13 EXTI_RPR1_RPIF13_Msk

Rising Pending Interrupt Flag on line 13

◆ EXTI_RPR1_RPIF13_Msk

#define EXTI_RPR1_RPIF13_Msk (0x1UL << EXTI_RPR1_RPIF13_Pos)

0x00002000

◆ EXTI_RPR1_RPIF13_Pos

#define EXTI_RPR1_RPIF13_Pos (13U)

◆ EXTI_RPR1_RPIF14

#define EXTI_RPR1_RPIF14 EXTI_RPR1_RPIF14_Msk

Rising Pending Interrupt Flag on line 14

◆ EXTI_RPR1_RPIF14_Msk

#define EXTI_RPR1_RPIF14_Msk (0x1UL << EXTI_RPR1_RPIF14_Pos)

0x00004000

◆ EXTI_RPR1_RPIF14_Pos

#define EXTI_RPR1_RPIF14_Pos (14U)

◆ EXTI_RPR1_RPIF15

#define EXTI_RPR1_RPIF15 EXTI_RPR1_RPIF15_Msk

Rising Pending Interrupt Flag on line 15

◆ EXTI_RPR1_RPIF15_Msk

#define EXTI_RPR1_RPIF15_Msk (0x1UL << EXTI_RPR1_RPIF15_Pos)

0x00008000

◆ EXTI_RPR1_RPIF15_Pos

#define EXTI_RPR1_RPIF15_Pos (15U)

◆ EXTI_RPR1_RPIF1_Msk

#define EXTI_RPR1_RPIF1_Msk (0x1UL << EXTI_RPR1_RPIF1_Pos)

0x00000002

◆ EXTI_RPR1_RPIF1_Pos

#define EXTI_RPR1_RPIF1_Pos (1U)

◆ EXTI_RPR1_RPIF2

#define EXTI_RPR1_RPIF2 EXTI_RPR1_RPIF2_Msk

Rising Pending Interrupt Flag on line 2

◆ EXTI_RPR1_RPIF2_Msk

#define EXTI_RPR1_RPIF2_Msk (0x1UL << EXTI_RPR1_RPIF2_Pos)

0x00000004

◆ EXTI_RPR1_RPIF2_Pos

#define EXTI_RPR1_RPIF2_Pos (2U)

◆ EXTI_RPR1_RPIF3

#define EXTI_RPR1_RPIF3 EXTI_RPR1_RPIF3_Msk

Rising Pending Interrupt Flag on line 3

◆ EXTI_RPR1_RPIF3_Msk

#define EXTI_RPR1_RPIF3_Msk (0x1UL << EXTI_RPR1_RPIF3_Pos)

0x00000008

◆ EXTI_RPR1_RPIF3_Pos

#define EXTI_RPR1_RPIF3_Pos (3U)

◆ EXTI_RPR1_RPIF4

#define EXTI_RPR1_RPIF4 EXTI_RPR1_RPIF4_Msk

Rising Pending Interrupt Flag on line 4

◆ EXTI_RPR1_RPIF4_Msk

#define EXTI_RPR1_RPIF4_Msk (0x1UL << EXTI_RPR1_RPIF4_Pos)

0x00000010

◆ EXTI_RPR1_RPIF4_Pos

#define EXTI_RPR1_RPIF4_Pos (4U)

◆ EXTI_RPR1_RPIF5

#define EXTI_RPR1_RPIF5 EXTI_RPR1_RPIF5_Msk

Rising Pending Interrupt Flag on line 5

◆ EXTI_RPR1_RPIF5_Msk

#define EXTI_RPR1_RPIF5_Msk (0x1UL << EXTI_RPR1_RPIF5_Pos)

0x00000020

◆ EXTI_RPR1_RPIF5_Pos

#define EXTI_RPR1_RPIF5_Pos (5U)

◆ EXTI_RPR1_RPIF6

#define EXTI_RPR1_RPIF6 EXTI_RPR1_RPIF6_Msk

Rising Pending Interrupt Flag on line 6

◆ EXTI_RPR1_RPIF6_Msk

#define EXTI_RPR1_RPIF6_Msk (0x1UL << EXTI_RPR1_RPIF6_Pos)

0x00000040

◆ EXTI_RPR1_RPIF6_Pos

#define EXTI_RPR1_RPIF6_Pos (6U)

◆ EXTI_RPR1_RPIF7

#define EXTI_RPR1_RPIF7 EXTI_RPR1_RPIF7_Msk

Rising Pending Interrupt Flag on line 7

◆ EXTI_RPR1_RPIF7_Msk

#define EXTI_RPR1_RPIF7_Msk (0x1UL << EXTI_RPR1_RPIF7_Pos)

0x00000080

◆ EXTI_RPR1_RPIF7_Pos

#define EXTI_RPR1_RPIF7_Pos (7U)

◆ EXTI_RPR1_RPIF8

#define EXTI_RPR1_RPIF8 EXTI_RPR1_RPIF8_Msk

Rising Pending Interrupt Flag on line 8

◆ EXTI_RPR1_RPIF8_Msk

#define EXTI_RPR1_RPIF8_Msk (0x1UL << EXTI_RPR1_RPIF8_Pos)

0x00000100

◆ EXTI_RPR1_RPIF8_Pos

#define EXTI_RPR1_RPIF8_Pos (8U)

◆ EXTI_RPR1_RPIF9

#define EXTI_RPR1_RPIF9 EXTI_RPR1_RPIF9_Msk

Rising Pending Interrupt Flag on line 9

◆ EXTI_RPR1_RPIF9_Msk

#define EXTI_RPR1_RPIF9_Msk (0x1UL << EXTI_RPR1_RPIF9_Pos)

0x00000200

◆ EXTI_RPR1_RPIF9_Pos

#define EXTI_RPR1_RPIF9_Pos (9U)

◆ EXTI_RTSR1_RT0

#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk

Rising trigger configuration for input line 0

◆ EXTI_RTSR1_RT0_Msk

#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos)

0x00000001

◆ EXTI_RTSR1_RT0_Pos

#define EXTI_RTSR1_RT0_Pos (0U)

◆ EXTI_RTSR1_RT1

#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk

Rising trigger configuration for input line 1

◆ EXTI_RTSR1_RT10

#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk

Rising trigger configuration for input line 10

◆ EXTI_RTSR1_RT10_Msk

#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos)

0x00000400

◆ EXTI_RTSR1_RT10_Pos

#define EXTI_RTSR1_RT10_Pos (10U)

◆ EXTI_RTSR1_RT11

#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk

Rising trigger configuration for input line 11

◆ EXTI_RTSR1_RT11_Msk

#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos)

0x00000800

◆ EXTI_RTSR1_RT11_Pos

#define EXTI_RTSR1_RT11_Pos (11U)

◆ EXTI_RTSR1_RT12

#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk

Rising trigger configuration for input line 12

◆ EXTI_RTSR1_RT12_Msk

#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos)

0x00001000

◆ EXTI_RTSR1_RT12_Pos

#define EXTI_RTSR1_RT12_Pos (12U)

◆ EXTI_RTSR1_RT13

#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk

Rising trigger configuration for input line 13

◆ EXTI_RTSR1_RT13_Msk

#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos)

0x00002000

◆ EXTI_RTSR1_RT13_Pos

#define EXTI_RTSR1_RT13_Pos (13U)

◆ EXTI_RTSR1_RT14

#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk

Rising trigger configuration for input line 14

◆ EXTI_RTSR1_RT14_Msk

#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos)

0x00004000

◆ EXTI_RTSR1_RT14_Pos

#define EXTI_RTSR1_RT14_Pos (14U)

◆ EXTI_RTSR1_RT15

#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk

Rising trigger configuration for input line 15

◆ EXTI_RTSR1_RT15_Msk

#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos)

0x00008000

◆ EXTI_RTSR1_RT15_Pos

#define EXTI_RTSR1_RT15_Pos (15U)

◆ EXTI_RTSR1_RT1_Msk

#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos)

0x00000002

◆ EXTI_RTSR1_RT1_Pos

#define EXTI_RTSR1_RT1_Pos (1U)

◆ EXTI_RTSR1_RT2

#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk

Rising trigger configuration for input line 2

◆ EXTI_RTSR1_RT2_Msk

#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos)

0x00000004

◆ EXTI_RTSR1_RT2_Pos

#define EXTI_RTSR1_RT2_Pos (2U)

◆ EXTI_RTSR1_RT3

#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk

Rising trigger configuration for input line 3

◆ EXTI_RTSR1_RT3_Msk

#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos)

0x00000008

◆ EXTI_RTSR1_RT3_Pos

#define EXTI_RTSR1_RT3_Pos (3U)

◆ EXTI_RTSR1_RT4

#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk

Rising trigger configuration for input line 4

◆ EXTI_RTSR1_RT4_Msk

#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos)

0x00000010

◆ EXTI_RTSR1_RT4_Pos

#define EXTI_RTSR1_RT4_Pos (4U)

◆ EXTI_RTSR1_RT5

#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk

Rising trigger configuration for input line 5

◆ EXTI_RTSR1_RT5_Msk

#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos)

0x00000020

◆ EXTI_RTSR1_RT5_Pos

#define EXTI_RTSR1_RT5_Pos (5U)

◆ EXTI_RTSR1_RT6

#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk

Rising trigger configuration for input line 6

◆ EXTI_RTSR1_RT6_Msk

#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos)

0x00000040

◆ EXTI_RTSR1_RT6_Pos

#define EXTI_RTSR1_RT6_Pos (6U)

◆ EXTI_RTSR1_RT7

#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk

Rising trigger configuration for input line 7

◆ EXTI_RTSR1_RT7_Msk

#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos)

0x00000080

◆ EXTI_RTSR1_RT7_Pos

#define EXTI_RTSR1_RT7_Pos (7U)

◆ EXTI_RTSR1_RT8

#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk

Rising trigger configuration for input line 8

◆ EXTI_RTSR1_RT8_Msk

#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos)

0x00000100

◆ EXTI_RTSR1_RT8_Pos

#define EXTI_RTSR1_RT8_Pos (8U)

◆ EXTI_RTSR1_RT9

#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk

Rising trigger configuration for input line 9

◆ EXTI_RTSR1_RT9_Msk

#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos)

0x00000200

◆ EXTI_RTSR1_RT9_Pos

#define EXTI_RTSR1_RT9_Pos (9U)

◆ EXTI_SWIER1_SWI0

#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk

Software Interrupt on line 0

◆ EXTI_SWIER1_SWI0_Msk

#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos)

0x00000001

◆ EXTI_SWIER1_SWI0_Pos

#define EXTI_SWIER1_SWI0_Pos (0U)

◆ EXTI_SWIER1_SWI1

#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk

Software Interrupt on line 1

◆ EXTI_SWIER1_SWI10

#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk

Software Interrupt on line 10

◆ EXTI_SWIER1_SWI10_Msk

#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos)

0x00000400

◆ EXTI_SWIER1_SWI10_Pos

#define EXTI_SWIER1_SWI10_Pos (10U)

◆ EXTI_SWIER1_SWI11

#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk

Software Interrupt on line 11

◆ EXTI_SWIER1_SWI11_Msk

#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos)

0x00000800

◆ EXTI_SWIER1_SWI11_Pos

#define EXTI_SWIER1_SWI11_Pos (11U)

◆ EXTI_SWIER1_SWI12

#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk

Software Interrupt on line 12

◆ EXTI_SWIER1_SWI12_Msk

#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos)

0x00001000

◆ EXTI_SWIER1_SWI12_Pos

#define EXTI_SWIER1_SWI12_Pos (12U)

◆ EXTI_SWIER1_SWI13

#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk

Software Interrupt on line 13

◆ EXTI_SWIER1_SWI13_Msk

#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos)

0x00002000

◆ EXTI_SWIER1_SWI13_Pos

#define EXTI_SWIER1_SWI13_Pos (13U)

◆ EXTI_SWIER1_SWI14

#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk

Software Interrupt on line 14

◆ EXTI_SWIER1_SWI14_Msk

#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos)

0x00004000

◆ EXTI_SWIER1_SWI14_Pos

#define EXTI_SWIER1_SWI14_Pos (14U)

◆ EXTI_SWIER1_SWI15

#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk

Software Interrupt on line 15

◆ EXTI_SWIER1_SWI15_Msk

#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos)

0x00008000

◆ EXTI_SWIER1_SWI15_Pos

#define EXTI_SWIER1_SWI15_Pos (15U)

◆ EXTI_SWIER1_SWI1_Msk

#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos)

0x00000002

◆ EXTI_SWIER1_SWI1_Pos

#define EXTI_SWIER1_SWI1_Pos (1U)

◆ EXTI_SWIER1_SWI2

#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk

Software Interrupt on line 2

◆ EXTI_SWIER1_SWI2_Msk

#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos)

0x00000004

◆ EXTI_SWIER1_SWI2_Pos

#define EXTI_SWIER1_SWI2_Pos (2U)

◆ EXTI_SWIER1_SWI3

#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk

Software Interrupt on line 3

◆ EXTI_SWIER1_SWI3_Msk

#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos)

0x00000008

◆ EXTI_SWIER1_SWI3_Pos

#define EXTI_SWIER1_SWI3_Pos (3U)

◆ EXTI_SWIER1_SWI4

#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk

Software Interrupt on line 4

◆ EXTI_SWIER1_SWI4_Msk

#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos)

0x00000010

◆ EXTI_SWIER1_SWI4_Pos

#define EXTI_SWIER1_SWI4_Pos (4U)

◆ EXTI_SWIER1_SWI5

#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk

Software Interrupt on line 5

◆ EXTI_SWIER1_SWI5_Msk

#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos)

0x00000020

◆ EXTI_SWIER1_SWI5_Pos

#define EXTI_SWIER1_SWI5_Pos (5U)

◆ EXTI_SWIER1_SWI6

#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk

Software Interrupt on line 6

◆ EXTI_SWIER1_SWI6_Msk

#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos)

0x00000040

◆ EXTI_SWIER1_SWI6_Pos

#define EXTI_SWIER1_SWI6_Pos (6U)

◆ EXTI_SWIER1_SWI7

#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk

Software Interrupt on line 7

◆ EXTI_SWIER1_SWI7_Msk

#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos)

0x00000080

◆ EXTI_SWIER1_SWI7_Pos

#define EXTI_SWIER1_SWI7_Pos (7U)

◆ EXTI_SWIER1_SWI8

#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk

Software Interrupt on line 8

◆ EXTI_SWIER1_SWI8_Msk

#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos)

0x00000100

◆ EXTI_SWIER1_SWI8_Pos

#define EXTI_SWIER1_SWI8_Pos (8U)

◆ EXTI_SWIER1_SWI9

#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk

Software Interrupt on line 9

◆ EXTI_SWIER1_SWI9_Msk

#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos)

0x00000200

◆ EXTI_SWIER1_SWI9_Pos

#define EXTI_SWIER1_SWI9_Pos (9U)

◆ FLASH_ACR_ICEN

#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk

◆ FLASH_ACR_ICEN_Msk

#define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos)

0x00000200

◆ FLASH_ACR_ICEN_Pos

#define FLASH_ACR_ICEN_Pos (9U)

◆ FLASH_ACR_ICRST

#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk

◆ FLASH_ACR_ICRST_Msk

#define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos)

0x00000800

◆ FLASH_ACR_ICRST_Pos

#define FLASH_ACR_ICRST_Pos (11U)

◆ FLASH_ACR_LATENCY

#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk

◆ FLASH_ACR_LATENCY_0

#define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos)

0x00000001

◆ FLASH_ACR_LATENCY_1

#define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos)

0x00000002

◆ FLASH_ACR_LATENCY_2

#define FLASH_ACR_LATENCY_2 (0x4UL << FLASH_ACR_LATENCY_Pos)

0x00000004

◆ FLASH_ACR_LATENCY_Msk

#define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos)

0x00000007

◆ FLASH_ACR_LATENCY_Pos

#define FLASH_ACR_LATENCY_Pos (0U)

◆ FLASH_ACR_PRFTEN

#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk

◆ FLASH_ACR_PRFTEN_Msk

#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos)

0x00000100

◆ FLASH_ACR_PRFTEN_Pos

#define FLASH_ACR_PRFTEN_Pos (8U)

◆ FLASH_ACR_PROGEMPTY

#define FLASH_ACR_PROGEMPTY FLASH_ACR_PROGEMPTY_Msk

◆ FLASH_ACR_PROGEMPTY_Msk

#define FLASH_ACR_PROGEMPTY_Msk (0x1UL << FLASH_ACR_PROGEMPTY_Pos)

0x00010000

◆ FLASH_ACR_PROGEMPTY_Pos

#define FLASH_ACR_PROGEMPTY_Pos (16U)

◆ FLASH_CR_EOPIE

#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk

◆ FLASH_CR_EOPIE_Msk

#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos)

0x01000000

◆ FLASH_CR_EOPIE_Pos

#define FLASH_CR_EOPIE_Pos (24U)

◆ FLASH_CR_ERRIE

#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk

◆ FLASH_CR_ERRIE_Msk

#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos)

0x02000000

◆ FLASH_CR_ERRIE_Pos

#define FLASH_CR_ERRIE_Pos (25U)

◆ FLASH_CR_FSTPG

#define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk

◆ FLASH_CR_FSTPG_Msk

#define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos)

0x00040000

◆ FLASH_CR_FSTPG_Pos

#define FLASH_CR_FSTPG_Pos (18U)

◆ FLASH_CR_LOCK

#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk

◆ FLASH_CR_LOCK_Msk

#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos)

0x80000000

◆ FLASH_CR_LOCK_Pos

#define FLASH_CR_LOCK_Pos (31U)

◆ FLASH_CR_MER1

#define FLASH_CR_MER1 FLASH_CR_MER1_Msk

◆ FLASH_CR_MER1_Msk

#define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos)

0x00000004

◆ FLASH_CR_MER1_Pos

#define FLASH_CR_MER1_Pos (2U)

◆ FLASH_CR_OBL_LAUNCH

#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk

◆ FLASH_CR_OBL_LAUNCH_Msk

#define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos)

0x08000000

◆ FLASH_CR_OBL_LAUNCH_Pos

#define FLASH_CR_OBL_LAUNCH_Pos (27U)

◆ FLASH_CR_OPTLOCK

#define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk

◆ FLASH_CR_OPTLOCK_Msk

#define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos)

0x40000000

◆ FLASH_CR_OPTLOCK_Pos

#define FLASH_CR_OPTLOCK_Pos (30U)

◆ FLASH_CR_OPTSTRT

#define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk

◆ FLASH_CR_OPTSTRT_Msk

#define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos)

0x00020000

◆ FLASH_CR_OPTSTRT_Pos

#define FLASH_CR_OPTSTRT_Pos (17U)

◆ FLASH_CR_PER

#define FLASH_CR_PER FLASH_CR_PER_Msk

◆ FLASH_CR_PER_Msk

#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos)

0x00000002

◆ FLASH_CR_PER_Pos

#define FLASH_CR_PER_Pos (1U)

◆ FLASH_CR_PG

#define FLASH_CR_PG FLASH_CR_PG_Msk

◆ FLASH_CR_PG_Msk

#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos)

0x00000001

◆ FLASH_CR_PG_Pos

#define FLASH_CR_PG_Pos (0U)

◆ FLASH_CR_PNB

#define FLASH_CR_PNB FLASH_CR_PNB_Msk

◆ FLASH_CR_PNB_Msk

#define FLASH_CR_PNB_Msk (0x3FFUL << FLASH_CR_PNB_Pos)

0x00001FF8

◆ FLASH_CR_PNB_Pos

#define FLASH_CR_PNB_Pos (3U)

◆ FLASH_CR_STRT

#define FLASH_CR_STRT FLASH_CR_STRT_Msk

◆ FLASH_CR_STRT_Msk

#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos)

0x00010000

◆ FLASH_CR_STRT_Pos

#define FLASH_CR_STRT_Pos (16U)

◆ FLASH_ECCR_ADDR_ECC

#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk

◆ FLASH_ECCR_ADDR_ECC_Msk

#define FLASH_ECCR_ADDR_ECC_Msk (0x3FFFUL << FLASH_ECCR_ADDR_ECC_Pos)

0x00003FFF

◆ FLASH_ECCR_ADDR_ECC_Pos

#define FLASH_ECCR_ADDR_ECC_Pos (0U)

◆ FLASH_ECCR_ECCC

#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk

◆ FLASH_ECCR_ECCC_Msk

#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos)

0x40000000

◆ FLASH_ECCR_ECCC_Pos

#define FLASH_ECCR_ECCC_Pos (30U)

◆ FLASH_ECCR_ECCCIE

#define FLASH_ECCR_ECCCIE FLASH_ECCR_ECCCIE_Msk

◆ FLASH_ECCR_ECCCIE_Msk

#define FLASH_ECCR_ECCCIE_Msk (0x1UL << FLASH_ECCR_ECCCIE_Pos)

0x01000000

◆ FLASH_ECCR_ECCCIE_Pos

#define FLASH_ECCR_ECCCIE_Pos (24U)

◆ FLASH_ECCR_ECCD

#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk

◆ FLASH_ECCR_ECCD_Msk

#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos)

0x80000000

◆ FLASH_ECCR_ECCD_Pos

#define FLASH_ECCR_ECCD_Pos (31U)

◆ FLASH_ECCR_SYSF_ECC

#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk

◆ FLASH_ECCR_SYSF_ECC_Msk

#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos)

0x00100000

◆ FLASH_ECCR_SYSF_ECC_Pos

#define FLASH_ECCR_SYSF_ECC_Pos (20U)

◆ FLASH_OPTR_IWDG_STDBY

#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk

◆ FLASH_OPTR_IWDG_STDBY_Msk

#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos)

0x00040000

◆ FLASH_OPTR_IWDG_STDBY_Pos

#define FLASH_OPTR_IWDG_STDBY_Pos (18U)

◆ FLASH_OPTR_IWDG_STOP

#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk

◆ FLASH_OPTR_IWDG_STOP_Msk

#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos)

0x00020000

◆ FLASH_OPTR_IWDG_STOP_Pos

#define FLASH_OPTR_IWDG_STOP_Pos (17U)

◆ FLASH_OPTR_IWDG_SW

#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk

◆ FLASH_OPTR_IWDG_SW_Msk

#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos)

0x00010000

◆ FLASH_OPTR_IWDG_SW_Pos

#define FLASH_OPTR_IWDG_SW_Pos (16U)

◆ FLASH_OPTR_nBOOT0

#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk

◆ FLASH_OPTR_nBOOT0_Msk

#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos)

0x04000000

◆ FLASH_OPTR_nBOOT0_Pos

#define FLASH_OPTR_nBOOT0_Pos (26U)

◆ FLASH_OPTR_nBOOT1

#define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk

◆ FLASH_OPTR_nBOOT1_Msk

#define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos)

0x02000000

◆ FLASH_OPTR_nBOOT1_Pos

#define FLASH_OPTR_nBOOT1_Pos (25U)

◆ FLASH_OPTR_nBOOT_SEL

#define FLASH_OPTR_nBOOT_SEL FLASH_OPTR_nBOOT_SEL_Msk

◆ FLASH_OPTR_nBOOT_SEL_Msk

#define FLASH_OPTR_nBOOT_SEL_Msk (0x1UL << FLASH_OPTR_nBOOT_SEL_Pos)

0x01000000

◆ FLASH_OPTR_nBOOT_SEL_Pos

#define FLASH_OPTR_nBOOT_SEL_Pos (24U)

◆ FLASH_OPTR_nRST_STDBY

#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk

◆ FLASH_OPTR_nRST_STDBY_Msk

#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos)

0x00004000

◆ FLASH_OPTR_nRST_STDBY_Pos

#define FLASH_OPTR_nRST_STDBY_Pos (14U)

◆ FLASH_OPTR_nRST_STOP

#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk

◆ FLASH_OPTR_nRST_STOP_Msk

#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos)

0x00002000

◆ FLASH_OPTR_nRST_STOP_Pos

#define FLASH_OPTR_nRST_STOP_Pos (13U)

◆ FLASH_OPTR_RAM_PARITY_CHECK

#define FLASH_OPTR_RAM_PARITY_CHECK FLASH_OPTR_RAM_PARITY_CHECK_Msk

◆ FLASH_OPTR_RAM_PARITY_CHECK_Msk

#define FLASH_OPTR_RAM_PARITY_CHECK_Msk (0x1UL << FLASH_OPTR_RAM_PARITY_CHECK_Pos)

0x00400000

◆ FLASH_OPTR_RAM_PARITY_CHECK_Pos

#define FLASH_OPTR_RAM_PARITY_CHECK_Pos (22U)

◆ FLASH_OPTR_RDP

#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk

◆ FLASH_OPTR_RDP_Msk

#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos)

0x000000FF

◆ FLASH_OPTR_RDP_Pos

#define FLASH_OPTR_RDP_Pos (0U)

◆ FLASH_OPTR_WWDG_SW

#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk

◆ FLASH_OPTR_WWDG_SW_Msk

#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos)

0x00080000

◆ FLASH_OPTR_WWDG_SW_Pos

#define FLASH_OPTR_WWDG_SW_Pos (19U)

◆ FLASH_SR_BSY1

#define FLASH_SR_BSY1 FLASH_SR_BSY1_Msk

◆ FLASH_SR_BSY1_Msk

#define FLASH_SR_BSY1_Msk (0x1UL << FLASH_SR_BSY1_Pos)

0x00010000

◆ FLASH_SR_BSY1_Pos

#define FLASH_SR_BSY1_Pos (16U)

◆ FLASH_SR_CFGBSY

#define FLASH_SR_CFGBSY FLASH_SR_CFGBSY_Msk

◆ FLASH_SR_CFGBSY_Msk

#define FLASH_SR_CFGBSY_Msk (0x1UL << FLASH_SR_CFGBSY_Pos)

0x00040000

◆ FLASH_SR_CFGBSY_Pos

#define FLASH_SR_CFGBSY_Pos (18U)

◆ FLASH_SR_EOP

#define FLASH_SR_EOP FLASH_SR_EOP_Msk

◆ FLASH_SR_EOP_Msk

#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos)

0x00000001

◆ FLASH_SR_EOP_Pos

#define FLASH_SR_EOP_Pos (0U)

◆ FLASH_SR_FASTERR

#define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk

◆ FLASH_SR_FASTERR_Msk

#define FLASH_SR_FASTERR_Msk (0x1UL << FLASH_SR_FASTERR_Pos)

0x00000200

◆ FLASH_SR_FASTERR_Pos

#define FLASH_SR_FASTERR_Pos (9U)

◆ FLASH_SR_MISERR

#define FLASH_SR_MISERR FLASH_SR_MISERR_Msk

◆ FLASH_SR_MISERR_Msk

#define FLASH_SR_MISERR_Msk (0x1UL << FLASH_SR_MISERR_Pos)

0x00000100

◆ FLASH_SR_MISERR_Pos

#define FLASH_SR_MISERR_Pos (8U)

◆ FLASH_SR_OPERR

#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk

◆ FLASH_SR_OPERR_Msk

#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos)

0x00000002

◆ FLASH_SR_OPERR_Pos

#define FLASH_SR_OPERR_Pos (1U)

◆ FLASH_SR_OPTVERR

#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk

◆ FLASH_SR_OPTVERR_Msk

#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos)

0x00008000

◆ FLASH_SR_OPTVERR_Pos

#define FLASH_SR_OPTVERR_Pos (15U)

◆ FLASH_SR_PGAERR

#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk

◆ FLASH_SR_PGAERR_Msk

#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos)

0x00000020

◆ FLASH_SR_PGAERR_Pos

#define FLASH_SR_PGAERR_Pos (5U)

◆ FLASH_SR_PGSERR

#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk

◆ FLASH_SR_PGSERR_Msk

#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos)

0x00000080

◆ FLASH_SR_PGSERR_Pos

#define FLASH_SR_PGSERR_Pos (7U)

◆ FLASH_SR_PROGERR

#define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk

◆ FLASH_SR_PROGERR_Msk

#define FLASH_SR_PROGERR_Msk (0x1UL << FLASH_SR_PROGERR_Pos)

0x00000008

◆ FLASH_SR_PROGERR_Pos

#define FLASH_SR_PROGERR_Pos (3U)

◆ FLASH_SR_SIZERR

#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk

◆ FLASH_SR_SIZERR_Msk

#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos)

0x00000040

◆ FLASH_SR_SIZERR_Pos

#define FLASH_SR_SIZERR_Pos (6U)

◆ FLASH_SR_WRPERR

#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk

◆ FLASH_SR_WRPERR_Msk

#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos)

0x00000010

◆ FLASH_SR_WRPERR_Pos

#define FLASH_SR_WRPERR_Pos (4U)

◆ FLASH_WRP1AR_WRP1A_END

#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk

◆ FLASH_WRP1AR_WRP1A_END_Msk

#define FLASH_WRP1AR_WRP1A_END_Msk (0x1FUL << FLASH_WRP1AR_WRP1A_END_Pos)

0x001F0000

◆ FLASH_WRP1AR_WRP1A_END_Pos

#define FLASH_WRP1AR_WRP1A_END_Pos (16U)

◆ FLASH_WRP1AR_WRP1A_STRT

#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk

◆ FLASH_WRP1AR_WRP1A_STRT_Msk

#define FLASH_WRP1AR_WRP1A_STRT_Msk (0x1FUL << FLASH_WRP1AR_WRP1A_STRT_Pos)

0x0000001F

◆ FLASH_WRP1AR_WRP1A_STRT_Pos

#define FLASH_WRP1AR_WRP1A_STRT_Pos (0U)

◆ FLASH_WRP1BR_WRP1B_END

#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk

◆ FLASH_WRP1BR_WRP1B_END_Msk

#define FLASH_WRP1BR_WRP1B_END_Msk (0x1FUL << FLASH_WRP1BR_WRP1B_END_Pos)

0x001F0000

◆ FLASH_WRP1BR_WRP1B_END_Pos

#define FLASH_WRP1BR_WRP1B_END_Pos (16U)

◆ FLASH_WRP1BR_WRP1B_STRT

#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk

◆ FLASH_WRP1BR_WRP1B_STRT_Msk

#define FLASH_WRP1BR_WRP1B_STRT_Msk (0x1FUL << FLASH_WRP1BR_WRP1B_STRT_Pos)

0x0000001F

◆ FLASH_WRP1BR_WRP1B_STRT_Pos

#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U)

◆ GPIO_AFRH_AFSEL10

#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk

◆ GPIO_AFRH_AFSEL10_0

#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos)

0x00000100

◆ GPIO_AFRH_AFSEL10_1

#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos)

0x00000200

◆ GPIO_AFRH_AFSEL10_2

#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos)

0x00000400

◆ GPIO_AFRH_AFSEL10_3

#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos)

0x00000800

◆ GPIO_AFRH_AFSEL10_Msk

#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos)

0x00000F00

◆ GPIO_AFRH_AFSEL10_Pos

#define GPIO_AFRH_AFSEL10_Pos (8U)

◆ GPIO_AFRH_AFSEL11

#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk

◆ GPIO_AFRH_AFSEL11_0

#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos)

0x00001000

◆ GPIO_AFRH_AFSEL11_1

#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos)

0x00002000

◆ GPIO_AFRH_AFSEL11_2

#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos)

0x00004000

◆ GPIO_AFRH_AFSEL11_3

#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos)

0x00008000

◆ GPIO_AFRH_AFSEL11_Msk

#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos)

0x0000F000

◆ GPIO_AFRH_AFSEL11_Pos

#define GPIO_AFRH_AFSEL11_Pos (12U)

◆ GPIO_AFRH_AFSEL12

#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk

◆ GPIO_AFRH_AFSEL12_0

#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos)

0x00010000

◆ GPIO_AFRH_AFSEL12_1

#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos)

0x00020000

◆ GPIO_AFRH_AFSEL12_2

#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos)

0x00040000

◆ GPIO_AFRH_AFSEL12_3

#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos)

0x00080000

◆ GPIO_AFRH_AFSEL12_Msk

#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos)

0x000F0000

◆ GPIO_AFRH_AFSEL12_Pos

#define GPIO_AFRH_AFSEL12_Pos (16U)

◆ GPIO_AFRH_AFSEL13

#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk

◆ GPIO_AFRH_AFSEL13_0

#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos)

0x00100000

◆ GPIO_AFRH_AFSEL13_1

#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos)

0x00200000

◆ GPIO_AFRH_AFSEL13_2

#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos)

0x00400000

◆ GPIO_AFRH_AFSEL13_3

#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos)

0x00800000

◆ GPIO_AFRH_AFSEL13_Msk

#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos)

0x00F00000

◆ GPIO_AFRH_AFSEL13_Pos

#define GPIO_AFRH_AFSEL13_Pos (20U)

◆ GPIO_AFRH_AFSEL14

#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk

◆ GPIO_AFRH_AFSEL14_0

#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos)

0x01000000

◆ GPIO_AFRH_AFSEL14_1

#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos)

0x02000000

◆ GPIO_AFRH_AFSEL14_2

#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos)

0x04000000

◆ GPIO_AFRH_AFSEL14_3

#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos)

0x08000000

◆ GPIO_AFRH_AFSEL14_Msk

#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos)

0x0F000000

◆ GPIO_AFRH_AFSEL14_Pos

#define GPIO_AFRH_AFSEL14_Pos (24U)

◆ GPIO_AFRH_AFSEL15

#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk

◆ GPIO_AFRH_AFSEL15_0

#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos)

0x10000000

◆ GPIO_AFRH_AFSEL15_1

#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos)

0x20000000

◆ GPIO_AFRH_AFSEL15_2

#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos)

0x40000000

◆ GPIO_AFRH_AFSEL15_3

#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos)

0x80000000

◆ GPIO_AFRH_AFSEL15_Msk

#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos)

0xF0000000

◆ GPIO_AFRH_AFSEL15_Pos

#define GPIO_AFRH_AFSEL15_Pos (28U)

◆ GPIO_AFRH_AFSEL8

#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk

◆ GPIO_AFRH_AFSEL8_0

#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos)

0x00000001

◆ GPIO_AFRH_AFSEL8_1

#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos)

0x00000002

◆ GPIO_AFRH_AFSEL8_2

#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos)

0x00000004

◆ GPIO_AFRH_AFSEL8_3

#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos)

0x00000008

◆ GPIO_AFRH_AFSEL8_Msk

#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos)

0x0000000F

◆ GPIO_AFRH_AFSEL8_Pos

#define GPIO_AFRH_AFSEL8_Pos (0U)

◆ GPIO_AFRH_AFSEL9

#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk

◆ GPIO_AFRH_AFSEL9_0

#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos)

0x00000010

◆ GPIO_AFRH_AFSEL9_1

#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos)

0x00000020

◆ GPIO_AFRH_AFSEL9_2

#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos)

0x00000040

◆ GPIO_AFRH_AFSEL9_3

#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos)

0x00000080

◆ GPIO_AFRH_AFSEL9_Msk

#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos)

0x000000F0

◆ GPIO_AFRH_AFSEL9_Pos

#define GPIO_AFRH_AFSEL9_Pos (4U)

◆ GPIO_AFRL_AFSEL0

#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk

◆ GPIO_AFRL_AFSEL0_0

#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos)

0x00000001

◆ GPIO_AFRL_AFSEL0_1

#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos)

0x00000002

◆ GPIO_AFRL_AFSEL0_2

#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos)

0x00000004

◆ GPIO_AFRL_AFSEL0_3

#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos)

0x00000008

◆ GPIO_AFRL_AFSEL0_Msk

#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos)

0x0000000F

◆ GPIO_AFRL_AFSEL0_Pos

#define GPIO_AFRL_AFSEL0_Pos (0U)

◆ GPIO_AFRL_AFSEL1

#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk

◆ GPIO_AFRL_AFSEL1_0

#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos)

0x00000010

◆ GPIO_AFRL_AFSEL1_1

#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos)

0x00000020

◆ GPIO_AFRL_AFSEL1_2

#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos)

0x00000040

◆ GPIO_AFRL_AFSEL1_3

#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos)

0x00000080

◆ GPIO_AFRL_AFSEL1_Msk

#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos)

0x000000F0

◆ GPIO_AFRL_AFSEL1_Pos

#define GPIO_AFRL_AFSEL1_Pos (4U)

◆ GPIO_AFRL_AFSEL2

#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk

◆ GPIO_AFRL_AFSEL2_0

#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos)

0x00000100

◆ GPIO_AFRL_AFSEL2_1

#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos)

0x00000200

◆ GPIO_AFRL_AFSEL2_2

#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos)

0x00000400

◆ GPIO_AFRL_AFSEL2_3

#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos)

0x00000800

◆ GPIO_AFRL_AFSEL2_Msk

#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos)

0x00000F00

◆ GPIO_AFRL_AFSEL2_Pos

#define GPIO_AFRL_AFSEL2_Pos (8U)

◆ GPIO_AFRL_AFSEL3

#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk

◆ GPIO_AFRL_AFSEL3_0

#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos)

0x00001000

◆ GPIO_AFRL_AFSEL3_1

#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos)

0x00002000

◆ GPIO_AFRL_AFSEL3_2

#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos)

0x00004000

◆ GPIO_AFRL_AFSEL3_3

#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos)

0x00008000

◆ GPIO_AFRL_AFSEL3_Msk

#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos)

0x0000F000

◆ GPIO_AFRL_AFSEL3_Pos

#define GPIO_AFRL_AFSEL3_Pos (12U)

◆ GPIO_AFRL_AFSEL4

#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk

◆ GPIO_AFRL_AFSEL4_0

#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos)

0x00010000

◆ GPIO_AFRL_AFSEL4_1

#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos)

0x00020000

◆ GPIO_AFRL_AFSEL4_2

#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos)

0x00040000

◆ GPIO_AFRL_AFSEL4_3

#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos)

0x00080000

◆ GPIO_AFRL_AFSEL4_Msk

#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos)

0x000F0000

◆ GPIO_AFRL_AFSEL4_Pos

#define GPIO_AFRL_AFSEL4_Pos (16U)

◆ GPIO_AFRL_AFSEL5

#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk

◆ GPIO_AFRL_AFSEL5_0

#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos)

0x00100000

◆ GPIO_AFRL_AFSEL5_1

#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos)

0x00200000

◆ GPIO_AFRL_AFSEL5_2

#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos)

0x00400000

◆ GPIO_AFRL_AFSEL5_3

#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos)

0x00800000

◆ GPIO_AFRL_AFSEL5_Msk

#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos)

0x00F00000

◆ GPIO_AFRL_AFSEL5_Pos

#define GPIO_AFRL_AFSEL5_Pos (20U)

◆ GPIO_AFRL_AFSEL6

#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk

◆ GPIO_AFRL_AFSEL6_0

#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos)

0x01000000

◆ GPIO_AFRL_AFSEL6_1

#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos)

0x02000000

◆ GPIO_AFRL_AFSEL6_2

#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos)

0x04000000

◆ GPIO_AFRL_AFSEL6_3

#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos)

0x08000000

◆ GPIO_AFRL_AFSEL6_Msk

#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos)

0x0F000000

◆ GPIO_AFRL_AFSEL6_Pos

#define GPIO_AFRL_AFSEL6_Pos (24U)

◆ GPIO_AFRL_AFSEL7

#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk

◆ GPIO_AFRL_AFSEL7_0

#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos)

0x10000000

◆ GPIO_AFRL_AFSEL7_1

#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos)

0x20000000

◆ GPIO_AFRL_AFSEL7_2

#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos)

0x40000000

◆ GPIO_AFRL_AFSEL7_3

#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos)

0x80000000

◆ GPIO_AFRL_AFSEL7_Msk

#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos)

0xF0000000

◆ GPIO_AFRL_AFSEL7_Pos

#define GPIO_AFRL_AFSEL7_Pos (28U)

◆ GPIO_BRR_BR0

#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk

◆ GPIO_BRR_BR0_Msk

#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos)

0x00000001

◆ GPIO_BRR_BR0_Pos

#define GPIO_BRR_BR0_Pos (0U)

◆ GPIO_BRR_BR1

#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk

◆ GPIO_BRR_BR10

#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk

◆ GPIO_BRR_BR10_Msk

#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos)

0x00000400

◆ GPIO_BRR_BR10_Pos

#define GPIO_BRR_BR10_Pos (10U)

◆ GPIO_BRR_BR11

#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk

◆ GPIO_BRR_BR11_Msk

#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos)

0x00000800

◆ GPIO_BRR_BR11_Pos

#define GPIO_BRR_BR11_Pos (11U)

◆ GPIO_BRR_BR12

#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk

◆ GPIO_BRR_BR12_Msk

#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos)

0x00001000

◆ GPIO_BRR_BR12_Pos

#define GPIO_BRR_BR12_Pos (12U)

◆ GPIO_BRR_BR13

#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk

◆ GPIO_BRR_BR13_Msk

#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos)

0x00002000

◆ GPIO_BRR_BR13_Pos

#define GPIO_BRR_BR13_Pos (13U)

◆ GPIO_BRR_BR14

#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk

◆ GPIO_BRR_BR14_Msk

#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos)

0x00004000

◆ GPIO_BRR_BR14_Pos

#define GPIO_BRR_BR14_Pos (14U)

◆ GPIO_BRR_BR15

#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk

◆ GPIO_BRR_BR15_Msk

#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos)

0x00008000

◆ GPIO_BRR_BR15_Pos

#define GPIO_BRR_BR15_Pos (15U)

◆ GPIO_BRR_BR1_Msk

#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos)

0x00000002

◆ GPIO_BRR_BR1_Pos

#define GPIO_BRR_BR1_Pos (1U)

◆ GPIO_BRR_BR2

#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk

◆ GPIO_BRR_BR2_Msk

#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos)

0x00000004

◆ GPIO_BRR_BR2_Pos

#define GPIO_BRR_BR2_Pos (2U)

◆ GPIO_BRR_BR3

#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk

◆ GPIO_BRR_BR3_Msk

#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos)

0x00000008

◆ GPIO_BRR_BR3_Pos

#define GPIO_BRR_BR3_Pos (3U)

◆ GPIO_BRR_BR4

#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk

◆ GPIO_BRR_BR4_Msk

#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos)

0x00000010

◆ GPIO_BRR_BR4_Pos

#define GPIO_BRR_BR4_Pos (4U)

◆ GPIO_BRR_BR5

#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk

◆ GPIO_BRR_BR5_Msk

#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos)

0x00000020

◆ GPIO_BRR_BR5_Pos

#define GPIO_BRR_BR5_Pos (5U)

◆ GPIO_BRR_BR6

#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk

◆ GPIO_BRR_BR6_Msk

#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos)

0x00000040

◆ GPIO_BRR_BR6_Pos

#define GPIO_BRR_BR6_Pos (6U)

◆ GPIO_BRR_BR7

#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk

◆ GPIO_BRR_BR7_Msk

#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos)

0x00000080

◆ GPIO_BRR_BR7_Pos

#define GPIO_BRR_BR7_Pos (7U)

◆ GPIO_BRR_BR8

#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk

◆ GPIO_BRR_BR8_Msk

#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos)

0x00000100

◆ GPIO_BRR_BR8_Pos

#define GPIO_BRR_BR8_Pos (8U)

◆ GPIO_BRR_BR9

#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk

◆ GPIO_BRR_BR9_Msk

#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos)

0x00000200

◆ GPIO_BRR_BR9_Pos

#define GPIO_BRR_BR9_Pos (9U)

◆ GPIO_BSRR_BR0

#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk

◆ GPIO_BSRR_BR0_Msk

#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos)

0x00010000

◆ GPIO_BSRR_BR0_Pos

#define GPIO_BSRR_BR0_Pos (16U)

◆ GPIO_BSRR_BR1

#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk

◆ GPIO_BSRR_BR10

#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk

◆ GPIO_BSRR_BR10_Msk

#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos)

0x04000000

◆ GPIO_BSRR_BR10_Pos

#define GPIO_BSRR_BR10_Pos (26U)

◆ GPIO_BSRR_BR11

#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk

◆ GPIO_BSRR_BR11_Msk

#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos)

0x08000000

◆ GPIO_BSRR_BR11_Pos

#define GPIO_BSRR_BR11_Pos (27U)

◆ GPIO_BSRR_BR12

#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk

◆ GPIO_BSRR_BR12_Msk

#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos)

0x10000000

◆ GPIO_BSRR_BR12_Pos

#define GPIO_BSRR_BR12_Pos (28U)

◆ GPIO_BSRR_BR13

#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk

◆ GPIO_BSRR_BR13_Msk

#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos)

0x20000000

◆ GPIO_BSRR_BR13_Pos

#define GPIO_BSRR_BR13_Pos (29U)

◆ GPIO_BSRR_BR14

#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk

◆ GPIO_BSRR_BR14_Msk

#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos)

0x40000000

◆ GPIO_BSRR_BR14_Pos

#define GPIO_BSRR_BR14_Pos (30U)

◆ GPIO_BSRR_BR15

#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk

◆ GPIO_BSRR_BR15_Msk

#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos)

0x80000000

◆ GPIO_BSRR_BR15_Pos

#define GPIO_BSRR_BR15_Pos (31U)

◆ GPIO_BSRR_BR1_Msk

#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos)

0x00020000

◆ GPIO_BSRR_BR1_Pos

#define GPIO_BSRR_BR1_Pos (17U)

◆ GPIO_BSRR_BR2

#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk

◆ GPIO_BSRR_BR2_Msk

#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos)

0x00040000

◆ GPIO_BSRR_BR2_Pos

#define GPIO_BSRR_BR2_Pos (18U)

◆ GPIO_BSRR_BR3

#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk

◆ GPIO_BSRR_BR3_Msk

#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos)

0x00080000

◆ GPIO_BSRR_BR3_Pos

#define GPIO_BSRR_BR3_Pos (19U)

◆ GPIO_BSRR_BR4

#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk

◆ GPIO_BSRR_BR4_Msk

#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos)

0x00100000

◆ GPIO_BSRR_BR4_Pos

#define GPIO_BSRR_BR4_Pos (20U)

◆ GPIO_BSRR_BR5

#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk

◆ GPIO_BSRR_BR5_Msk

#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos)

0x00200000

◆ GPIO_BSRR_BR5_Pos

#define GPIO_BSRR_BR5_Pos (21U)

◆ GPIO_BSRR_BR6

#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk

◆ GPIO_BSRR_BR6_Msk

#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos)

0x00400000

◆ GPIO_BSRR_BR6_Pos

#define GPIO_BSRR_BR6_Pos (22U)

◆ GPIO_BSRR_BR7

#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk

◆ GPIO_BSRR_BR7_Msk

#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos)

0x00800000

◆ GPIO_BSRR_BR7_Pos

#define GPIO_BSRR_BR7_Pos (23U)

◆ GPIO_BSRR_BR8

#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk

◆ GPIO_BSRR_BR8_Msk

#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos)

0x01000000

◆ GPIO_BSRR_BR8_Pos

#define GPIO_BSRR_BR8_Pos (24U)

◆ GPIO_BSRR_BR9

#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk

◆ GPIO_BSRR_BR9_Msk

#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos)

0x02000000

◆ GPIO_BSRR_BR9_Pos

#define GPIO_BSRR_BR9_Pos (25U)

◆ GPIO_BSRR_BS0

#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk

◆ GPIO_BSRR_BS0_Msk

#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos)

0x00000001

◆ GPIO_BSRR_BS0_Pos

#define GPIO_BSRR_BS0_Pos (0U)

◆ GPIO_BSRR_BS1

#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk

◆ GPIO_BSRR_BS10

#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk

◆ GPIO_BSRR_BS10_Msk

#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos)

0x00000400

◆ GPIO_BSRR_BS10_Pos

#define GPIO_BSRR_BS10_Pos (10U)

◆ GPIO_BSRR_BS11

#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk

◆ GPIO_BSRR_BS11_Msk

#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos)

0x00000800

◆ GPIO_BSRR_BS11_Pos

#define GPIO_BSRR_BS11_Pos (11U)

◆ GPIO_BSRR_BS12

#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk

◆ GPIO_BSRR_BS12_Msk

#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos)

0x00001000

◆ GPIO_BSRR_BS12_Pos

#define GPIO_BSRR_BS12_Pos (12U)

◆ GPIO_BSRR_BS13

#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk

◆ GPIO_BSRR_BS13_Msk

#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos)

0x00002000

◆ GPIO_BSRR_BS13_Pos

#define GPIO_BSRR_BS13_Pos (13U)

◆ GPIO_BSRR_BS14

#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk

◆ GPIO_BSRR_BS14_Msk

#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos)

0x00004000

◆ GPIO_BSRR_BS14_Pos

#define GPIO_BSRR_BS14_Pos (14U)

◆ GPIO_BSRR_BS15

#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk

◆ GPIO_BSRR_BS15_Msk

#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos)

0x00008000

◆ GPIO_BSRR_BS15_Pos

#define GPIO_BSRR_BS15_Pos (15U)

◆ GPIO_BSRR_BS1_Msk

#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos)

0x00000002

◆ GPIO_BSRR_BS1_Pos

#define GPIO_BSRR_BS1_Pos (1U)

◆ GPIO_BSRR_BS2

#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk

◆ GPIO_BSRR_BS2_Msk

#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos)

0x00000004

◆ GPIO_BSRR_BS2_Pos

#define GPIO_BSRR_BS2_Pos (2U)

◆ GPIO_BSRR_BS3

#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk

◆ GPIO_BSRR_BS3_Msk

#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos)

0x00000008

◆ GPIO_BSRR_BS3_Pos

#define GPIO_BSRR_BS3_Pos (3U)

◆ GPIO_BSRR_BS4

#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk

◆ GPIO_BSRR_BS4_Msk

#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos)

0x00000010

◆ GPIO_BSRR_BS4_Pos

#define GPIO_BSRR_BS4_Pos (4U)

◆ GPIO_BSRR_BS5

#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk

◆ GPIO_BSRR_BS5_Msk

#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos)

0x00000020

◆ GPIO_BSRR_BS5_Pos

#define GPIO_BSRR_BS5_Pos (5U)

◆ GPIO_BSRR_BS6

#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk

◆ GPIO_BSRR_BS6_Msk

#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos)

0x00000040

◆ GPIO_BSRR_BS6_Pos

#define GPIO_BSRR_BS6_Pos (6U)

◆ GPIO_BSRR_BS7

#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk

◆ GPIO_BSRR_BS7_Msk

#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos)

0x00000080

◆ GPIO_BSRR_BS7_Pos

#define GPIO_BSRR_BS7_Pos (7U)

◆ GPIO_BSRR_BS8

#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk

◆ GPIO_BSRR_BS8_Msk

#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos)

0x00000100

◆ GPIO_BSRR_BS8_Pos

#define GPIO_BSRR_BS8_Pos (8U)

◆ GPIO_BSRR_BS9

#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk

◆ GPIO_BSRR_BS9_Msk

#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos)

0x00000200

◆ GPIO_BSRR_BS9_Pos

#define GPIO_BSRR_BS9_Pos (9U)

◆ GPIO_IDR_ID0

#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk

◆ GPIO_IDR_ID0_Msk

#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos)

0x00000001

◆ GPIO_IDR_ID0_Pos

#define GPIO_IDR_ID0_Pos (0U)

◆ GPIO_IDR_ID1

#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk

◆ GPIO_IDR_ID10

#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk

◆ GPIO_IDR_ID10_Msk

#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos)

0x00000400

◆ GPIO_IDR_ID10_Pos

#define GPIO_IDR_ID10_Pos (10U)

◆ GPIO_IDR_ID11

#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk

◆ GPIO_IDR_ID11_Msk

#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos)

0x00000800

◆ GPIO_IDR_ID11_Pos

#define GPIO_IDR_ID11_Pos (11U)

◆ GPIO_IDR_ID12

#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk

◆ GPIO_IDR_ID12_Msk

#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos)

0x00001000

◆ GPIO_IDR_ID12_Pos

#define GPIO_IDR_ID12_Pos (12U)

◆ GPIO_IDR_ID13

#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk

◆ GPIO_IDR_ID13_Msk

#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos)

0x00002000

◆ GPIO_IDR_ID13_Pos

#define GPIO_IDR_ID13_Pos (13U)

◆ GPIO_IDR_ID14

#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk

◆ GPIO_IDR_ID14_Msk

#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos)

0x00004000

◆ GPIO_IDR_ID14_Pos

#define GPIO_IDR_ID14_Pos (14U)

◆ GPIO_IDR_ID15

#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk

◆ GPIO_IDR_ID15_Msk

#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos)

0x00008000

◆ GPIO_IDR_ID15_Pos

#define GPIO_IDR_ID15_Pos (15U)

◆ GPIO_IDR_ID1_Msk

#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos)

0x00000002

◆ GPIO_IDR_ID1_Pos

#define GPIO_IDR_ID1_Pos (1U)

◆ GPIO_IDR_ID2

#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk

◆ GPIO_IDR_ID2_Msk

#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos)

0x00000004

◆ GPIO_IDR_ID2_Pos

#define GPIO_IDR_ID2_Pos (2U)

◆ GPIO_IDR_ID3

#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk

◆ GPIO_IDR_ID3_Msk

#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos)

0x00000008

◆ GPIO_IDR_ID3_Pos

#define GPIO_IDR_ID3_Pos (3U)

◆ GPIO_IDR_ID4

#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk

◆ GPIO_IDR_ID4_Msk

#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos)

0x00000010

◆ GPIO_IDR_ID4_Pos

#define GPIO_IDR_ID4_Pos (4U)

◆ GPIO_IDR_ID5

#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk

◆ GPIO_IDR_ID5_Msk

#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos)

0x00000020

◆ GPIO_IDR_ID5_Pos

#define GPIO_IDR_ID5_Pos (5U)

◆ GPIO_IDR_ID6

#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk

◆ GPIO_IDR_ID6_Msk

#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos)

0x00000040

◆ GPIO_IDR_ID6_Pos

#define GPIO_IDR_ID6_Pos (6U)

◆ GPIO_IDR_ID7

#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk

◆ GPIO_IDR_ID7_Msk

#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos)

0x00000080

◆ GPIO_IDR_ID7_Pos

#define GPIO_IDR_ID7_Pos (7U)

◆ GPIO_IDR_ID8

#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk

◆ GPIO_IDR_ID8_Msk

#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos)

0x00000100

◆ GPIO_IDR_ID8_Pos

#define GPIO_IDR_ID8_Pos (8U)

◆ GPIO_IDR_ID9

#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk

◆ GPIO_IDR_ID9_Msk

#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos)

0x00000200

◆ GPIO_IDR_ID9_Pos

#define GPIO_IDR_ID9_Pos (9U)

◆ GPIO_LCKR_LCK0

#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk

◆ GPIO_LCKR_LCK0_Msk

#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos)

0x00000001

◆ GPIO_LCKR_LCK0_Pos

#define GPIO_LCKR_LCK0_Pos (0U)

◆ GPIO_LCKR_LCK1

#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk

◆ GPIO_LCKR_LCK10

#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk

◆ GPIO_LCKR_LCK10_Msk

#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos)

0x00000400

◆ GPIO_LCKR_LCK10_Pos

#define GPIO_LCKR_LCK10_Pos (10U)

◆ GPIO_LCKR_LCK11

#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk

◆ GPIO_LCKR_LCK11_Msk

#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos)

0x00000800

◆ GPIO_LCKR_LCK11_Pos

#define GPIO_LCKR_LCK11_Pos (11U)

◆ GPIO_LCKR_LCK12

#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk

◆ GPIO_LCKR_LCK12_Msk

#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos)

0x00001000

◆ GPIO_LCKR_LCK12_Pos

#define GPIO_LCKR_LCK12_Pos (12U)

◆ GPIO_LCKR_LCK13

#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk

◆ GPIO_LCKR_LCK13_Msk

#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos)

0x00002000

◆ GPIO_LCKR_LCK13_Pos

#define GPIO_LCKR_LCK13_Pos (13U)

◆ GPIO_LCKR_LCK14

#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk

◆ GPIO_LCKR_LCK14_Msk

#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos)

0x00004000

◆ GPIO_LCKR_LCK14_Pos

#define GPIO_LCKR_LCK14_Pos (14U)

◆ GPIO_LCKR_LCK15

#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk

◆ GPIO_LCKR_LCK15_Msk

#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos)

0x00008000

◆ GPIO_LCKR_LCK15_Pos

#define GPIO_LCKR_LCK15_Pos (15U)

◆ GPIO_LCKR_LCK1_Msk

#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos)

0x00000002

◆ GPIO_LCKR_LCK1_Pos

#define GPIO_LCKR_LCK1_Pos (1U)

◆ GPIO_LCKR_LCK2

#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk

◆ GPIO_LCKR_LCK2_Msk

#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos)

0x00000004

◆ GPIO_LCKR_LCK2_Pos

#define GPIO_LCKR_LCK2_Pos (2U)

◆ GPIO_LCKR_LCK3

#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk

◆ GPIO_LCKR_LCK3_Msk

#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos)

0x00000008

◆ GPIO_LCKR_LCK3_Pos

#define GPIO_LCKR_LCK3_Pos (3U)

◆ GPIO_LCKR_LCK4

#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk

◆ GPIO_LCKR_LCK4_Msk

#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos)

0x00000010

◆ GPIO_LCKR_LCK4_Pos

#define GPIO_LCKR_LCK4_Pos (4U)

◆ GPIO_LCKR_LCK5

#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk

◆ GPIO_LCKR_LCK5_Msk

#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos)

0x00000020

◆ GPIO_LCKR_LCK5_Pos

#define GPIO_LCKR_LCK5_Pos (5U)

◆ GPIO_LCKR_LCK6

#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk

◆ GPIO_LCKR_LCK6_Msk

#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos)

0x00000040

◆ GPIO_LCKR_LCK6_Pos

#define GPIO_LCKR_LCK6_Pos (6U)

◆ GPIO_LCKR_LCK7

#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk

◆ GPIO_LCKR_LCK7_Msk

#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos)

0x00000080

◆ GPIO_LCKR_LCK7_Pos

#define GPIO_LCKR_LCK7_Pos (7U)

◆ GPIO_LCKR_LCK8

#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk

◆ GPIO_LCKR_LCK8_Msk

#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos)

0x00000100

◆ GPIO_LCKR_LCK8_Pos

#define GPIO_LCKR_LCK8_Pos (8U)

◆ GPIO_LCKR_LCK9

#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk

◆ GPIO_LCKR_LCK9_Msk

#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos)

0x00000200

◆ GPIO_LCKR_LCK9_Pos

#define GPIO_LCKR_LCK9_Pos (9U)

◆ GPIO_LCKR_LCKK

#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk

◆ GPIO_LCKR_LCKK_Msk

#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos)

0x00010000

◆ GPIO_LCKR_LCKK_Pos

#define GPIO_LCKR_LCKK_Pos (16U)

◆ GPIO_MODER_MODE0

#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk

◆ GPIO_MODER_MODE0_0

#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos)

0x00000001

◆ GPIO_MODER_MODE0_1

#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos)

0x00000002

◆ GPIO_MODER_MODE0_Msk

#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos)

0x00000003

◆ GPIO_MODER_MODE0_Pos

#define GPIO_MODER_MODE0_Pos (0U)

◆ GPIO_MODER_MODE1

#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk

◆ GPIO_MODER_MODE10

#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk

◆ GPIO_MODER_MODE10_0

#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos)

0x00100000

◆ GPIO_MODER_MODE10_1

#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos)

0x00200000

◆ GPIO_MODER_MODE10_Msk

#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos)

0x00300000

◆ GPIO_MODER_MODE10_Pos

#define GPIO_MODER_MODE10_Pos (20U)

◆ GPIO_MODER_MODE11

#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk

◆ GPIO_MODER_MODE11_0

#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos)

0x00400000

◆ GPIO_MODER_MODE11_1

#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos)

0x00800000

◆ GPIO_MODER_MODE11_Msk

#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos)

0x00C00000

◆ GPIO_MODER_MODE11_Pos

#define GPIO_MODER_MODE11_Pos (22U)

◆ GPIO_MODER_MODE12

#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk

◆ GPIO_MODER_MODE12_0

#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos)

0x01000000

◆ GPIO_MODER_MODE12_1

#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos)

0x02000000

◆ GPIO_MODER_MODE12_Msk

#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos)

0x03000000

◆ GPIO_MODER_MODE12_Pos

#define GPIO_MODER_MODE12_Pos (24U)

◆ GPIO_MODER_MODE13

#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk

◆ GPIO_MODER_MODE13_0

#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos)

0x04000000

◆ GPIO_MODER_MODE13_1

#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos)

0x08000000

◆ GPIO_MODER_MODE13_Msk

#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos)

0x0C000000

◆ GPIO_MODER_MODE13_Pos

#define GPIO_MODER_MODE13_Pos (26U)

◆ GPIO_MODER_MODE14

#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk

◆ GPIO_MODER_MODE14_0

#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos)

0x10000000

◆ GPIO_MODER_MODE14_1

#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos)

0x20000000

◆ GPIO_MODER_MODE14_Msk

#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos)

0x30000000

◆ GPIO_MODER_MODE14_Pos

#define GPIO_MODER_MODE14_Pos (28U)

◆ GPIO_MODER_MODE15

#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk

◆ GPIO_MODER_MODE15_0

#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos)

0x40000000

◆ GPIO_MODER_MODE15_1

#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos)

0x80000000

◆ GPIO_MODER_MODE15_Msk

#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos)

0xC0000000

◆ GPIO_MODER_MODE15_Pos

#define GPIO_MODER_MODE15_Pos (30U)

◆ GPIO_MODER_MODE1_0

#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos)

0x00000004

◆ GPIO_MODER_MODE1_1

#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos)

0x00000008

◆ GPIO_MODER_MODE1_Msk

#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos)

0x0000000C

◆ GPIO_MODER_MODE1_Pos

#define GPIO_MODER_MODE1_Pos (2U)

◆ GPIO_MODER_MODE2

#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk

◆ GPIO_MODER_MODE2_0

#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos)

0x00000010

◆ GPIO_MODER_MODE2_1

#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos)

0x00000020

◆ GPIO_MODER_MODE2_Msk

#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos)

0x00000030

◆ GPIO_MODER_MODE2_Pos

#define GPIO_MODER_MODE2_Pos (4U)

◆ GPIO_MODER_MODE3

#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk

◆ GPIO_MODER_MODE3_0

#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos)

0x00000040

◆ GPIO_MODER_MODE3_1

#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos)

0x00000080

◆ GPIO_MODER_MODE3_Msk

#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos)

0x000000C0

◆ GPIO_MODER_MODE3_Pos

#define GPIO_MODER_MODE3_Pos (6U)

◆ GPIO_MODER_MODE4

#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk

◆ GPIO_MODER_MODE4_0

#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos)

0x00000100

◆ GPIO_MODER_MODE4_1

#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos)

0x00000200

◆ GPIO_MODER_MODE4_Msk

#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos)

0x00000300

◆ GPIO_MODER_MODE4_Pos

#define GPIO_MODER_MODE4_Pos (8U)

◆ GPIO_MODER_MODE5

#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk

◆ GPIO_MODER_MODE5_0

#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos)

0x00000400

◆ GPIO_MODER_MODE5_1

#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos)

0x00000800

◆ GPIO_MODER_MODE5_Msk

#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos)

0x00000C00

◆ GPIO_MODER_MODE5_Pos

#define GPIO_MODER_MODE5_Pos (10U)

◆ GPIO_MODER_MODE6

#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk

◆ GPIO_MODER_MODE6_0

#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos)

0x00001000

◆ GPIO_MODER_MODE6_1

#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos)

0x00002000

◆ GPIO_MODER_MODE6_Msk

#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos)

0x00003000

◆ GPIO_MODER_MODE6_Pos

#define GPIO_MODER_MODE6_Pos (12U)

◆ GPIO_MODER_MODE7

#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk

◆ GPIO_MODER_MODE7_0

#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos)

0x00004000

◆ GPIO_MODER_MODE7_1

#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos)

0x00008000

◆ GPIO_MODER_MODE7_Msk

#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos)

0x0000C000

◆ GPIO_MODER_MODE7_Pos

#define GPIO_MODER_MODE7_Pos (14U)

◆ GPIO_MODER_MODE8

#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk

◆ GPIO_MODER_MODE8_0

#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos)

0x00010000

◆ GPIO_MODER_MODE8_1

#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos)

0x00020000

◆ GPIO_MODER_MODE8_Msk

#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos)

0x00030000

◆ GPIO_MODER_MODE8_Pos

#define GPIO_MODER_MODE8_Pos (16U)

◆ GPIO_MODER_MODE9

#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk

◆ GPIO_MODER_MODE9_0

#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos)

0x00040000

◆ GPIO_MODER_MODE9_1

#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos)

0x00080000

◆ GPIO_MODER_MODE9_Msk

#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos)

0x000C0000

◆ GPIO_MODER_MODE9_Pos

#define GPIO_MODER_MODE9_Pos (18U)

◆ GPIO_ODR_OD0

#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk

◆ GPIO_ODR_OD0_Msk

#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos)

0x00000001

◆ GPIO_ODR_OD0_Pos

#define GPIO_ODR_OD0_Pos (0U)

◆ GPIO_ODR_OD1

#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk

◆ GPIO_ODR_OD10

#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk

◆ GPIO_ODR_OD10_Msk

#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos)

0x00000400

◆ GPIO_ODR_OD10_Pos

#define GPIO_ODR_OD10_Pos (10U)

◆ GPIO_ODR_OD11

#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk

◆ GPIO_ODR_OD11_Msk

#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos)

0x00000800

◆ GPIO_ODR_OD11_Pos

#define GPIO_ODR_OD11_Pos (11U)

◆ GPIO_ODR_OD12

#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk

◆ GPIO_ODR_OD12_Msk

#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos)

0x00001000

◆ GPIO_ODR_OD12_Pos

#define GPIO_ODR_OD12_Pos (12U)

◆ GPIO_ODR_OD13

#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk

◆ GPIO_ODR_OD13_Msk

#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos)

0x00002000

◆ GPIO_ODR_OD13_Pos

#define GPIO_ODR_OD13_Pos (13U)

◆ GPIO_ODR_OD14

#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk

◆ GPIO_ODR_OD14_Msk

#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos)

0x00004000

◆ GPIO_ODR_OD14_Pos

#define GPIO_ODR_OD14_Pos (14U)

◆ GPIO_ODR_OD15

#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk

◆ GPIO_ODR_OD15_Msk

#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos)

0x00008000

◆ GPIO_ODR_OD15_Pos

#define GPIO_ODR_OD15_Pos (15U)

◆ GPIO_ODR_OD1_Msk

#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos)

0x00000002

◆ GPIO_ODR_OD1_Pos

#define GPIO_ODR_OD1_Pos (1U)

◆ GPIO_ODR_OD2

#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk

◆ GPIO_ODR_OD2_Msk

#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos)

0x00000004

◆ GPIO_ODR_OD2_Pos

#define GPIO_ODR_OD2_Pos (2U)

◆ GPIO_ODR_OD3

#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk

◆ GPIO_ODR_OD3_Msk

#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos)

0x00000008

◆ GPIO_ODR_OD3_Pos

#define GPIO_ODR_OD3_Pos (3U)

◆ GPIO_ODR_OD4

#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk

◆ GPIO_ODR_OD4_Msk

#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos)

0x00000010

◆ GPIO_ODR_OD4_Pos

#define GPIO_ODR_OD4_Pos (4U)

◆ GPIO_ODR_OD5

#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk

◆ GPIO_ODR_OD5_Msk

#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos)

0x00000020

◆ GPIO_ODR_OD5_Pos

#define GPIO_ODR_OD5_Pos (5U)

◆ GPIO_ODR_OD6

#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk

◆ GPIO_ODR_OD6_Msk

#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos)

0x00000040

◆ GPIO_ODR_OD6_Pos

#define GPIO_ODR_OD6_Pos (6U)

◆ GPIO_ODR_OD7

#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk

◆ GPIO_ODR_OD7_Msk

#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos)

0x00000080

◆ GPIO_ODR_OD7_Pos

#define GPIO_ODR_OD7_Pos (7U)

◆ GPIO_ODR_OD8

#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk

◆ GPIO_ODR_OD8_Msk

#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos)

0x00000100

◆ GPIO_ODR_OD8_Pos

#define GPIO_ODR_OD8_Pos (8U)

◆ GPIO_ODR_OD9

#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk

◆ GPIO_ODR_OD9_Msk

#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos)

0x00000200

◆ GPIO_ODR_OD9_Pos

#define GPIO_ODR_OD9_Pos (9U)

◆ GPIO_OSPEEDR_OSPEED0

#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk

◆ GPIO_OSPEEDR_OSPEED0_0

#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)

0x00000001

◆ GPIO_OSPEEDR_OSPEED0_1

#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)

0x00000002

◆ GPIO_OSPEEDR_OSPEED0_Msk

#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)

0x00000003

◆ GPIO_OSPEEDR_OSPEED0_Pos

#define GPIO_OSPEEDR_OSPEED0_Pos (0U)

◆ GPIO_OSPEEDR_OSPEED1

#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk

◆ GPIO_OSPEEDR_OSPEED10

#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk

◆ GPIO_OSPEEDR_OSPEED10_0

#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)

0x00100000

◆ GPIO_OSPEEDR_OSPEED10_1

#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)

0x00200000

◆ GPIO_OSPEEDR_OSPEED10_Msk

#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)

0x00300000

◆ GPIO_OSPEEDR_OSPEED10_Pos

#define GPIO_OSPEEDR_OSPEED10_Pos (20U)

◆ GPIO_OSPEEDR_OSPEED11

#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk

◆ GPIO_OSPEEDR_OSPEED11_0

#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)

0x00400000

◆ GPIO_OSPEEDR_OSPEED11_1

#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)

0x00800000

◆ GPIO_OSPEEDR_OSPEED11_Msk

#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)

0x00C00000

◆ GPIO_OSPEEDR_OSPEED11_Pos

#define GPIO_OSPEEDR_OSPEED11_Pos (22U)

◆ GPIO_OSPEEDR_OSPEED12

#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk

◆ GPIO_OSPEEDR_OSPEED12_0

#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)

0x01000000

◆ GPIO_OSPEEDR_OSPEED12_1

#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)

0x02000000

◆ GPIO_OSPEEDR_OSPEED12_Msk

#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)

0x03000000

◆ GPIO_OSPEEDR_OSPEED12_Pos

#define GPIO_OSPEEDR_OSPEED12_Pos (24U)

◆ GPIO_OSPEEDR_OSPEED13

#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk

◆ GPIO_OSPEEDR_OSPEED13_0

#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)

0x04000000

◆ GPIO_OSPEEDR_OSPEED13_1

#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)

0x08000000

◆ GPIO_OSPEEDR_OSPEED13_Msk

#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)

0x0C000000

◆ GPIO_OSPEEDR_OSPEED13_Pos

#define GPIO_OSPEEDR_OSPEED13_Pos (26U)

◆ GPIO_OSPEEDR_OSPEED14

#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk

◆ GPIO_OSPEEDR_OSPEED14_0

#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)

0x10000000

◆ GPIO_OSPEEDR_OSPEED14_1

#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)

0x20000000

◆ GPIO_OSPEEDR_OSPEED14_Msk

#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)

0x30000000

◆ GPIO_OSPEEDR_OSPEED14_Pos

#define GPIO_OSPEEDR_OSPEED14_Pos (28U)

◆ GPIO_OSPEEDR_OSPEED15

#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk

◆ GPIO_OSPEEDR_OSPEED15_0

#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)

0x40000000

◆ GPIO_OSPEEDR_OSPEED15_1

#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)

0x80000000

◆ GPIO_OSPEEDR_OSPEED15_Msk

#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)

0xC0000000

◆ GPIO_OSPEEDR_OSPEED15_Pos

#define GPIO_OSPEEDR_OSPEED15_Pos (30U)

◆ GPIO_OSPEEDR_OSPEED1_0

#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)

0x00000004

◆ GPIO_OSPEEDR_OSPEED1_1

#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)

0x00000008

◆ GPIO_OSPEEDR_OSPEED1_Msk

#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)

0x0000000C

◆ GPIO_OSPEEDR_OSPEED1_Pos

#define GPIO_OSPEEDR_OSPEED1_Pos (2U)

◆ GPIO_OSPEEDR_OSPEED2

#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk

◆ GPIO_OSPEEDR_OSPEED2_0

#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)

0x00000010

◆ GPIO_OSPEEDR_OSPEED2_1

#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)

0x00000020

◆ GPIO_OSPEEDR_OSPEED2_Msk

#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)

0x00000030

◆ GPIO_OSPEEDR_OSPEED2_Pos

#define GPIO_OSPEEDR_OSPEED2_Pos (4U)

◆ GPIO_OSPEEDR_OSPEED3

#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk

◆ GPIO_OSPEEDR_OSPEED3_0

#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)

0x00000040

◆ GPIO_OSPEEDR_OSPEED3_1

#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)

0x00000080

◆ GPIO_OSPEEDR_OSPEED3_Msk

#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)

0x000000C0

◆ GPIO_OSPEEDR_OSPEED3_Pos

#define GPIO_OSPEEDR_OSPEED3_Pos (6U)

◆ GPIO_OSPEEDR_OSPEED4

#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk

◆ GPIO_OSPEEDR_OSPEED4_0

#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)

0x00000100

◆ GPIO_OSPEEDR_OSPEED4_1

#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)

0x00000200

◆ GPIO_OSPEEDR_OSPEED4_Msk

#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)

0x00000300

◆ GPIO_OSPEEDR_OSPEED4_Pos

#define GPIO_OSPEEDR_OSPEED4_Pos (8U)

◆ GPIO_OSPEEDR_OSPEED5

#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk

◆ GPIO_OSPEEDR_OSPEED5_0

#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)

0x00000400

◆ GPIO_OSPEEDR_OSPEED5_1

#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)

0x00000800

◆ GPIO_OSPEEDR_OSPEED5_Msk

#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)

0x00000C00

◆ GPIO_OSPEEDR_OSPEED5_Pos

#define GPIO_OSPEEDR_OSPEED5_Pos (10U)

◆ GPIO_OSPEEDR_OSPEED6

#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk

◆ GPIO_OSPEEDR_OSPEED6_0

#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)

0x00001000

◆ GPIO_OSPEEDR_OSPEED6_1

#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)

0x00002000

◆ GPIO_OSPEEDR_OSPEED6_Msk

#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)

0x00003000

◆ GPIO_OSPEEDR_OSPEED6_Pos

#define GPIO_OSPEEDR_OSPEED6_Pos (12U)

◆ GPIO_OSPEEDR_OSPEED7

#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk

◆ GPIO_OSPEEDR_OSPEED7_0

#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)

0x00004000

◆ GPIO_OSPEEDR_OSPEED7_1

#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)

0x00008000

◆ GPIO_OSPEEDR_OSPEED7_Msk

#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)

0x0000C000

◆ GPIO_OSPEEDR_OSPEED7_Pos

#define GPIO_OSPEEDR_OSPEED7_Pos (14U)

◆ GPIO_OSPEEDR_OSPEED8

#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk

◆ GPIO_OSPEEDR_OSPEED8_0

#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)

0x00010000

◆ GPIO_OSPEEDR_OSPEED8_1

#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)

0x00020000

◆ GPIO_OSPEEDR_OSPEED8_Msk

#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)

0x00030000

◆ GPIO_OSPEEDR_OSPEED8_Pos

#define GPIO_OSPEEDR_OSPEED8_Pos (16U)

◆ GPIO_OSPEEDR_OSPEED9

#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk

◆ GPIO_OSPEEDR_OSPEED9_0

#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)

0x00040000

◆ GPIO_OSPEEDR_OSPEED9_1

#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)

0x00080000

◆ GPIO_OSPEEDR_OSPEED9_Msk

#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)

0x000C0000

◆ GPIO_OSPEEDR_OSPEED9_Pos

#define GPIO_OSPEEDR_OSPEED9_Pos (18U)

◆ GPIO_OTYPER_OT0

#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk

◆ GPIO_OTYPER_OT0_Msk

#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos)

0x00000001

◆ GPIO_OTYPER_OT0_Pos

#define GPIO_OTYPER_OT0_Pos (0U)

◆ GPIO_OTYPER_OT1

#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk

◆ GPIO_OTYPER_OT10

#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk

◆ GPIO_OTYPER_OT10_Msk

#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos)

0x00000400

◆ GPIO_OTYPER_OT10_Pos

#define GPIO_OTYPER_OT10_Pos (10U)

◆ GPIO_OTYPER_OT11

#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk

◆ GPIO_OTYPER_OT11_Msk

#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos)

0x00000800

◆ GPIO_OTYPER_OT11_Pos

#define GPIO_OTYPER_OT11_Pos (11U)

◆ GPIO_OTYPER_OT12

#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk

◆ GPIO_OTYPER_OT12_Msk

#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos)

0x00001000

◆ GPIO_OTYPER_OT12_Pos

#define GPIO_OTYPER_OT12_Pos (12U)

◆ GPIO_OTYPER_OT13

#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk

◆ GPIO_OTYPER_OT13_Msk

#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos)

0x00002000

◆ GPIO_OTYPER_OT13_Pos

#define GPIO_OTYPER_OT13_Pos (13U)

◆ GPIO_OTYPER_OT14

#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk

◆ GPIO_OTYPER_OT14_Msk

#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos)

0x00004000

◆ GPIO_OTYPER_OT14_Pos

#define GPIO_OTYPER_OT14_Pos (14U)

◆ GPIO_OTYPER_OT15

#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk

◆ GPIO_OTYPER_OT15_Msk

#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos)

0x00008000

◆ GPIO_OTYPER_OT15_Pos

#define GPIO_OTYPER_OT15_Pos (15U)

◆ GPIO_OTYPER_OT1_Msk

#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos)

0x00000002

◆ GPIO_OTYPER_OT1_Pos

#define GPIO_OTYPER_OT1_Pos (1U)

◆ GPIO_OTYPER_OT2

#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk

◆ GPIO_OTYPER_OT2_Msk

#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos)

0x00000004

◆ GPIO_OTYPER_OT2_Pos

#define GPIO_OTYPER_OT2_Pos (2U)

◆ GPIO_OTYPER_OT3

#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk

◆ GPIO_OTYPER_OT3_Msk

#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos)

0x00000008

◆ GPIO_OTYPER_OT3_Pos

#define GPIO_OTYPER_OT3_Pos (3U)

◆ GPIO_OTYPER_OT4

#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk

◆ GPIO_OTYPER_OT4_Msk

#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos)

0x00000010

◆ GPIO_OTYPER_OT4_Pos

#define GPIO_OTYPER_OT4_Pos (4U)

◆ GPIO_OTYPER_OT5

#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk

◆ GPIO_OTYPER_OT5_Msk

#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos)

0x00000020

◆ GPIO_OTYPER_OT5_Pos

#define GPIO_OTYPER_OT5_Pos (5U)

◆ GPIO_OTYPER_OT6

#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk

◆ GPIO_OTYPER_OT6_Msk

#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos)

0x00000040

◆ GPIO_OTYPER_OT6_Pos

#define GPIO_OTYPER_OT6_Pos (6U)

◆ GPIO_OTYPER_OT7

#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk

◆ GPIO_OTYPER_OT7_Msk

#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos)

0x00000080

◆ GPIO_OTYPER_OT7_Pos

#define GPIO_OTYPER_OT7_Pos (7U)

◆ GPIO_OTYPER_OT8

#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk

◆ GPIO_OTYPER_OT8_Msk

#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos)

0x00000100

◆ GPIO_OTYPER_OT8_Pos

#define GPIO_OTYPER_OT8_Pos (8U)

◆ GPIO_OTYPER_OT9

#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk

◆ GPIO_OTYPER_OT9_Msk

#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos)

0x00000200

◆ GPIO_OTYPER_OT9_Pos

#define GPIO_OTYPER_OT9_Pos (9U)

◆ GPIO_PUPDR_PUPD0

#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk

◆ GPIO_PUPDR_PUPD0_0

#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos)

0x00000001

◆ GPIO_PUPDR_PUPD0_1

#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos)

0x00000002

◆ GPIO_PUPDR_PUPD0_Msk

#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos)

0x00000003

◆ GPIO_PUPDR_PUPD0_Pos

#define GPIO_PUPDR_PUPD0_Pos (0U)

◆ GPIO_PUPDR_PUPD1

#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk

◆ GPIO_PUPDR_PUPD10

#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk

◆ GPIO_PUPDR_PUPD10_0

#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos)

0x00100000

◆ GPIO_PUPDR_PUPD10_1

#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos)

0x00200000

◆ GPIO_PUPDR_PUPD10_Msk

#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos)

0x00300000

◆ GPIO_PUPDR_PUPD10_Pos

#define GPIO_PUPDR_PUPD10_Pos (20U)

◆ GPIO_PUPDR_PUPD11

#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk

◆ GPIO_PUPDR_PUPD11_0

#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos)

0x00400000

◆ GPIO_PUPDR_PUPD11_1

#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos)

0x00800000

◆ GPIO_PUPDR_PUPD11_Msk

#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos)

0x00C00000

◆ GPIO_PUPDR_PUPD11_Pos

#define GPIO_PUPDR_PUPD11_Pos (22U)

◆ GPIO_PUPDR_PUPD12

#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk

◆ GPIO_PUPDR_PUPD12_0

#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos)

0x01000000

◆ GPIO_PUPDR_PUPD12_1

#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos)

0x02000000

◆ GPIO_PUPDR_PUPD12_Msk

#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos)

0x03000000

◆ GPIO_PUPDR_PUPD12_Pos

#define GPIO_PUPDR_PUPD12_Pos (24U)

◆ GPIO_PUPDR_PUPD13

#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk

◆ GPIO_PUPDR_PUPD13_0

#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos)

0x04000000

◆ GPIO_PUPDR_PUPD13_1

#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos)

0x08000000

◆ GPIO_PUPDR_PUPD13_Msk

#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos)

0x0C000000

◆ GPIO_PUPDR_PUPD13_Pos

#define GPIO_PUPDR_PUPD13_Pos (26U)

◆ GPIO_PUPDR_PUPD14

#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk

◆ GPIO_PUPDR_PUPD14_0

#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos)

0x10000000

◆ GPIO_PUPDR_PUPD14_1

#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos)

0x20000000

◆ GPIO_PUPDR_PUPD14_Msk

#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos)

0x30000000

◆ GPIO_PUPDR_PUPD14_Pos

#define GPIO_PUPDR_PUPD14_Pos (28U)

◆ GPIO_PUPDR_PUPD15

#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk

◆ GPIO_PUPDR_PUPD15_0

#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos)

0x40000000

◆ GPIO_PUPDR_PUPD15_1

#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos)

0x80000000

◆ GPIO_PUPDR_PUPD15_Msk

#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos)

0xC0000000

◆ GPIO_PUPDR_PUPD15_Pos

#define GPIO_PUPDR_PUPD15_Pos (30U)

◆ GPIO_PUPDR_PUPD1_0

#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos)

0x00000004

◆ GPIO_PUPDR_PUPD1_1

#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos)

0x00000008

◆ GPIO_PUPDR_PUPD1_Msk

#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos)

0x0000000C

◆ GPIO_PUPDR_PUPD1_Pos

#define GPIO_PUPDR_PUPD1_Pos (2U)

◆ GPIO_PUPDR_PUPD2

#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk

◆ GPIO_PUPDR_PUPD2_0

#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos)

0x00000010

◆ GPIO_PUPDR_PUPD2_1

#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos)

0x00000020

◆ GPIO_PUPDR_PUPD2_Msk

#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos)

0x00000030

◆ GPIO_PUPDR_PUPD2_Pos

#define GPIO_PUPDR_PUPD2_Pos (4U)

◆ GPIO_PUPDR_PUPD3

#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk

◆ GPIO_PUPDR_PUPD3_0

#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos)

0x00000040

◆ GPIO_PUPDR_PUPD3_1

#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos)

0x00000080

◆ GPIO_PUPDR_PUPD3_Msk

#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos)

0x000000C0

◆ GPIO_PUPDR_PUPD3_Pos

#define GPIO_PUPDR_PUPD3_Pos (6U)

◆ GPIO_PUPDR_PUPD4

#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk

◆ GPIO_PUPDR_PUPD4_0

#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos)

0x00000100

◆ GPIO_PUPDR_PUPD4_1

#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos)

0x00000200

◆ GPIO_PUPDR_PUPD4_Msk

#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos)

0x00000300

◆ GPIO_PUPDR_PUPD4_Pos

#define GPIO_PUPDR_PUPD4_Pos (8U)

◆ GPIO_PUPDR_PUPD5

#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk

◆ GPIO_PUPDR_PUPD5_0

#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos)

0x00000400

◆ GPIO_PUPDR_PUPD5_1

#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos)

0x00000800

◆ GPIO_PUPDR_PUPD5_Msk

#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos)

0x00000C00

◆ GPIO_PUPDR_PUPD5_Pos

#define GPIO_PUPDR_PUPD5_Pos (10U)

◆ GPIO_PUPDR_PUPD6

#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk

◆ GPIO_PUPDR_PUPD6_0

#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos)

0x00001000

◆ GPIO_PUPDR_PUPD6_1

#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos)

0x00002000

◆ GPIO_PUPDR_PUPD6_Msk

#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos)

0x00003000

◆ GPIO_PUPDR_PUPD6_Pos

#define GPIO_PUPDR_PUPD6_Pos (12U)

◆ GPIO_PUPDR_PUPD7

#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk

◆ GPIO_PUPDR_PUPD7_0

#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos)

0x00004000

◆ GPIO_PUPDR_PUPD7_1

#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos)

0x00008000

◆ GPIO_PUPDR_PUPD7_Msk

#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos)

0x0000C000

◆ GPIO_PUPDR_PUPD7_Pos

#define GPIO_PUPDR_PUPD7_Pos (14U)

◆ GPIO_PUPDR_PUPD8

#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk

◆ GPIO_PUPDR_PUPD8_0

#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos)

0x00010000

◆ GPIO_PUPDR_PUPD8_1

#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos)

0x00020000

◆ GPIO_PUPDR_PUPD8_Msk

#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos)

0x00030000

◆ GPIO_PUPDR_PUPD8_Pos

#define GPIO_PUPDR_PUPD8_Pos (16U)

◆ GPIO_PUPDR_PUPD9

#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk

◆ GPIO_PUPDR_PUPD9_0

#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos)

0x00040000

◆ GPIO_PUPDR_PUPD9_1

#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos)

0x00080000

◆ GPIO_PUPDR_PUPD9_Msk

#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos)

0x000C0000

◆ GPIO_PUPDR_PUPD9_Pos

#define GPIO_PUPDR_PUPD9_Pos (18U)

◆ I2C_CR1_ADDRIE

#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk

Address match interrupt enable

◆ I2C_CR1_ADDRIE_Msk

#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos)

0x00000008

◆ I2C_CR1_ADDRIE_Pos

#define I2C_CR1_ADDRIE_Pos (3U)

◆ I2C_CR1_ALERTEN

#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk

SMBus alert enable

◆ I2C_CR1_ALERTEN_Msk

#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos)

0x00400000

◆ I2C_CR1_ALERTEN_Pos

#define I2C_CR1_ALERTEN_Pos (22U)

◆ I2C_CR1_ANFOFF

#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk

Analog noise filter OFF

◆ I2C_CR1_ANFOFF_Msk

#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos)

0x00001000

◆ I2C_CR1_ANFOFF_Pos

#define I2C_CR1_ANFOFF_Pos (12U)

◆ I2C_CR1_DNF

#define I2C_CR1_DNF I2C_CR1_DNF_Msk

Digital noise filter

◆ I2C_CR1_DNF_Msk

#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos)

0x00000F00

◆ I2C_CR1_DNF_Pos

#define I2C_CR1_DNF_Pos (8U)

◆ I2C_CR1_ERRIE

#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk

Errors interrupt enable

◆ I2C_CR1_ERRIE_Msk

#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos)

0x00000080

◆ I2C_CR1_ERRIE_Pos

#define I2C_CR1_ERRIE_Pos (7U)

◆ I2C_CR1_GCEN

#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk

General call enable

◆ I2C_CR1_GCEN_Msk

#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos)

0x00080000

◆ I2C_CR1_GCEN_Pos

#define I2C_CR1_GCEN_Pos (19U)

◆ I2C_CR1_NACKIE

#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk

NACK received interrupt enable

◆ I2C_CR1_NACKIE_Msk

#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos)

0x00000010

◆ I2C_CR1_NACKIE_Pos

#define I2C_CR1_NACKIE_Pos (4U)

◆ I2C_CR1_NOSTRETCH

#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk

Clock stretching disable

◆ I2C_CR1_NOSTRETCH_Msk

#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos)

0x00020000

◆ I2C_CR1_NOSTRETCH_Pos

#define I2C_CR1_NOSTRETCH_Pos (17U)

◆ I2C_CR1_PE

#define I2C_CR1_PE I2C_CR1_PE_Msk

Peripheral enable

◆ I2C_CR1_PE_Msk

#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos)

0x00000001

◆ I2C_CR1_PE_Pos

#define I2C_CR1_PE_Pos (0U)

◆ I2C_CR1_PECEN

#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk

PEC enable

◆ I2C_CR1_PECEN_Msk

#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos)

0x00800000

◆ I2C_CR1_PECEN_Pos

#define I2C_CR1_PECEN_Pos (23U)

◆ I2C_CR1_RXDMAEN

#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk

DMA reception requests enable

◆ I2C_CR1_RXDMAEN_Msk

#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos)

0x00008000

◆ I2C_CR1_RXDMAEN_Pos

#define I2C_CR1_RXDMAEN_Pos (15U)

◆ I2C_CR1_RXIE

#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk

RX interrupt enable

◆ I2C_CR1_RXIE_Msk

#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos)

0x00000004

◆ I2C_CR1_RXIE_Pos

#define I2C_CR1_RXIE_Pos (2U)

◆ I2C_CR1_SBC

#define I2C_CR1_SBC I2C_CR1_SBC_Msk

Slave byte control

◆ I2C_CR1_SBC_Msk

#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos)

0x00010000

◆ I2C_CR1_SBC_Pos

#define I2C_CR1_SBC_Pos (16U)

◆ I2C_CR1_SMBDEN

#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk

SMBus device default address enable

◆ I2C_CR1_SMBDEN_Msk

#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos)

0x00200000

◆ I2C_CR1_SMBDEN_Pos

#define I2C_CR1_SMBDEN_Pos (21U)

◆ I2C_CR1_SMBHEN

#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk

SMBus host address enable

◆ I2C_CR1_SMBHEN_Msk

#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos)

0x00100000

◆ I2C_CR1_SMBHEN_Pos

#define I2C_CR1_SMBHEN_Pos (20U)

◆ I2C_CR1_STOPIE

#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk

STOP detection interrupt enable

◆ I2C_CR1_STOPIE_Msk

#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos)

0x00000020

◆ I2C_CR1_STOPIE_Pos

#define I2C_CR1_STOPIE_Pos (5U)

◆ I2C_CR1_SWRST

#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk

Software reset

◆ I2C_CR1_SWRST_Msk

#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos)

0x00002000

◆ I2C_CR1_SWRST_Pos

#define I2C_CR1_SWRST_Pos (13U)

◆ I2C_CR1_TCIE

#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk

Transfer complete interrupt enable

◆ I2C_CR1_TCIE_Msk

#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos)

0x00000040

◆ I2C_CR1_TCIE_Pos

#define I2C_CR1_TCIE_Pos (6U)

◆ I2C_CR1_TXDMAEN

#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk

DMA transmission requests enable

◆ I2C_CR1_TXDMAEN_Msk

#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos)

0x00004000

◆ I2C_CR1_TXDMAEN_Pos

#define I2C_CR1_TXDMAEN_Pos (14U)

◆ I2C_CR1_TXIE

#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk

TX interrupt enable

◆ I2C_CR1_TXIE_Msk

#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos)

0x00000002

◆ I2C_CR1_TXIE_Pos

#define I2C_CR1_TXIE_Pos (1U)

◆ I2C_CR1_WUPEN

#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk

Wakeup from STOP enable

◆ I2C_CR1_WUPEN_Msk

#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos)

0x00040000

◆ I2C_CR1_WUPEN_Pos

#define I2C_CR1_WUPEN_Pos (18U)

◆ I2C_CR2_ADD10

#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk

10-bit addressing mode (master mode)

◆ I2C_CR2_ADD10_Msk

#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos)

0x00000800

◆ I2C_CR2_ADD10_Pos

#define I2C_CR2_ADD10_Pos (11U)

◆ I2C_CR2_AUTOEND

#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk

Automatic end mode (master mode)

◆ I2C_CR2_AUTOEND_Msk

#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos)

0x02000000

◆ I2C_CR2_AUTOEND_Pos

#define I2C_CR2_AUTOEND_Pos (25U)

◆ I2C_CR2_HEAD10R

#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk

10-bit address header only read direction (master mode)

◆ I2C_CR2_HEAD10R_Msk

#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos)

0x00001000

◆ I2C_CR2_HEAD10R_Pos

#define I2C_CR2_HEAD10R_Pos (12U)

◆ I2C_CR2_NACK

#define I2C_CR2_NACK I2C_CR2_NACK_Msk

NACK generation (slave mode)

◆ I2C_CR2_NACK_Msk

#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos)

0x00008000

◆ I2C_CR2_NACK_Pos

#define I2C_CR2_NACK_Pos (15U)

◆ I2C_CR2_NBYTES

#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk

Number of bytes

◆ I2C_CR2_NBYTES_Msk

#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos)

0x00FF0000

◆ I2C_CR2_NBYTES_Pos

#define I2C_CR2_NBYTES_Pos (16U)

◆ I2C_CR2_PECBYTE

#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk

Packet error checking byte

◆ I2C_CR2_PECBYTE_Msk

#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos)

0x04000000

◆ I2C_CR2_PECBYTE_Pos

#define I2C_CR2_PECBYTE_Pos (26U)

◆ I2C_CR2_RD_WRN

#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk

Transfer direction (master mode)

◆ I2C_CR2_RD_WRN_Msk

#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos)

0x00000400

◆ I2C_CR2_RD_WRN_Pos

#define I2C_CR2_RD_WRN_Pos (10U)

◆ I2C_CR2_RELOAD

#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk

NBYTES reload mode

◆ I2C_CR2_RELOAD_Msk

#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos)

0x01000000

◆ I2C_CR2_RELOAD_Pos

#define I2C_CR2_RELOAD_Pos (24U)

◆ I2C_CR2_SADD

#define I2C_CR2_SADD I2C_CR2_SADD_Msk

Slave address (master mode)

◆ I2C_CR2_SADD_Msk

#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos)

0x000003FF

◆ I2C_CR2_SADD_Pos

#define I2C_CR2_SADD_Pos (0U)

◆ I2C_CR2_START

#define I2C_CR2_START I2C_CR2_START_Msk

START generation

◆ I2C_CR2_START_Msk

#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos)

0x00002000

◆ I2C_CR2_START_Pos

#define I2C_CR2_START_Pos (13U)

◆ I2C_CR2_STOP

#define I2C_CR2_STOP I2C_CR2_STOP_Msk

STOP generation (master mode)

◆ I2C_CR2_STOP_Msk

#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos)

0x00004000

◆ I2C_CR2_STOP_Pos

#define I2C_CR2_STOP_Pos (14U)

◆ I2C_ICR_ADDRCF

#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk

Address matched clear flag

◆ I2C_ICR_ADDRCF_Msk

#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos)

0x00000008

◆ I2C_ICR_ADDRCF_Pos

#define I2C_ICR_ADDRCF_Pos (3U)

◆ I2C_ICR_ALERTCF

#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk

Alert clear flag

◆ I2C_ICR_ALERTCF_Msk

#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos)

0x00002000

◆ I2C_ICR_ALERTCF_Pos

#define I2C_ICR_ALERTCF_Pos (13U)

◆ I2C_ICR_ARLOCF

#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk

Arbitration lost clear flag

◆ I2C_ICR_ARLOCF_Msk

#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos)

0x00000200

◆ I2C_ICR_ARLOCF_Pos

#define I2C_ICR_ARLOCF_Pos (9U)

◆ I2C_ICR_BERRCF

#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk

Bus error clear flag

◆ I2C_ICR_BERRCF_Msk

#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos)

0x00000100

◆ I2C_ICR_BERRCF_Pos

#define I2C_ICR_BERRCF_Pos (8U)

◆ I2C_ICR_NACKCF

#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk

NACK clear flag

◆ I2C_ICR_NACKCF_Msk

#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos)

0x00000010

◆ I2C_ICR_NACKCF_Pos

#define I2C_ICR_NACKCF_Pos (4U)

◆ I2C_ICR_OVRCF

#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk

Overrun/Underrun clear flag

◆ I2C_ICR_OVRCF_Msk

#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos)

0x00000400

◆ I2C_ICR_OVRCF_Pos

#define I2C_ICR_OVRCF_Pos (10U)

◆ I2C_ICR_PECCF

#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk

PAC error clear flag

◆ I2C_ICR_PECCF_Msk

#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos)

0x00000800

◆ I2C_ICR_PECCF_Pos

#define I2C_ICR_PECCF_Pos (11U)

◆ I2C_ICR_STOPCF

#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk

STOP detection clear flag

◆ I2C_ICR_STOPCF_Msk

#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos)

0x00000020

◆ I2C_ICR_STOPCF_Pos

#define I2C_ICR_STOPCF_Pos (5U)

◆ I2C_ICR_TIMOUTCF

#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk

Timeout clear flag

◆ I2C_ICR_TIMOUTCF_Msk

#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos)

0x00001000

◆ I2C_ICR_TIMOUTCF_Pos

#define I2C_ICR_TIMOUTCF_Pos (12U)

◆ I2C_ISR_ADDCODE

#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk

Address match code (slave mode)

◆ I2C_ISR_ADDCODE_Msk

#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos)

0x00FE0000

◆ I2C_ISR_ADDCODE_Pos

#define I2C_ISR_ADDCODE_Pos (17U)

◆ I2C_ISR_ADDR

#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk

Address matched (slave mode)

◆ I2C_ISR_ADDR_Msk

#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos)

0x00000008

◆ I2C_ISR_ADDR_Pos

#define I2C_ISR_ADDR_Pos (3U)

◆ I2C_ISR_ALERT

#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk

SMBus alert

◆ I2C_ISR_ALERT_Msk

#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos)

0x00002000

◆ I2C_ISR_ALERT_Pos

#define I2C_ISR_ALERT_Pos (13U)

◆ I2C_ISR_ARLO

#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk

Arbitration lost

◆ I2C_ISR_ARLO_Msk

#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos)

0x00000200

◆ I2C_ISR_ARLO_Pos

#define I2C_ISR_ARLO_Pos (9U)

◆ I2C_ISR_BERR

#define I2C_ISR_BERR I2C_ISR_BERR_Msk

Bus error

◆ I2C_ISR_BERR_Msk

#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos)

0x00000100

◆ I2C_ISR_BERR_Pos

#define I2C_ISR_BERR_Pos (8U)

◆ I2C_ISR_BUSY

#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk

Bus busy

◆ I2C_ISR_BUSY_Msk

#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos)

0x00008000

◆ I2C_ISR_BUSY_Pos

#define I2C_ISR_BUSY_Pos (15U)

◆ I2C_ISR_DIR

#define I2C_ISR_DIR I2C_ISR_DIR_Msk

Transfer direction (slave mode)

◆ I2C_ISR_DIR_Msk

#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos)

0x00010000

◆ I2C_ISR_DIR_Pos

#define I2C_ISR_DIR_Pos (16U)

◆ I2C_ISR_NACKF

#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk

NACK received flag

◆ I2C_ISR_NACKF_Msk

#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos)

0x00000010

◆ I2C_ISR_NACKF_Pos

#define I2C_ISR_NACKF_Pos (4U)

◆ I2C_ISR_OVR

#define I2C_ISR_OVR I2C_ISR_OVR_Msk

Overrun/Underrun

◆ I2C_ISR_OVR_Msk

#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos)

0x00000400

◆ I2C_ISR_OVR_Pos

#define I2C_ISR_OVR_Pos (10U)

◆ I2C_ISR_PECERR

#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk

PEC error in reception

◆ I2C_ISR_PECERR_Msk

#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos)

0x00000800

◆ I2C_ISR_PECERR_Pos

#define I2C_ISR_PECERR_Pos (11U)

◆ I2C_ISR_RXNE

#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk

Receive data register not empty

◆ I2C_ISR_RXNE_Msk

#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos)

0x00000004

◆ I2C_ISR_RXNE_Pos

#define I2C_ISR_RXNE_Pos (2U)

◆ I2C_ISR_STOPF

#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk

STOP detection flag

◆ I2C_ISR_STOPF_Msk

#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos)

0x00000020

◆ I2C_ISR_STOPF_Pos

#define I2C_ISR_STOPF_Pos (5U)

◆ I2C_ISR_TC

#define I2C_ISR_TC I2C_ISR_TC_Msk

Transfer complete (master mode)

◆ I2C_ISR_TC_Msk

#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos)

0x00000040

◆ I2C_ISR_TC_Pos

#define I2C_ISR_TC_Pos (6U)

◆ I2C_ISR_TCR

#define I2C_ISR_TCR I2C_ISR_TCR_Msk

Transfer complete reload

◆ I2C_ISR_TCR_Msk

#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos)

0x00000080

◆ I2C_ISR_TCR_Pos

#define I2C_ISR_TCR_Pos (7U)

◆ I2C_ISR_TIMEOUT

#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk

Timeout or Tlow detection flag

◆ I2C_ISR_TIMEOUT_Msk

#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos)

0x00001000

◆ I2C_ISR_TIMEOUT_Pos

#define I2C_ISR_TIMEOUT_Pos (12U)

◆ I2C_ISR_TXE

#define I2C_ISR_TXE I2C_ISR_TXE_Msk

Transmit data register empty

◆ I2C_ISR_TXE_Msk

#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos)

0x00000001

◆ I2C_ISR_TXE_Pos

#define I2C_ISR_TXE_Pos (0U)

◆ I2C_ISR_TXIS

#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk

Transmit interrupt status

◆ I2C_ISR_TXIS_Msk

#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos)

0x00000002

◆ I2C_ISR_TXIS_Pos

#define I2C_ISR_TXIS_Pos (1U)

◆ I2C_OAR1_OA1

#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk

Interface own address 1

◆ I2C_OAR1_OA1_Msk

#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos)

0x000003FF

◆ I2C_OAR1_OA1_Pos

#define I2C_OAR1_OA1_Pos (0U)

◆ I2C_OAR1_OA1EN

#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk

Own address 1 enable

◆ I2C_OAR1_OA1EN_Msk

#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos)

0x00008000

◆ I2C_OAR1_OA1EN_Pos

#define I2C_OAR1_OA1EN_Pos (15U)

◆ I2C_OAR1_OA1MODE

#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk

Own address 1 10-bit mode

◆ I2C_OAR1_OA1MODE_Msk

#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos)

0x00000400

◆ I2C_OAR1_OA1MODE_Pos

#define I2C_OAR1_OA1MODE_Pos (10U)

◆ I2C_OAR2_OA2

#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk

Interface own address 2

◆ I2C_OAR2_OA2_Msk

#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos)

0x000000FE

◆ I2C_OAR2_OA2_Pos

#define I2C_OAR2_OA2_Pos (1U)

◆ I2C_OAR2_OA2EN

#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk

Own address 2 enable

◆ I2C_OAR2_OA2EN_Msk

#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos)

0x00008000

◆ I2C_OAR2_OA2EN_Pos

#define I2C_OAR2_OA2EN_Pos (15U)

◆ I2C_OAR2_OA2MASK01

#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk

OA2[1] is masked, Only OA2[7:2] are compared

◆ I2C_OAR2_OA2MASK01_Msk

#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos)

0x00000100

◆ I2C_OAR2_OA2MASK01_Pos

#define I2C_OAR2_OA2MASK01_Pos (8U)

◆ I2C_OAR2_OA2MASK02

#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk

OA2[2:1] is masked, Only OA2[7:3] are compared

◆ I2C_OAR2_OA2MASK02_Msk

#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos)

0x00000200

◆ I2C_OAR2_OA2MASK02_Pos

#define I2C_OAR2_OA2MASK02_Pos (9U)

◆ I2C_OAR2_OA2MASK03

#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk

OA2[3:1] is masked, Only OA2[7:4] are compared

◆ I2C_OAR2_OA2MASK03_Msk

#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos)

0x00000300

◆ I2C_OAR2_OA2MASK03_Pos

#define I2C_OAR2_OA2MASK03_Pos (8U)

◆ I2C_OAR2_OA2MASK04

#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk

OA2[4:1] is masked, Only OA2[7:5] are compared

◆ I2C_OAR2_OA2MASK04_Msk

#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos)

0x00000400

◆ I2C_OAR2_OA2MASK04_Pos

#define I2C_OAR2_OA2MASK04_Pos (10U)

◆ I2C_OAR2_OA2MASK05

#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk

OA2[5:1] is masked, Only OA2[7:6] are compared

◆ I2C_OAR2_OA2MASK05_Msk

#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos)

0x00000500

◆ I2C_OAR2_OA2MASK05_Pos

#define I2C_OAR2_OA2MASK05_Pos (8U)

◆ I2C_OAR2_OA2MASK06

#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk

OA2[6:1] is masked, Only OA2[7] are compared

◆ I2C_OAR2_OA2MASK06_Msk

#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos)

0x00000600

◆ I2C_OAR2_OA2MASK06_Pos

#define I2C_OAR2_OA2MASK06_Pos (9U)

◆ I2C_OAR2_OA2MASK07

#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk

OA2[7:1] is masked, No comparison is done

◆ I2C_OAR2_OA2MASK07_Msk

#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos)

0x00000700

◆ I2C_OAR2_OA2MASK07_Pos

#define I2C_OAR2_OA2MASK07_Pos (8U)

◆ I2C_OAR2_OA2MSK

#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk

Own address 2 masks

◆ I2C_OAR2_OA2MSK_Msk

#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos)

0x00000700

◆ I2C_OAR2_OA2MSK_Pos

#define I2C_OAR2_OA2MSK_Pos (8U)

◆ I2C_OAR2_OA2NOMASK

#define I2C_OAR2_OA2NOMASK (0U)

No mask

◆ I2C_PECR_PEC

#define I2C_PECR_PEC I2C_PECR_PEC_Msk

PEC register

◆ I2C_PECR_PEC_Msk

#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos)

0x000000FF

◆ I2C_PECR_PEC_Pos

#define I2C_PECR_PEC_Pos (0U)

◆ I2C_RXDR_RXDATA

#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk

8-bit receive data

◆ I2C_RXDR_RXDATA_Msk

#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos)

0x000000FF

◆ I2C_RXDR_RXDATA_Pos

#define I2C_RXDR_RXDATA_Pos (0U)

◆ I2C_TIMEOUTR_TEXTEN

#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk

Extended clock timeout enable

◆ I2C_TIMEOUTR_TEXTEN_Msk

#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)

0x80000000

◆ I2C_TIMEOUTR_TEXTEN_Pos

#define I2C_TIMEOUTR_TEXTEN_Pos (31U)

◆ I2C_TIMEOUTR_TIDLE

#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk

Idle clock timeout detection

◆ I2C_TIMEOUTR_TIDLE_Msk

#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)

0x00001000

◆ I2C_TIMEOUTR_TIDLE_Pos

#define I2C_TIMEOUTR_TIDLE_Pos (12U)

◆ I2C_TIMEOUTR_TIMEOUTA

#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk

Bus timeout A

◆ I2C_TIMEOUTR_TIMEOUTA_Msk

#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)

0x00000FFF

◆ I2C_TIMEOUTR_TIMEOUTA_Pos

#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)

◆ I2C_TIMEOUTR_TIMEOUTB

#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk

Bus timeout B

◆ I2C_TIMEOUTR_TIMEOUTB_Msk

#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)

0x0FFF0000

◆ I2C_TIMEOUTR_TIMEOUTB_Pos

#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)

◆ I2C_TIMEOUTR_TIMOUTEN

#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk

Clock timeout enable

◆ I2C_TIMEOUTR_TIMOUTEN_Msk

#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)

0x00008000

◆ I2C_TIMEOUTR_TIMOUTEN_Pos

#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)

◆ I2C_TIMINGR_PRESC

#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk

Timings prescaler

◆ I2C_TIMINGR_PRESC_Msk

#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos)

0xF0000000

◆ I2C_TIMINGR_PRESC_Pos

#define I2C_TIMINGR_PRESC_Pos (28U)

◆ I2C_TIMINGR_SCLDEL

#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk

Data setup time

◆ I2C_TIMINGR_SCLDEL_Msk

#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos)

0x00F00000

◆ I2C_TIMINGR_SCLDEL_Pos

#define I2C_TIMINGR_SCLDEL_Pos (20U)

◆ I2C_TIMINGR_SCLH

#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk

SCL high period (master mode)

◆ I2C_TIMINGR_SCLH_Msk

#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos)

0x0000FF00

◆ I2C_TIMINGR_SCLH_Pos

#define I2C_TIMINGR_SCLH_Pos (8U)

◆ I2C_TIMINGR_SCLL

#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk

SCL low period (master mode)

◆ I2C_TIMINGR_SCLL_Msk

#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos)

0x000000FF

◆ I2C_TIMINGR_SCLL_Pos

#define I2C_TIMINGR_SCLL_Pos (0U)

◆ I2C_TIMINGR_SDADEL

#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk

Data hold time

◆ I2C_TIMINGR_SDADEL_Msk

#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos)

0x000F0000

◆ I2C_TIMINGR_SDADEL_Pos

#define I2C_TIMINGR_SDADEL_Pos (16U)

◆ I2C_TXDR_TXDATA

#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk

8-bit transmit data

◆ I2C_TXDR_TXDATA_Msk

#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos)

0x000000FF

◆ I2C_TXDR_TXDATA_Pos

#define I2C_TXDR_TXDATA_Pos (0U)

◆ IWDG_KR_KEY

#define IWDG_KR_KEY IWDG_KR_KEY_Msk

Key value (write only, read 0000h)

◆ IWDG_KR_KEY_Msk

#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos)

0x0000FFFF

◆ IWDG_KR_KEY_Pos

#define IWDG_KR_KEY_Pos (0U)

◆ IWDG_PR_PR

#define IWDG_PR_PR IWDG_PR_PR_Msk

PR[2:0] (Prescaler divider)

◆ IWDG_PR_PR_0

#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos)

0x00000001

◆ IWDG_PR_PR_1

#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos)

0x00000002

◆ IWDG_PR_PR_2

#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos)

0x00000004

◆ IWDG_PR_PR_Msk

#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos)

0x00000007

◆ IWDG_PR_PR_Pos

#define IWDG_PR_PR_Pos (0U)

◆ IWDG_RLR_RL

#define IWDG_RLR_RL IWDG_RLR_RL_Msk

Watchdog counter reload value

◆ IWDG_RLR_RL_Msk

#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos)

0x00000FFF

◆ IWDG_RLR_RL_Pos

#define IWDG_RLR_RL_Pos (0U)

◆ IWDG_SR_PVU

#define IWDG_SR_PVU IWDG_SR_PVU_Msk

Watchdog prescaler value update

◆ IWDG_SR_PVU_Msk

#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos)

0x00000001

◆ IWDG_SR_PVU_Pos

#define IWDG_SR_PVU_Pos (0U)

◆ IWDG_SR_RVU

#define IWDG_SR_RVU IWDG_SR_RVU_Msk

Watchdog counter reload value update

◆ IWDG_SR_RVU_Msk

#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos)

0x00000002

◆ IWDG_SR_RVU_Pos

#define IWDG_SR_RVU_Pos (1U)

◆ IWDG_SR_WVU

#define IWDG_SR_WVU IWDG_SR_WVU_Msk

Watchdog counter window value update

◆ IWDG_SR_WVU_Msk

#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos)

0x00000004

◆ IWDG_SR_WVU_Pos

#define IWDG_SR_WVU_Pos (2U)

◆ IWDG_WINR_WIN

#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk

Watchdog counter window value

◆ IWDG_WINR_WIN_Msk

#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos)

0x00000FFF

◆ IWDG_WINR_WIN_Pos

#define IWDG_WINR_WIN_Pos (0U)

◆ PWR_CR1_DBP

#define PWR_CR1_DBP PWR_CR1_DBP_Msk

Disable Backup Domain write protection

◆ PWR_CR1_DBP_Msk

#define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos)

0x00000100

◆ PWR_CR1_DBP_Pos

#define PWR_CR1_DBP_Pos (8U)

◆ PWR_CR1_FPD_LPRUN

#define PWR_CR1_FPD_LPRUN PWR_CR1_FPD_LPRUN_Msk

Flash power down mode during run

◆ PWR_CR1_FPD_LPRUN_Msk

#define PWR_CR1_FPD_LPRUN_Msk (0x1UL << PWR_CR1_FPD_LPRUN_Pos)

0x00000010

◆ PWR_CR1_FPD_LPRUN_Pos

#define PWR_CR1_FPD_LPRUN_Pos (4U)

◆ PWR_CR1_FPD_LPSLP

#define PWR_CR1_FPD_LPSLP PWR_CR1_FPD_LPSLP_Msk

Flash power down mode during sleep

◆ PWR_CR1_FPD_LPSLP_Msk

#define PWR_CR1_FPD_LPSLP_Msk (0x1UL << PWR_CR1_FPD_LPSLP_Pos)

0x00000020

◆ PWR_CR1_FPD_LPSLP_Pos

#define PWR_CR1_FPD_LPSLP_Pos (5U)

◆ PWR_CR1_FPD_STOP

#define PWR_CR1_FPD_STOP PWR_CR1_FPD_STOP_Msk

Flash power down mode during stop

◆ PWR_CR1_FPD_STOP_Msk

#define PWR_CR1_FPD_STOP_Msk (0x1UL << PWR_CR1_FPD_STOP_Pos)

0x00000008

◆ PWR_CR1_FPD_STOP_Pos

#define PWR_CR1_FPD_STOP_Pos (3U)

◆ PWR_CR1_LPMS

#define PWR_CR1_LPMS PWR_CR1_LPMS_Msk

Low Power Mode Selection

◆ PWR_CR1_LPMS_0

#define PWR_CR1_LPMS_0 (0x1UL << PWR_CR1_LPMS_Pos)

0x00000001

◆ PWR_CR1_LPMS_1

#define PWR_CR1_LPMS_1 (0x2UL << PWR_CR1_LPMS_Pos)

0x00000002

◆ PWR_CR1_LPMS_Msk

#define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos)

0x00000007

◆ PWR_CR1_LPMS_Pos

#define PWR_CR1_LPMS_Pos (0U)

◆ PWR_CR1_LPR

#define PWR_CR1_LPR PWR_CR1_LPR_Msk

Regulator Low-Power Run mode

◆ PWR_CR1_LPR_Msk

#define PWR_CR1_LPR_Msk (0x1UL << PWR_CR1_LPR_Pos)

0x00004000

◆ PWR_CR1_LPR_Pos

#define PWR_CR1_LPR_Pos (14U)

◆ PWR_CR1_VOS

#define PWR_CR1_VOS PWR_CR1_VOS_Msk

Voltage scaling

◆ PWR_CR1_VOS_0

#define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_Pos)

Voltage scaling bit 0

◆ PWR_CR1_VOS_1

#define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_Pos)

Voltage scaling bit 1

◆ PWR_CR1_VOS_Msk

#define PWR_CR1_VOS_Msk (0x3UL << PWR_CR1_VOS_Pos)

0x00000600

◆ PWR_CR1_VOS_Pos

#define PWR_CR1_VOS_Pos (9U)

◆ PWR_CR3_APC

#define PWR_CR3_APC PWR_CR3_APC_Msk

Apply pull-up and pull-down configuration

◆ PWR_CR3_APC_Msk

#define PWR_CR3_APC_Msk (0x1UL << PWR_CR3_APC_Pos)

0x00000400

◆ PWR_CR3_APC_Pos

#define PWR_CR3_APC_Pos (10U)

◆ PWR_CR3_EIWUL

#define PWR_CR3_EIWUL PWR_CR3_EIWUL_Msk

Enable Internal Wake-up line

◆ PWR_CR3_EIWUL_Msk

#define PWR_CR3_EIWUL_Msk (0x1UL << PWR_CR3_EIWUL_Pos)

0x00008000

◆ PWR_CR3_EIWUL_Pos

#define PWR_CR3_EIWUL_Pos (15U)

◆ PWR_CR3_EWUP

#define PWR_CR3_EWUP PWR_CR3_EWUP_Msk

Enable all Wake-Up Pins

◆ PWR_CR3_EWUP1

#define PWR_CR3_EWUP1 PWR_CR3_EWUP1_Msk

Enable WKUP pin 1

◆ PWR_CR3_EWUP1_Msk

#define PWR_CR3_EWUP1_Msk (0x1UL << PWR_CR3_EWUP1_Pos)

0x00000001

◆ PWR_CR3_EWUP1_Pos

#define PWR_CR3_EWUP1_Pos (0U)

◆ PWR_CR3_EWUP2

#define PWR_CR3_EWUP2 PWR_CR3_EWUP2_Msk

Enable WKUP pin 2

◆ PWR_CR3_EWUP2_Msk

#define PWR_CR3_EWUP2_Msk (0x1UL << PWR_CR3_EWUP2_Pos)

0x00000002

◆ PWR_CR3_EWUP2_Pos

#define PWR_CR3_EWUP2_Pos (1U)

◆ PWR_CR3_EWUP4

#define PWR_CR3_EWUP4 PWR_CR3_EWUP4_Msk

Enable WKUP pin 4

◆ PWR_CR3_EWUP4_Msk

#define PWR_CR3_EWUP4_Msk (0x1UL << PWR_CR3_EWUP4_Pos)

0x00000008

◆ PWR_CR3_EWUP4_Pos

#define PWR_CR3_EWUP4_Pos (3U)

◆ PWR_CR3_EWUP6

#define PWR_CR3_EWUP6 PWR_CR3_EWUP6_Msk

Enable WKUP pin 6

◆ PWR_CR3_EWUP6_Msk

#define PWR_CR3_EWUP6_Msk (0x1UL << PWR_CR3_EWUP6_Pos)

0x00000020

◆ PWR_CR3_EWUP6_Pos

#define PWR_CR3_EWUP6_Pos (5U)

◆ PWR_CR3_EWUP_Msk

#define PWR_CR3_EWUP_Msk (0x2BUL << PWR_CR3_EWUP_Pos)

0x0000002B

◆ PWR_CR3_EWUP_Pos

#define PWR_CR3_EWUP_Pos (0U)

◆ PWR_CR4_VBE

#define PWR_CR4_VBE PWR_CR4_VBE_Msk

VBAT Battery charging Enable

◆ PWR_CR4_VBE_Msk

#define PWR_CR4_VBE_Msk (0x1UL << PWR_CR4_VBE_Pos)

0x00000100

◆ PWR_CR4_VBE_Pos

#define PWR_CR4_VBE_Pos (8U)

◆ PWR_CR4_VBRS

#define PWR_CR4_VBRS PWR_CR4_VBRS_Msk

VBAT Battery charging Resistor Selection

◆ PWR_CR4_VBRS_Msk

#define PWR_CR4_VBRS_Msk (0x1UL << PWR_CR4_VBRS_Pos)

0x00000200

◆ PWR_CR4_VBRS_Pos

#define PWR_CR4_VBRS_Pos (9U)

◆ PWR_CR4_WP

#define PWR_CR4_WP PWR_CR4_WP_Msk

all Wake-Up Pin polarity

◆ PWR_CR4_WP1

#define PWR_CR4_WP1 PWR_CR4_WP1_Msk

Wake-Up Pin 1 polarity

◆ PWR_CR4_WP1_Msk

#define PWR_CR4_WP1_Msk (0x1UL << PWR_CR4_WP1_Pos)

0x00000001

◆ PWR_CR4_WP1_Pos

#define PWR_CR4_WP1_Pos (0U)

◆ PWR_CR4_WP2

#define PWR_CR4_WP2 PWR_CR4_WP2_Msk

Wake-Up Pin 2 polarity

◆ PWR_CR4_WP2_Msk

#define PWR_CR4_WP2_Msk (0x1UL << PWR_CR4_WP2_Pos)

0x00000002

◆ PWR_CR4_WP2_Pos

#define PWR_CR4_WP2_Pos (1U)

◆ PWR_CR4_WP4

#define PWR_CR4_WP4 PWR_CR4_WP4_Msk

Wake-Up Pin 4 polarity

◆ PWR_CR4_WP4_Msk

#define PWR_CR4_WP4_Msk (0x1UL << PWR_CR4_WP4_Pos)

0x00000008

◆ PWR_CR4_WP4_Pos

#define PWR_CR4_WP4_Pos (3U)

◆ PWR_CR4_WP6

#define PWR_CR4_WP6 PWR_CR4_WP6_Msk

Wake-Up Pin 6 polarity

◆ PWR_CR4_WP6_Msk

#define PWR_CR4_WP6_Msk (0x1UL << PWR_CR4_WP6_Pos)

0x00000020

◆ PWR_CR4_WP6_Pos

#define PWR_CR4_WP6_Pos (5U)

◆ PWR_CR4_WP_Msk

#define PWR_CR4_WP_Msk (0x2BUL << PWR_CR4_WP_Pos)

0x0000002B

◆ PWR_CR4_WP_Pos

#define PWR_CR4_WP_Pos (0U)

◆ PWR_PDCRA_PD0

#define PWR_PDCRA_PD0 PWR_PDCRA_PD0_Msk

Pin PA0 Pull-Down set

◆ PWR_PDCRA_PD0_Msk

#define PWR_PDCRA_PD0_Msk (0x1UL << PWR_PDCRA_PD0_Pos)

0x00000001

◆ PWR_PDCRA_PD0_Pos

#define PWR_PDCRA_PD0_Pos (0U)

◆ PWR_PDCRA_PD1

#define PWR_PDCRA_PD1 PWR_PDCRA_PD1_Msk

Pin PA1 Pull-Down set

◆ PWR_PDCRA_PD10

#define PWR_PDCRA_PD10 PWR_PDCRA_PD10_Msk

Pin PA10 Pull-Down set

◆ PWR_PDCRA_PD10_Msk

#define PWR_PDCRA_PD10_Msk (0x1UL << PWR_PDCRA_PD10_Pos)

0x00000400

◆ PWR_PDCRA_PD10_Pos

#define PWR_PDCRA_PD10_Pos (10U)

◆ PWR_PDCRA_PD11

#define PWR_PDCRA_PD11 PWR_PDCRA_PD11_Msk

Pin PA11 Pull-Down set

◆ PWR_PDCRA_PD11_Msk

#define PWR_PDCRA_PD11_Msk (0x1UL << PWR_PDCRA_PD11_Pos)

0x00000800

◆ PWR_PDCRA_PD11_Pos

#define PWR_PDCRA_PD11_Pos (11U)

◆ PWR_PDCRA_PD12

#define PWR_PDCRA_PD12 PWR_PDCRA_PD12_Msk

Pin PA12 Pull-Down set

◆ PWR_PDCRA_PD12_Msk

#define PWR_PDCRA_PD12_Msk (0x1UL << PWR_PDCRA_PD12_Pos)

0x00001000

◆ PWR_PDCRA_PD12_Pos

#define PWR_PDCRA_PD12_Pos (12U)

◆ PWR_PDCRA_PD13

#define PWR_PDCRA_PD13 PWR_PDCRA_PD13_Msk

Pin PA13 Pull-Down set

◆ PWR_PDCRA_PD13_Msk

#define PWR_PDCRA_PD13_Msk (0x1UL << PWR_PDCRA_PD13_Pos)

0x00002000

◆ PWR_PDCRA_PD13_Pos

#define PWR_PDCRA_PD13_Pos (13U)

◆ PWR_PDCRA_PD14

#define PWR_PDCRA_PD14 PWR_PDCRA_PD14_Msk

Pin PA14 Pull-Down set

◆ PWR_PDCRA_PD14_Msk

#define PWR_PDCRA_PD14_Msk (0x1UL << PWR_PDCRA_PD14_Pos)

0x00004000

◆ PWR_PDCRA_PD14_Pos

#define PWR_PDCRA_PD14_Pos (14U)

◆ PWR_PDCRA_PD15

#define PWR_PDCRA_PD15 PWR_PDCRA_PD15_Msk

Pin PA15 Pull-Down set

◆ PWR_PDCRA_PD15_Msk

#define PWR_PDCRA_PD15_Msk (0x1UL << PWR_PDCRA_PD15_Pos)

0x00008000

◆ PWR_PDCRA_PD15_Pos

#define PWR_PDCRA_PD15_Pos (15U)

◆ PWR_PDCRA_PD1_Msk

#define PWR_PDCRA_PD1_Msk (0x1UL << PWR_PDCRA_PD1_Pos)

0x00000002

◆ PWR_PDCRA_PD1_Pos

#define PWR_PDCRA_PD1_Pos (1U)

◆ PWR_PDCRA_PD2

#define PWR_PDCRA_PD2 PWR_PDCRA_PD2_Msk

Pin PA2 Pull-Down set

◆ PWR_PDCRA_PD2_Msk

#define PWR_PDCRA_PD2_Msk (0x1UL << PWR_PDCRA_PD2_Pos)

0x00000004

◆ PWR_PDCRA_PD2_Pos

#define PWR_PDCRA_PD2_Pos (2U)

◆ PWR_PDCRA_PD3

#define PWR_PDCRA_PD3 PWR_PDCRA_PD3_Msk

Pin PA3 Pull-Down set

◆ PWR_PDCRA_PD3_Msk

#define PWR_PDCRA_PD3_Msk (0x1UL << PWR_PDCRA_PD3_Pos)

0x00000008

◆ PWR_PDCRA_PD3_Pos

#define PWR_PDCRA_PD3_Pos (3U)

◆ PWR_PDCRA_PD4

#define PWR_PDCRA_PD4 PWR_PDCRA_PD4_Msk

Pin PA4 Pull-Down set

◆ PWR_PDCRA_PD4_Msk

#define PWR_PDCRA_PD4_Msk (0x1UL << PWR_PDCRA_PD4_Pos)

0x00000010

◆ PWR_PDCRA_PD4_Pos

#define PWR_PDCRA_PD4_Pos (4U)

◆ PWR_PDCRA_PD5

#define PWR_PDCRA_PD5 PWR_PDCRA_PD5_Msk

Pin PA5 Pull-Down set

◆ PWR_PDCRA_PD5_Msk

#define PWR_PDCRA_PD5_Msk (0x1UL << PWR_PDCRA_PD5_Pos)

0x00000020

◆ PWR_PDCRA_PD5_Pos

#define PWR_PDCRA_PD5_Pos (5U)

◆ PWR_PDCRA_PD6

#define PWR_PDCRA_PD6 PWR_PDCRA_PD6_Msk

Pin PA6 Pull-Down set

◆ PWR_PDCRA_PD6_Msk

#define PWR_PDCRA_PD6_Msk (0x1UL << PWR_PDCRA_PD6_Pos)

0x00000040

◆ PWR_PDCRA_PD6_Pos

#define PWR_PDCRA_PD6_Pos (6U)

◆ PWR_PDCRA_PD7

#define PWR_PDCRA_PD7 PWR_PDCRA_PD7_Msk

Pin PA7 Pull-Down set

◆ PWR_PDCRA_PD7_Msk

#define PWR_PDCRA_PD7_Msk (0x1UL << PWR_PDCRA_PD7_Pos)

0x00000080

◆ PWR_PDCRA_PD7_Pos

#define PWR_PDCRA_PD7_Pos (7U)

◆ PWR_PDCRA_PD8

#define PWR_PDCRA_PD8 PWR_PDCRA_PD8_Msk

Pin PA8 Pull-Down set

◆ PWR_PDCRA_PD8_Msk

#define PWR_PDCRA_PD8_Msk (0x1UL << PWR_PDCRA_PD8_Pos)

0x00000100

◆ PWR_PDCRA_PD8_Pos

#define PWR_PDCRA_PD8_Pos (8U)

◆ PWR_PDCRA_PD9

#define PWR_PDCRA_PD9 PWR_PDCRA_PD9_Msk

Pin PA9 Pull-Down set

◆ PWR_PDCRA_PD9_Msk

#define PWR_PDCRA_PD9_Msk (0x1UL << PWR_PDCRA_PD9_Pos)

0x00000200

◆ PWR_PDCRA_PD9_Pos

#define PWR_PDCRA_PD9_Pos (9U)

◆ PWR_PDCRB_PD0

#define PWR_PDCRB_PD0 PWR_PDCRB_PD0_Msk

Pin PB0 Pull-Down set

◆ PWR_PDCRB_PD0_Msk

#define PWR_PDCRB_PD0_Msk (0x1UL << PWR_PDCRB_PD0_Pos)

0x00000001

◆ PWR_PDCRB_PD0_Pos

#define PWR_PDCRB_PD0_Pos (0U)

◆ PWR_PDCRB_PD1

#define PWR_PDCRB_PD1 PWR_PDCRB_PD1_Msk

Pin PB1 Pull-Down set

◆ PWR_PDCRB_PD10

#define PWR_PDCRB_PD10 PWR_PDCRB_PD10_Msk

Pin PB10 Pull-Down set

◆ PWR_PDCRB_PD10_Msk

#define PWR_PDCRB_PD10_Msk (0x1UL << PWR_PDCRB_PD10_Pos)

0x00000400

◆ PWR_PDCRB_PD10_Pos

#define PWR_PDCRB_PD10_Pos (10U)

◆ PWR_PDCRB_PD11

#define PWR_PDCRB_PD11 PWR_PDCRB_PD11_Msk

Pin PB11 Pull-Down set

◆ PWR_PDCRB_PD11_Msk

#define PWR_PDCRB_PD11_Msk (0x1UL << PWR_PDCRB_PD11_Pos)

0x00000800

◆ PWR_PDCRB_PD11_Pos

#define PWR_PDCRB_PD11_Pos (11U)

◆ PWR_PDCRB_PD12

#define PWR_PDCRB_PD12 PWR_PDCRB_PD12_Msk

Pin PB12 Pull-Down set

◆ PWR_PDCRB_PD12_Msk

#define PWR_PDCRB_PD12_Msk (0x1UL << PWR_PDCRB_PD12_Pos)

0x00001000

◆ PWR_PDCRB_PD12_Pos

#define PWR_PDCRB_PD12_Pos (12U)

◆ PWR_PDCRB_PD13

#define PWR_PDCRB_PD13 PWR_PDCRB_PD13_Msk

Pin PB13 Pull-Down set

◆ PWR_PDCRB_PD13_Msk

#define PWR_PDCRB_PD13_Msk (0x1UL << PWR_PDCRB_PD13_Pos)

0x00002000

◆ PWR_PDCRB_PD13_Pos

#define PWR_PDCRB_PD13_Pos (13U)

◆ PWR_PDCRB_PD14

#define PWR_PDCRB_PD14 PWR_PDCRB_PD14_Msk

Pin PB14 Pull-Down set

◆ PWR_PDCRB_PD14_Msk

#define PWR_PDCRB_PD14_Msk (0x1UL << PWR_PDCRB_PD14_Pos)

0x00004000

◆ PWR_PDCRB_PD14_Pos

#define PWR_PDCRB_PD14_Pos (14U)

◆ PWR_PDCRB_PD15

#define PWR_PDCRB_PD15 PWR_PDCRB_PD15_Msk

Pin PB15 Pull-Down set

◆ PWR_PDCRB_PD15_Msk

#define PWR_PDCRB_PD15_Msk (0x1UL << PWR_PDCRB_PD15_Pos)

0x00008000

◆ PWR_PDCRB_PD15_Pos

#define PWR_PDCRB_PD15_Pos (15U)

◆ PWR_PDCRB_PD1_Msk

#define PWR_PDCRB_PD1_Msk (0x1UL << PWR_PDCRB_PD1_Pos)

0x00000002

◆ PWR_PDCRB_PD1_Pos

#define PWR_PDCRB_PD1_Pos (1U)

◆ PWR_PDCRB_PD2

#define PWR_PDCRB_PD2 PWR_PDCRB_PD2_Msk

Pin PB2 Pull-Down set

◆ PWR_PDCRB_PD2_Msk

#define PWR_PDCRB_PD2_Msk (0x1UL << PWR_PDCRB_PD2_Pos)

0x00000004

◆ PWR_PDCRB_PD2_Pos

#define PWR_PDCRB_PD2_Pos (2U)

◆ PWR_PDCRB_PD3

#define PWR_PDCRB_PD3 PWR_PDCRB_PD3_Msk

Pin PB3 Pull-Down set

◆ PWR_PDCRB_PD3_Msk

#define PWR_PDCRB_PD3_Msk (0x1UL << PWR_PDCRB_PD3_Pos)

0x00000008

◆ PWR_PDCRB_PD3_Pos

#define PWR_PDCRB_PD3_Pos (3U)

◆ PWR_PDCRB_PD4

#define PWR_PDCRB_PD4 PWR_PDCRB_PD4_Msk

Pin PB4 Pull-Down set

◆ PWR_PDCRB_PD4_Msk

#define PWR_PDCRB_PD4_Msk (0x1UL << PWR_PDCRB_PD4_Pos)

0x00000010

◆ PWR_PDCRB_PD4_Pos

#define PWR_PDCRB_PD4_Pos (4U)

◆ PWR_PDCRB_PD5

#define PWR_PDCRB_PD5 PWR_PDCRB_PD5_Msk

Pin PB5 Pull-Down set

◆ PWR_PDCRB_PD5_Msk

#define PWR_PDCRB_PD5_Msk (0x1UL << PWR_PDCRB_PD5_Pos)

0x00000020

◆ PWR_PDCRB_PD5_Pos

#define PWR_PDCRB_PD5_Pos (5U)

◆ PWR_PDCRB_PD6

#define PWR_PDCRB_PD6 PWR_PDCRB_PD6_Msk

Pin PB6 Pull-Down set

◆ PWR_PDCRB_PD6_Msk

#define PWR_PDCRB_PD6_Msk (0x1UL << PWR_PDCRB_PD6_Pos)

0x00000040

◆ PWR_PDCRB_PD6_Pos

#define PWR_PDCRB_PD6_Pos (6U)

◆ PWR_PDCRB_PD7

#define PWR_PDCRB_PD7 PWR_PDCRB_PD7_Msk

Pin PB7 Pull-Down set

◆ PWR_PDCRB_PD7_Msk

#define PWR_PDCRB_PD7_Msk (0x1UL << PWR_PDCRB_PD7_Pos)

0x00000080

◆ PWR_PDCRB_PD7_Pos

#define PWR_PDCRB_PD7_Pos (7U)

◆ PWR_PDCRB_PD8

#define PWR_PDCRB_PD8 PWR_PDCRB_PD8_Msk

Pin PB8 Pull-Down set

◆ PWR_PDCRB_PD8_Msk

#define PWR_PDCRB_PD8_Msk (0x1UL << PWR_PDCRB_PD8_Pos)

0x00000100

◆ PWR_PDCRB_PD8_Pos

#define PWR_PDCRB_PD8_Pos (8U)

◆ PWR_PDCRB_PD9

#define PWR_PDCRB_PD9 PWR_PDCRB_PD9_Msk

Pin PB9 Pull-Down set

◆ PWR_PDCRB_PD9_Msk

#define PWR_PDCRB_PD9_Msk (0x1UL << PWR_PDCRB_PD9_Pos)

0x00000200

◆ PWR_PDCRB_PD9_Pos

#define PWR_PDCRB_PD9_Pos (9U)

◆ PWR_PDCRC_PD13

#define PWR_PDCRC_PD13 PWR_PDCRC_PD13_Msk

Pin PC13 Pull-Down set

◆ PWR_PDCRC_PD13_Msk

#define PWR_PDCRC_PD13_Msk (0x1UL << PWR_PDCRC_PD13_Pos)

0x00002000

◆ PWR_PDCRC_PD13_Pos

#define PWR_PDCRC_PD13_Pos (13U)

◆ PWR_PDCRC_PD14

#define PWR_PDCRC_PD14 PWR_PDCRC_PD14_Msk

Pin PC14 Pull-Down set

◆ PWR_PDCRC_PD14_Msk

#define PWR_PDCRC_PD14_Msk (0x1UL << PWR_PDCRC_PD14_Pos)

0x00004000

◆ PWR_PDCRC_PD14_Pos

#define PWR_PDCRC_PD14_Pos (14U)

◆ PWR_PDCRC_PD15

#define PWR_PDCRC_PD15 PWR_PDCRC_PD15_Msk

Pin PC15 Pull-Down set

◆ PWR_PDCRC_PD15_Msk

#define PWR_PDCRC_PD15_Msk (0x1UL << PWR_PDCRC_PD15_Pos)

0x00008000

◆ PWR_PDCRC_PD15_Pos

#define PWR_PDCRC_PD15_Pos (15U)

◆ PWR_PDCRC_PD6

#define PWR_PDCRC_PD6 PWR_PDCRC_PD6_Msk

Pin PC6 Pull-Down set

◆ PWR_PDCRC_PD6_Msk

#define PWR_PDCRC_PD6_Msk (0x1UL << PWR_PDCRC_PD6_Pos)

0x00000040

◆ PWR_PDCRC_PD6_Pos

#define PWR_PDCRC_PD6_Pos (6U)

◆ PWR_PDCRC_PD7

#define PWR_PDCRC_PD7 PWR_PDCRC_PD7_Msk

Pin PC7 Pull-Down set

◆ PWR_PDCRC_PD7_Msk

#define PWR_PDCRC_PD7_Msk (0x1UL << PWR_PDCRC_PD7_Pos)

0x00000080

◆ PWR_PDCRC_PD7_Pos

#define PWR_PDCRC_PD7_Pos (7U)

◆ PWR_PDCRD_PD0

#define PWR_PDCRD_PD0 PWR_PDCRD_PD0_Msk

Pin PD0 Pull-Down set

◆ PWR_PDCRD_PD0_Msk

#define PWR_PDCRD_PD0_Msk (0x1UL << PWR_PDCRD_PD0_Pos)

0x00000001

◆ PWR_PDCRD_PD0_Pos

#define PWR_PDCRD_PD0_Pos (0U)

◆ PWR_PDCRD_PD1

#define PWR_PDCRD_PD1 PWR_PDCRD_PD1_Msk

Pin PD1 Pull-Down set

◆ PWR_PDCRD_PD1_Msk

#define PWR_PDCRD_PD1_Msk (0x1UL << PWR_PDCRD_PD1_Pos)

0x00000002

◆ PWR_PDCRD_PD1_Pos

#define PWR_PDCRD_PD1_Pos (1U)

◆ PWR_PDCRD_PD2

#define PWR_PDCRD_PD2 PWR_PDCRD_PD2_Msk

Pin PD2 Pull-Down set

◆ PWR_PDCRD_PD2_Msk

#define PWR_PDCRD_PD2_Msk (0x1UL << PWR_PDCRD_PD2_Pos)

0x00000004

◆ PWR_PDCRD_PD2_Pos

#define PWR_PDCRD_PD2_Pos (2U)

◆ PWR_PDCRD_PD3

#define PWR_PDCRD_PD3 PWR_PDCRD_PD3_Msk

Pin PD3 Pull-Down set

◆ PWR_PDCRD_PD3_Msk

#define PWR_PDCRD_PD3_Msk (0x1UL << PWR_PDCRD_PD3_Pos)

0x00000008

◆ PWR_PDCRD_PD3_Pos

#define PWR_PDCRD_PD3_Pos (3U)

◆ PWR_PDCRF_PD0

#define PWR_PDCRF_PD0 PWR_PDCRF_PD0_Msk

Pin PF0 Pull-Down set

◆ PWR_PDCRF_PD0_Msk

#define PWR_PDCRF_PD0_Msk (0x1UL << PWR_PDCRF_PD0_Pos)

0x00000001

◆ PWR_PDCRF_PD0_Pos

#define PWR_PDCRF_PD0_Pos (0U)

◆ PWR_PDCRF_PD1

#define PWR_PDCRF_PD1 PWR_PDCRF_PD1_Msk

Pin PF1 Pull-Down set

◆ PWR_PDCRF_PD1_Msk

#define PWR_PDCRF_PD1_Msk (0x1UL << PWR_PDCRF_PD1_Pos)

0x00000002

◆ PWR_PDCRF_PD1_Pos

#define PWR_PDCRF_PD1_Pos (1U)

◆ PWR_PDCRF_PD2

#define PWR_PDCRF_PD2 PWR_PDCRF_PD2_Msk

Pin PF2 Pull-Down set

◆ PWR_PDCRF_PD2_Msk

#define PWR_PDCRF_PD2_Msk (0x1UL << PWR_PDCRF_PD2_Pos)

0x00000004

◆ PWR_PDCRF_PD2_Pos

#define PWR_PDCRF_PD2_Pos (2U)

◆ PWR_PUCRA_PU0

#define PWR_PUCRA_PU0 PWR_PUCRA_PU0_Msk

Pin PA0 Pull-Up set

◆ PWR_PUCRA_PU0_Msk

#define PWR_PUCRA_PU0_Msk (0x1UL << PWR_PUCRA_PU0_Pos)

0x00000001

◆ PWR_PUCRA_PU0_Pos

#define PWR_PUCRA_PU0_Pos (0U)

◆ PWR_PUCRA_PU1

#define PWR_PUCRA_PU1 PWR_PUCRA_PU1_Msk

Pin PA1 Pull-Up set

◆ PWR_PUCRA_PU10

#define PWR_PUCRA_PU10 PWR_PUCRA_PU10_Msk

Pin PA10 Pull-Up set

◆ PWR_PUCRA_PU10_Msk

#define PWR_PUCRA_PU10_Msk (0x1UL << PWR_PUCRA_PU10_Pos)

0x00000400

◆ PWR_PUCRA_PU10_Pos

#define PWR_PUCRA_PU10_Pos (10U)

◆ PWR_PUCRA_PU11

#define PWR_PUCRA_PU11 PWR_PUCRA_PU11_Msk

Pin PA11 Pull-Up set

◆ PWR_PUCRA_PU11_Msk

#define PWR_PUCRA_PU11_Msk (0x1UL << PWR_PUCRA_PU11_Pos)

0x00000800

◆ PWR_PUCRA_PU11_Pos

#define PWR_PUCRA_PU11_Pos (11U)

◆ PWR_PUCRA_PU12

#define PWR_PUCRA_PU12 PWR_PUCRA_PU12_Msk

Pin PA12 Pull-Up set

◆ PWR_PUCRA_PU12_Msk

#define PWR_PUCRA_PU12_Msk (0x1UL << PWR_PUCRA_PU12_Pos)

0x00001000

◆ PWR_PUCRA_PU12_Pos

#define PWR_PUCRA_PU12_Pos (12U)

◆ PWR_PUCRA_PU13

#define PWR_PUCRA_PU13 PWR_PUCRA_PU13_Msk

Pin PA13 Pull-Up set

◆ PWR_PUCRA_PU13_Msk

#define PWR_PUCRA_PU13_Msk (0x1UL << PWR_PUCRA_PU13_Pos)

0x00002000

◆ PWR_PUCRA_PU13_Pos

#define PWR_PUCRA_PU13_Pos (13U)

◆ PWR_PUCRA_PU14

#define PWR_PUCRA_PU14 PWR_PUCRA_PU14_Msk

Pin PA14 Pull-Up set

◆ PWR_PUCRA_PU14_Msk

#define PWR_PUCRA_PU14_Msk (0x1UL << PWR_PUCRA_PU14_Pos)

0x00004000

◆ PWR_PUCRA_PU14_Pos

#define PWR_PUCRA_PU14_Pos (14U)

◆ PWR_PUCRA_PU15

#define PWR_PUCRA_PU15 PWR_PUCRA_PU15_Msk

Pin PA15 Pull-Up set

◆ PWR_PUCRA_PU15_Msk

#define PWR_PUCRA_PU15_Msk (0x1UL << PWR_PUCRA_PU15_Pos)

0x00008000

◆ PWR_PUCRA_PU15_Pos

#define PWR_PUCRA_PU15_Pos (15U)

◆ PWR_PUCRA_PU1_Msk

#define PWR_PUCRA_PU1_Msk (0x1UL << PWR_PUCRA_PU1_Pos)

0x00000002

◆ PWR_PUCRA_PU1_Pos

#define PWR_PUCRA_PU1_Pos (1U)

◆ PWR_PUCRA_PU2

#define PWR_PUCRA_PU2 PWR_PUCRA_PU2_Msk

Pin PA2 Pull-Up set

◆ PWR_PUCRA_PU2_Msk

#define PWR_PUCRA_PU2_Msk (0x1UL << PWR_PUCRA_PU2_Pos)

0x00000004

◆ PWR_PUCRA_PU2_Pos

#define PWR_PUCRA_PU2_Pos (2U)

◆ PWR_PUCRA_PU3

#define PWR_PUCRA_PU3 PWR_PUCRA_PU3_Msk

Pin PA3 Pull-Up set

◆ PWR_PUCRA_PU3_Msk

#define PWR_PUCRA_PU3_Msk (0x1UL << PWR_PUCRA_PU3_Pos)

0x00000008

◆ PWR_PUCRA_PU3_Pos

#define PWR_PUCRA_PU3_Pos (3U)

◆ PWR_PUCRA_PU4

#define PWR_PUCRA_PU4 PWR_PUCRA_PU4_Msk

Pin PA4 Pull-Up set

◆ PWR_PUCRA_PU4_Msk

#define PWR_PUCRA_PU4_Msk (0x1UL << PWR_PUCRA_PU4_Pos)

0x00000010

◆ PWR_PUCRA_PU4_Pos

#define PWR_PUCRA_PU4_Pos (4U)

◆ PWR_PUCRA_PU5

#define PWR_PUCRA_PU5 PWR_PUCRA_PU5_Msk

Pin PA5 Pull-Up set

◆ PWR_PUCRA_PU5_Msk

#define PWR_PUCRA_PU5_Msk (0x1UL << PWR_PUCRA_PU5_Pos)

0x00000020

◆ PWR_PUCRA_PU5_Pos

#define PWR_PUCRA_PU5_Pos (5U)

◆ PWR_PUCRA_PU6

#define PWR_PUCRA_PU6 PWR_PUCRA_PU6_Msk

Pin PA6 Pull-Up set

◆ PWR_PUCRA_PU6_Msk

#define PWR_PUCRA_PU6_Msk (0x1UL << PWR_PUCRA_PU6_Pos)

0x00000040

◆ PWR_PUCRA_PU6_Pos

#define PWR_PUCRA_PU6_Pos (6U)

◆ PWR_PUCRA_PU7

#define PWR_PUCRA_PU7 PWR_PUCRA_PU7_Msk

Pin PA7 Pull-Up set

◆ PWR_PUCRA_PU7_Msk

#define PWR_PUCRA_PU7_Msk (0x1UL << PWR_PUCRA_PU7_Pos)

0x00000080

◆ PWR_PUCRA_PU7_Pos

#define PWR_PUCRA_PU7_Pos (7U)

◆ PWR_PUCRA_PU8

#define PWR_PUCRA_PU8 PWR_PUCRA_PU8_Msk

Pin PA8 Pull-Up set

◆ PWR_PUCRA_PU8_Msk

#define PWR_PUCRA_PU8_Msk (0x1UL << PWR_PUCRA_PU8_Pos)

0x00000100

◆ PWR_PUCRA_PU8_Pos

#define PWR_PUCRA_PU8_Pos (8U)

◆ PWR_PUCRA_PU9

#define PWR_PUCRA_PU9 PWR_PUCRA_PU9_Msk

Pin PA9 Pull-Up set

◆ PWR_PUCRA_PU9_Msk

#define PWR_PUCRA_PU9_Msk (0x1UL << PWR_PUCRA_PU9_Pos)

0x00000200

◆ PWR_PUCRA_PU9_Pos

#define PWR_PUCRA_PU9_Pos (9U)

◆ PWR_PUCRB_PU0

#define PWR_PUCRB_PU0 PWR_PUCRB_PU0_Msk

Pin PB0 Pull-Up set

◆ PWR_PUCRB_PU0_Msk

#define PWR_PUCRB_PU0_Msk (0x1UL << PWR_PUCRB_PU0_Pos)

0x00000001

◆ PWR_PUCRB_PU0_Pos

#define PWR_PUCRB_PU0_Pos (0U)

◆ PWR_PUCRB_PU1

#define PWR_PUCRB_PU1 PWR_PUCRB_PU1_Msk

Pin PB1 Pull-Up set

◆ PWR_PUCRB_PU10

#define PWR_PUCRB_PU10 PWR_PUCRB_PU10_Msk

Pin PB10 Pull-Up set

◆ PWR_PUCRB_PU10_Msk

#define PWR_PUCRB_PU10_Msk (0x1UL << PWR_PUCRB_PU10_Pos)

0x00000400

◆ PWR_PUCRB_PU10_Pos

#define PWR_PUCRB_PU10_Pos (10U)

◆ PWR_PUCRB_PU11

#define PWR_PUCRB_PU11 PWR_PUCRB_PU11_Msk

Pin PB11 Pull-Up set

◆ PWR_PUCRB_PU11_Msk

#define PWR_PUCRB_PU11_Msk (0x1UL << PWR_PUCRB_PU11_Pos)

0x00000800

◆ PWR_PUCRB_PU11_Pos

#define PWR_PUCRB_PU11_Pos (11U)

◆ PWR_PUCRB_PU12

#define PWR_PUCRB_PU12 PWR_PUCRB_PU12_Msk

Pin PB12 Pull-Up set

◆ PWR_PUCRB_PU12_Msk

#define PWR_PUCRB_PU12_Msk (0x1UL << PWR_PUCRB_PU12_Pos)

0x00001000

◆ PWR_PUCRB_PU12_Pos

#define PWR_PUCRB_PU12_Pos (12U)

◆ PWR_PUCRB_PU13

#define PWR_PUCRB_PU13 PWR_PUCRB_PU13_Msk

Pin PB13 Pull-Up set

◆ PWR_PUCRB_PU13_Msk

#define PWR_PUCRB_PU13_Msk (0x1UL << PWR_PUCRB_PU13_Pos)

0x00002000

◆ PWR_PUCRB_PU13_Pos

#define PWR_PUCRB_PU13_Pos (13U)

◆ PWR_PUCRB_PU14

#define PWR_PUCRB_PU14 PWR_PUCRB_PU14_Msk

Pin PB14 Pull-Up set

◆ PWR_PUCRB_PU14_Msk

#define PWR_PUCRB_PU14_Msk (0x1UL << PWR_PUCRB_PU14_Pos)

0x00004000

◆ PWR_PUCRB_PU14_Pos

#define PWR_PUCRB_PU14_Pos (14U)

◆ PWR_PUCRB_PU15

#define PWR_PUCRB_PU15 PWR_PUCRB_PU15_Msk

Pin PB15 Pull-Up set

◆ PWR_PUCRB_PU15_Msk

#define PWR_PUCRB_PU15_Msk (0x1UL << PWR_PUCRB_PU15_Pos)

0x00008000

◆ PWR_PUCRB_PU15_Pos

#define PWR_PUCRB_PU15_Pos (15U)

◆ PWR_PUCRB_PU1_Msk

#define PWR_PUCRB_PU1_Msk (0x1UL << PWR_PUCRB_PU1_Pos)

0x00000002

◆ PWR_PUCRB_PU1_Pos

#define PWR_PUCRB_PU1_Pos (1U)

◆ PWR_PUCRB_PU2

#define PWR_PUCRB_PU2 PWR_PUCRB_PU2_Msk

Pin PB2 Pull-Up set

◆ PWR_PUCRB_PU2_Msk

#define PWR_PUCRB_PU2_Msk (0x1UL << PWR_PUCRB_PU2_Pos)

0x00000004

◆ PWR_PUCRB_PU2_Pos

#define PWR_PUCRB_PU2_Pos (2U)

◆ PWR_PUCRB_PU3

#define PWR_PUCRB_PU3 PWR_PUCRB_PU3_Msk

Pin PB3 Pull-Up set

◆ PWR_PUCRB_PU3_Msk

#define PWR_PUCRB_PU3_Msk (0x1UL << PWR_PUCRB_PU3_Pos)

0x00000008

◆ PWR_PUCRB_PU3_Pos

#define PWR_PUCRB_PU3_Pos (3U)

◆ PWR_PUCRB_PU4

#define PWR_PUCRB_PU4 PWR_PUCRB_PU4_Msk

Pin PB4 Pull-Up set

◆ PWR_PUCRB_PU4_Msk

#define PWR_PUCRB_PU4_Msk (0x1UL << PWR_PUCRB_PU4_Pos)

0x00000010

◆ PWR_PUCRB_PU4_Pos

#define PWR_PUCRB_PU4_Pos (4U)

◆ PWR_PUCRB_PU5

#define PWR_PUCRB_PU5 PWR_PUCRB_PU5_Msk

Pin PB5 Pull-Up set

◆ PWR_PUCRB_PU5_Msk

#define PWR_PUCRB_PU5_Msk (0x1UL << PWR_PUCRB_PU5_Pos)

0x00000020

◆ PWR_PUCRB_PU5_Pos

#define PWR_PUCRB_PU5_Pos (5U)

◆ PWR_PUCRB_PU6

#define PWR_PUCRB_PU6 PWR_PUCRB_PU6_Msk

Pin PB6 Pull-Up set

◆ PWR_PUCRB_PU6_Msk

#define PWR_PUCRB_PU6_Msk (0x1UL << PWR_PUCRB_PU6_Pos)

0x00000040

◆ PWR_PUCRB_PU6_Pos

#define PWR_PUCRB_PU6_Pos (6U)

◆ PWR_PUCRB_PU7

#define PWR_PUCRB_PU7 PWR_PUCRB_PU7_Msk

Pin PB7 Pull-Up set

◆ PWR_PUCRB_PU7_Msk

#define PWR_PUCRB_PU7_Msk (0x1UL << PWR_PUCRB_PU7_Pos)

0x00000080

◆ PWR_PUCRB_PU7_Pos

#define PWR_PUCRB_PU7_Pos (7U)

◆ PWR_PUCRB_PU8

#define PWR_PUCRB_PU8 PWR_PUCRB_PU8_Msk

Pin PB8 Pull-Up set

◆ PWR_PUCRB_PU8_Msk

#define PWR_PUCRB_PU8_Msk (0x1UL << PWR_PUCRB_PU8_Pos)

0x00000100

◆ PWR_PUCRB_PU8_Pos

#define PWR_PUCRB_PU8_Pos (8U)

◆ PWR_PUCRB_PU9

#define PWR_PUCRB_PU9 PWR_PUCRB_PU9_Msk

Pin PB9 Pull-Up set

◆ PWR_PUCRB_PU9_Msk

#define PWR_PUCRB_PU9_Msk (0x1UL << PWR_PUCRB_PU9_Pos)

0x00000200

◆ PWR_PUCRB_PU9_Pos

#define PWR_PUCRB_PU9_Pos (9U)

◆ PWR_PUCRC_PU13

#define PWR_PUCRC_PU13 PWR_PUCRC_PU13_Msk

Pin PC13 Pull-Up set

◆ PWR_PUCRC_PU13_Msk

#define PWR_PUCRC_PU13_Msk (0x1UL << PWR_PUCRC_PU13_Pos)

0x00002000

◆ PWR_PUCRC_PU13_Pos

#define PWR_PUCRC_PU13_Pos (13U)

◆ PWR_PUCRC_PU14

#define PWR_PUCRC_PU14 PWR_PUCRC_PU14_Msk

Pin PC14 Pull-Up set

◆ PWR_PUCRC_PU14_Msk

#define PWR_PUCRC_PU14_Msk (0x1UL << PWR_PUCRC_PU14_Pos)

0x00004000

◆ PWR_PUCRC_PU14_Pos

#define PWR_PUCRC_PU14_Pos (14U)

◆ PWR_PUCRC_PU15

#define PWR_PUCRC_PU15 PWR_PUCRC_PU15_Msk

Pin PC15 Pull-Up set

◆ PWR_PUCRC_PU15_Msk

#define PWR_PUCRC_PU15_Msk (0x1UL << PWR_PUCRC_PU15_Pos)

0x00008000

◆ PWR_PUCRC_PU15_Pos

#define PWR_PUCRC_PU15_Pos (15U)

◆ PWR_PUCRC_PU6

#define PWR_PUCRC_PU6 PWR_PUCRC_PU6_Msk

Pin PC6 Pull-Up set

◆ PWR_PUCRC_PU6_Msk

#define PWR_PUCRC_PU6_Msk (0x1UL << PWR_PUCRC_PU6_Pos)

0x00000040

◆ PWR_PUCRC_PU6_Pos

#define PWR_PUCRC_PU6_Pos (6U)

◆ PWR_PUCRC_PU7

#define PWR_PUCRC_PU7 PWR_PUCRC_PU7_Msk

Pin PC7 Pull-Up set

◆ PWR_PUCRC_PU7_Msk

#define PWR_PUCRC_PU7_Msk (0x1UL << PWR_PUCRC_PU7_Pos)

0x00000080

◆ PWR_PUCRC_PU7_Pos

#define PWR_PUCRC_PU7_Pos (7U)

◆ PWR_PUCRD_PU0

#define PWR_PUCRD_PU0 PWR_PUCRD_PU0_Msk

Pin PD0 Pull-Up set

◆ PWR_PUCRD_PU0_Msk

#define PWR_PUCRD_PU0_Msk (0x1UL << PWR_PUCRD_PU0_Pos)

0x00000001

◆ PWR_PUCRD_PU0_Pos

#define PWR_PUCRD_PU0_Pos (0U)

◆ PWR_PUCRD_PU1

#define PWR_PUCRD_PU1 PWR_PUCRD_PU1_Msk

Pin PD1 Pull-Up set

◆ PWR_PUCRD_PU1_Msk

#define PWR_PUCRD_PU1_Msk (0x1UL << PWR_PUCRD_PU1_Pos)

0x00000002

◆ PWR_PUCRD_PU1_Pos

#define PWR_PUCRD_PU1_Pos (1U)

◆ PWR_PUCRD_PU2

#define PWR_PUCRD_PU2 PWR_PUCRD_PU2_Msk

Pin PD2 Pull-Up set

◆ PWR_PUCRD_PU2_Msk

#define PWR_PUCRD_PU2_Msk (0x1UL << PWR_PUCRD_PU2_Pos)

0x00000004

◆ PWR_PUCRD_PU2_Pos

#define PWR_PUCRD_PU2_Pos (2U)

◆ PWR_PUCRD_PU3

#define PWR_PUCRD_PU3 PWR_PUCRD_PU3_Msk

Pin PD3 Pull-Up set

◆ PWR_PUCRD_PU3_Msk

#define PWR_PUCRD_PU3_Msk (0x1UL << PWR_PUCRD_PU3_Pos)

0x00000008

◆ PWR_PUCRD_PU3_Pos

#define PWR_PUCRD_PU3_Pos (3U)

◆ PWR_PUCRF_PU0

#define PWR_PUCRF_PU0 PWR_PUCRF_PU0_Msk

Pin PF0 Pull-Up set

◆ PWR_PUCRF_PU0_Msk

#define PWR_PUCRF_PU0_Msk (0x1UL << PWR_PUCRF_PU0_Pos)

0x00000001

◆ PWR_PUCRF_PU0_Pos

#define PWR_PUCRF_PU0_Pos (0U)

◆ PWR_PUCRF_PU1

#define PWR_PUCRF_PU1 PWR_PUCRF_PU1_Msk

Pin PF1 Pull-Up set

◆ PWR_PUCRF_PU1_Msk

#define PWR_PUCRF_PU1_Msk (0x1UL << PWR_PUCRF_PU1_Pos)

0x00000002

◆ PWR_PUCRF_PU1_Pos

#define PWR_PUCRF_PU1_Pos (1U)

◆ PWR_PUCRF_PU2

#define PWR_PUCRF_PU2 PWR_PUCRF_PU2_Msk

Pin PF2 Pull-Up set

◆ PWR_PUCRF_PU2_Msk

#define PWR_PUCRF_PU2_Msk (0x1UL << PWR_PUCRF_PU2_Pos)

0x00000004

◆ PWR_PUCRF_PU2_Pos

#define PWR_PUCRF_PU2_Pos (2U)

◆ PWR_SCR_CSBF

#define PWR_SCR_CSBF PWR_SCR_CSBF_Msk

Clear Standby Flag

◆ PWR_SCR_CSBF_Msk

#define PWR_SCR_CSBF_Msk (0x1UL << PWR_SCR_CSBF_Pos)

0x00000100

◆ PWR_SCR_CSBF_Pos

#define PWR_SCR_CSBF_Pos (8U)

◆ PWR_SCR_CWUF

#define PWR_SCR_CWUF PWR_SCR_CWUF_Msk

Clear Wake-up Flags

◆ PWR_SCR_CWUF1

#define PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk

Clear Wake-up Flag 1

◆ PWR_SCR_CWUF1_Msk

#define PWR_SCR_CWUF1_Msk (0x1UL << PWR_SCR_CWUF1_Pos)

0x00000001

◆ PWR_SCR_CWUF1_Pos

#define PWR_SCR_CWUF1_Pos (0U)

◆ PWR_SCR_CWUF2

#define PWR_SCR_CWUF2 PWR_SCR_CWUF2_Msk

Clear Wake-up Flag 2

◆ PWR_SCR_CWUF2_Msk

#define PWR_SCR_CWUF2_Msk (0x1UL << PWR_SCR_CWUF2_Pos)

0x00000002

◆ PWR_SCR_CWUF2_Pos

#define PWR_SCR_CWUF2_Pos (1U)

◆ PWR_SCR_CWUF4

#define PWR_SCR_CWUF4 PWR_SCR_CWUF4_Msk

Clear Wake-up Flag 4

◆ PWR_SCR_CWUF4_Msk

#define PWR_SCR_CWUF4_Msk (0x1UL << PWR_SCR_CWUF4_Pos)

0x00000008

◆ PWR_SCR_CWUF4_Pos

#define PWR_SCR_CWUF4_Pos (3U)

◆ PWR_SCR_CWUF6

#define PWR_SCR_CWUF6 PWR_SCR_CWUF6_Msk

Clear Wake-up Flag 6

◆ PWR_SCR_CWUF6_Msk

#define PWR_SCR_CWUF6_Msk (0x1UL << PWR_SCR_CWUF6_Pos)

0x00000020

◆ PWR_SCR_CWUF6_Pos

#define PWR_SCR_CWUF6_Pos (5U)

◆ PWR_SCR_CWUF_Msk

#define PWR_SCR_CWUF_Msk (0x2BUL << PWR_SCR_CWUF_Pos)

0x0000002B

◆ PWR_SCR_CWUF_Pos

#define PWR_SCR_CWUF_Pos (0U)

◆ PWR_SR1_SBF

#define PWR_SR1_SBF PWR_SR1_SBF_Msk

Standby Flag

◆ PWR_SR1_SBF_Msk

#define PWR_SR1_SBF_Msk (0x1UL << PWR_SR1_SBF_Pos)

0x00000100

◆ PWR_SR1_SBF_Pos

#define PWR_SR1_SBF_Pos (8U)

◆ PWR_SR1_WUF

#define PWR_SR1_WUF PWR_SR1_WUF_Msk

Wakeup Flags

◆ PWR_SR1_WUF1

#define PWR_SR1_WUF1 PWR_SR1_WUF1_Msk

Wakeup Flag 1

◆ PWR_SR1_WUF1_Msk

#define PWR_SR1_WUF1_Msk (0x1UL << PWR_SR1_WUF1_Pos)

0x00000001

◆ PWR_SR1_WUF1_Pos

#define PWR_SR1_WUF1_Pos (0U)

◆ PWR_SR1_WUF2

#define PWR_SR1_WUF2 PWR_SR1_WUF2_Msk

Wakeup Flag 2

◆ PWR_SR1_WUF2_Msk

#define PWR_SR1_WUF2_Msk (0x1UL << PWR_SR1_WUF2_Pos)

0x00000002

◆ PWR_SR1_WUF2_Pos

#define PWR_SR1_WUF2_Pos (1U)

◆ PWR_SR1_WUF4

#define PWR_SR1_WUF4 PWR_SR1_WUF4_Msk

Wakeup Flag 4

◆ PWR_SR1_WUF4_Msk

#define PWR_SR1_WUF4_Msk (0x1UL << PWR_SR1_WUF4_Pos)

0x00000008

◆ PWR_SR1_WUF4_Pos

#define PWR_SR1_WUF4_Pos (3U)

◆ PWR_SR1_WUF6

#define PWR_SR1_WUF6 PWR_SR1_WUF6_Msk

Wakeup Flag 6

◆ PWR_SR1_WUF6_Msk

#define PWR_SR1_WUF6_Msk (0x1UL << PWR_SR1_WUF6_Pos)

0x00000020

◆ PWR_SR1_WUF6_Pos

#define PWR_SR1_WUF6_Pos (5U)

◆ PWR_SR1_WUF_Msk

#define PWR_SR1_WUF_Msk (0x2BUL << PWR_SR1_WUF_Pos)

0x0000002B

◆ PWR_SR1_WUF_Pos

#define PWR_SR1_WUF_Pos (0U)

◆ PWR_SR1_WUFI

#define PWR_SR1_WUFI PWR_SR1_WUFI_Msk

Wakeup Flag Internal

◆ PWR_SR1_WUFI_Msk

#define PWR_SR1_WUFI_Msk (0x1UL << PWR_SR1_WUFI_Pos)

0x00008000

◆ PWR_SR1_WUFI_Pos

#define PWR_SR1_WUFI_Pos (15U)

◆ PWR_SR2_FLASH_RDY

#define PWR_SR2_FLASH_RDY PWR_SR2_FLASH_RDY_Msk

Flash Ready

◆ PWR_SR2_FLASH_RDY_Msk

#define PWR_SR2_FLASH_RDY_Msk (0x1UL << PWR_SR2_FLASH_RDY_Pos)

0x00000080

◆ PWR_SR2_FLASH_RDY_Pos

#define PWR_SR2_FLASH_RDY_Pos (7U)

◆ PWR_SR2_REGLPF

#define PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk

Regulator Low Power flag

◆ PWR_SR2_REGLPF_Msk

#define PWR_SR2_REGLPF_Msk (0x1UL << PWR_SR2_REGLPF_Pos)

0x00000200

◆ PWR_SR2_REGLPF_Pos

#define PWR_SR2_REGLPF_Pos (9U)

◆ PWR_SR2_REGLPS

#define PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk

Regulator Low Power started

◆ PWR_SR2_REGLPS_Msk

#define PWR_SR2_REGLPS_Msk (0x1UL << PWR_SR2_REGLPS_Pos)

0x00000100

◆ PWR_SR2_REGLPS_Pos

#define PWR_SR2_REGLPS_Pos (8U)

◆ PWR_SR2_VOSF

#define PWR_SR2_VOSF PWR_SR2_VOSF_Msk

Voltage Scaling Flag

◆ PWR_SR2_VOSF_Msk

#define PWR_SR2_VOSF_Msk (0x1UL << PWR_SR2_VOSF_Pos)

0x00000400

◆ PWR_SR2_VOSF_Pos

#define PWR_SR2_VOSF_Pos (10U)

◆ RCC_AHBENR_CRCEN

#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk

◆ RCC_AHBENR_CRCEN_Msk

#define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos)

0x00001000

◆ RCC_AHBENR_CRCEN_Pos

#define RCC_AHBENR_CRCEN_Pos (12U)

◆ RCC_AHBENR_DMA1EN

#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk

◆ RCC_AHBENR_DMA1EN_Msk

#define RCC_AHBENR_DMA1EN_Msk (0x1UL << RCC_AHBENR_DMA1EN_Pos)

0x00000001

◆ RCC_AHBENR_DMA1EN_Pos

#define RCC_AHBENR_DMA1EN_Pos (0U)

◆ RCC_AHBENR_FLASHEN

#define RCC_AHBENR_FLASHEN RCC_AHBENR_FLASHEN_Msk

◆ RCC_AHBENR_FLASHEN_Msk

#define RCC_AHBENR_FLASHEN_Msk (0x1UL << RCC_AHBENR_FLASHEN_Pos)

0x00000100

◆ RCC_AHBENR_FLASHEN_Pos

#define RCC_AHBENR_FLASHEN_Pos (8U)

◆ RCC_AHBRSTR_CRCRST

#define RCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_Msk

◆ RCC_AHBRSTR_CRCRST_Msk

#define RCC_AHBRSTR_CRCRST_Msk (0x1UL << RCC_AHBRSTR_CRCRST_Pos)

0x00001000

◆ RCC_AHBRSTR_CRCRST_Pos

#define RCC_AHBRSTR_CRCRST_Pos (12U)

◆ RCC_AHBRSTR_DMA1RST

#define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMA1RST_Msk

◆ RCC_AHBRSTR_DMA1RST_Msk

#define RCC_AHBRSTR_DMA1RST_Msk (0x1UL << RCC_AHBRSTR_DMA1RST_Pos)

0x00000001

◆ RCC_AHBRSTR_DMA1RST_Pos

#define RCC_AHBRSTR_DMA1RST_Pos (0U)

◆ RCC_AHBRSTR_FLASHRST

#define RCC_AHBRSTR_FLASHRST RCC_AHBRSTR_FLASHRST_Msk

◆ RCC_AHBRSTR_FLASHRST_Msk

#define RCC_AHBRSTR_FLASHRST_Msk (0x1UL << RCC_AHBRSTR_FLASHRST_Pos)

0x00000100

◆ RCC_AHBRSTR_FLASHRST_Pos

#define RCC_AHBRSTR_FLASHRST_Pos (8U)

◆ RCC_AHBSMENR_CRCSMEN

#define RCC_AHBSMENR_CRCSMEN RCC_AHBSMENR_CRCSMEN_Msk

◆ RCC_AHBSMENR_CRCSMEN_Msk

#define RCC_AHBSMENR_CRCSMEN_Msk (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos)

0x00001000

◆ RCC_AHBSMENR_CRCSMEN_Pos

#define RCC_AHBSMENR_CRCSMEN_Pos (12U)

◆ RCC_AHBSMENR_DMA1SMEN

#define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMA1SMEN_Msk

◆ RCC_AHBSMENR_DMA1SMEN_Msk

#define RCC_AHBSMENR_DMA1SMEN_Msk (0x1UL << RCC_AHBSMENR_DMA1SMEN_Pos)

0x00000001

◆ RCC_AHBSMENR_DMA1SMEN_Pos

#define RCC_AHBSMENR_DMA1SMEN_Pos (0U)

◆ RCC_AHBSMENR_FLASHSMEN

#define RCC_AHBSMENR_FLASHSMEN RCC_AHBSMENR_FLASHSMEN_Msk

◆ RCC_AHBSMENR_FLASHSMEN_Msk

#define RCC_AHBSMENR_FLASHSMEN_Msk (0x1UL << RCC_AHBSMENR_FLASHSMEN_Pos)

0x00000100

◆ RCC_AHBSMENR_FLASHSMEN_Pos

#define RCC_AHBSMENR_FLASHSMEN_Pos (8U)

◆ RCC_AHBSMENR_SRAMSMEN

#define RCC_AHBSMENR_SRAMSMEN RCC_AHBSMENR_SRAMSMEN_Msk

◆ RCC_AHBSMENR_SRAMSMEN_Msk

#define RCC_AHBSMENR_SRAMSMEN_Msk (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos)

0x00000200

◆ RCC_AHBSMENR_SRAMSMEN_Pos

#define RCC_AHBSMENR_SRAMSMEN_Pos (9U)

◆ RCC_APBENR1_DBGEN

#define RCC_APBENR1_DBGEN RCC_APBENR1_DBGEN_Msk

◆ RCC_APBENR1_DBGEN_Msk

#define RCC_APBENR1_DBGEN_Msk (0x1UL << RCC_APBENR1_DBGEN_Pos)

0x08000000

◆ RCC_APBENR1_DBGEN_Pos

#define RCC_APBENR1_DBGEN_Pos (27U)

◆ RCC_APBENR1_I2C1EN

#define RCC_APBENR1_I2C1EN RCC_APBENR1_I2C1EN_Msk

◆ RCC_APBENR1_I2C1EN_Msk

#define RCC_APBENR1_I2C1EN_Msk (0x1UL << RCC_APBENR1_I2C1EN_Pos)

0x00200000

◆ RCC_APBENR1_I2C1EN_Pos

#define RCC_APBENR1_I2C1EN_Pos (21U)

◆ RCC_APBENR1_I2C2EN

#define RCC_APBENR1_I2C2EN RCC_APBENR1_I2C2EN_Msk

◆ RCC_APBENR1_I2C2EN_Msk

#define RCC_APBENR1_I2C2EN_Msk (0x1UL << RCC_APBENR1_I2C2EN_Pos)

0x00400000

◆ RCC_APBENR1_I2C2EN_Pos

#define RCC_APBENR1_I2C2EN_Pos (22U)

◆ RCC_APBENR1_PWREN

#define RCC_APBENR1_PWREN RCC_APBENR1_PWREN_Msk

◆ RCC_APBENR1_PWREN_Msk

#define RCC_APBENR1_PWREN_Msk (0x1UL << RCC_APBENR1_PWREN_Pos)

0x10000000

◆ RCC_APBENR1_PWREN_Pos

#define RCC_APBENR1_PWREN_Pos (28U)

◆ RCC_APBENR1_RTCAPBEN

#define RCC_APBENR1_RTCAPBEN RCC_APBENR1_RTCAPBEN_Msk

◆ RCC_APBENR1_RTCAPBEN_Msk

#define RCC_APBENR1_RTCAPBEN_Msk (0x1UL << RCC_APBENR1_RTCAPBEN_Pos)

0x00000400

◆ RCC_APBENR1_RTCAPBEN_Pos

#define RCC_APBENR1_RTCAPBEN_Pos (10U)

◆ RCC_APBENR1_SPI2EN

#define RCC_APBENR1_SPI2EN RCC_APBENR1_SPI2EN_Msk

◆ RCC_APBENR1_SPI2EN_Msk

#define RCC_APBENR1_SPI2EN_Msk (0x1UL << RCC_APBENR1_SPI2EN_Pos)

0x00004000

◆ RCC_APBENR1_SPI2EN_Pos

#define RCC_APBENR1_SPI2EN_Pos (14U)

◆ RCC_APBENR1_TIM3EN

#define RCC_APBENR1_TIM3EN RCC_APBENR1_TIM3EN_Msk

◆ RCC_APBENR1_TIM3EN_Msk

#define RCC_APBENR1_TIM3EN_Msk (0x1UL << RCC_APBENR1_TIM3EN_Pos)

0x00000002

◆ RCC_APBENR1_TIM3EN_Pos

#define RCC_APBENR1_TIM3EN_Pos (1U)

◆ RCC_APBENR1_USART2EN

#define RCC_APBENR1_USART2EN RCC_APBENR1_USART2EN_Msk

◆ RCC_APBENR1_USART2EN_Msk

#define RCC_APBENR1_USART2EN_Msk (0x1UL << RCC_APBENR1_USART2EN_Pos)

0x00020000

◆ RCC_APBENR1_USART2EN_Pos

#define RCC_APBENR1_USART2EN_Pos (17U)

◆ RCC_APBENR1_WWDGEN

#define RCC_APBENR1_WWDGEN RCC_APBENR1_WWDGEN_Msk

◆ RCC_APBENR1_WWDGEN_Msk

#define RCC_APBENR1_WWDGEN_Msk (0x1UL << RCC_APBENR1_WWDGEN_Pos)

0x00000800

◆ RCC_APBENR1_WWDGEN_Pos

#define RCC_APBENR1_WWDGEN_Pos (11U)

◆ RCC_APBENR2_ADCEN

#define RCC_APBENR2_ADCEN RCC_APBENR2_ADCEN_Msk

◆ RCC_APBENR2_ADCEN_Msk

#define RCC_APBENR2_ADCEN_Msk (0x1UL << RCC_APBENR2_ADCEN_Pos)

0x00100000

◆ RCC_APBENR2_ADCEN_Pos

#define RCC_APBENR2_ADCEN_Pos (20U)

◆ RCC_APBENR2_SPI1EN

#define RCC_APBENR2_SPI1EN RCC_APBENR2_SPI1EN_Msk

◆ RCC_APBENR2_SPI1EN_Msk

#define RCC_APBENR2_SPI1EN_Msk (0x1UL << RCC_APBENR2_SPI1EN_Pos)

0x00001000

◆ RCC_APBENR2_SPI1EN_Pos

#define RCC_APBENR2_SPI1EN_Pos (12U)

◆ RCC_APBENR2_SYSCFGEN

#define RCC_APBENR2_SYSCFGEN RCC_APBENR2_SYSCFGEN_Msk

◆ RCC_APBENR2_SYSCFGEN_Msk

#define RCC_APBENR2_SYSCFGEN_Msk (0x1UL << RCC_APBENR2_SYSCFGEN_Pos)

0x00000001

◆ RCC_APBENR2_SYSCFGEN_Pos

#define RCC_APBENR2_SYSCFGEN_Pos (0U)

◆ RCC_APBENR2_TIM14EN

#define RCC_APBENR2_TIM14EN RCC_APBENR2_TIM14EN_Msk

◆ RCC_APBENR2_TIM14EN_Msk

#define RCC_APBENR2_TIM14EN_Msk (0x1UL << RCC_APBENR2_TIM14EN_Pos)

0x00008000

◆ RCC_APBENR2_TIM14EN_Pos

#define RCC_APBENR2_TIM14EN_Pos (15U)

◆ RCC_APBENR2_TIM16EN

#define RCC_APBENR2_TIM16EN RCC_APBENR2_TIM16EN_Msk

◆ RCC_APBENR2_TIM16EN_Msk

#define RCC_APBENR2_TIM16EN_Msk (0x1UL << RCC_APBENR2_TIM16EN_Pos)

0x00020000

◆ RCC_APBENR2_TIM16EN_Pos

#define RCC_APBENR2_TIM16EN_Pos (17U)

◆ RCC_APBENR2_TIM17EN

#define RCC_APBENR2_TIM17EN RCC_APBENR2_TIM17EN_Msk

◆ RCC_APBENR2_TIM17EN_Msk

#define RCC_APBENR2_TIM17EN_Msk (0x1UL << RCC_APBENR2_TIM17EN_Pos)

0x00040000

◆ RCC_APBENR2_TIM17EN_Pos

#define RCC_APBENR2_TIM17EN_Pos (18U)

◆ RCC_APBENR2_TIM1EN

#define RCC_APBENR2_TIM1EN RCC_APBENR2_TIM1EN_Msk

◆ RCC_APBENR2_TIM1EN_Msk

#define RCC_APBENR2_TIM1EN_Msk (0x1UL << RCC_APBENR2_TIM1EN_Pos)

0x00000800

◆ RCC_APBENR2_TIM1EN_Pos

#define RCC_APBENR2_TIM1EN_Pos (11U)

◆ RCC_APBENR2_USART1EN

#define RCC_APBENR2_USART1EN RCC_APBENR2_USART1EN_Msk

◆ RCC_APBENR2_USART1EN_Msk

#define RCC_APBENR2_USART1EN_Msk (0x1UL << RCC_APBENR2_USART1EN_Pos)

0x00004000

◆ RCC_APBENR2_USART1EN_Pos

#define RCC_APBENR2_USART1EN_Pos (14U)

◆ RCC_APBRSTR1_DBGRST

#define RCC_APBRSTR1_DBGRST RCC_APBRSTR1_DBGRST_Msk

◆ RCC_APBRSTR1_DBGRST_Msk

#define RCC_APBRSTR1_DBGRST_Msk (0x1UL << RCC_APBRSTR1_DBGRST_Pos)

0x08000000

◆ RCC_APBRSTR1_DBGRST_Pos

#define RCC_APBRSTR1_DBGRST_Pos (27U)

◆ RCC_APBRSTR1_I2C1RST

#define RCC_APBRSTR1_I2C1RST RCC_APBRSTR1_I2C1RST_Msk

◆ RCC_APBRSTR1_I2C1RST_Msk

#define RCC_APBRSTR1_I2C1RST_Msk (0x1UL << RCC_APBRSTR1_I2C1RST_Pos)

0x00200000

◆ RCC_APBRSTR1_I2C1RST_Pos

#define RCC_APBRSTR1_I2C1RST_Pos (21U)

◆ RCC_APBRSTR1_I2C2RST

#define RCC_APBRSTR1_I2C2RST RCC_APBRSTR1_I2C2RST_Msk

◆ RCC_APBRSTR1_I2C2RST_Msk

#define RCC_APBRSTR1_I2C2RST_Msk (0x1UL << RCC_APBRSTR1_I2C2RST_Pos)

0x00400000

◆ RCC_APBRSTR1_I2C2RST_Pos

#define RCC_APBRSTR1_I2C2RST_Pos (22U)

◆ RCC_APBRSTR1_PWRRST

#define RCC_APBRSTR1_PWRRST RCC_APBRSTR1_PWRRST_Msk

◆ RCC_APBRSTR1_PWRRST_Msk

#define RCC_APBRSTR1_PWRRST_Msk (0x1UL << RCC_APBRSTR1_PWRRST_Pos)

0x10000000

◆ RCC_APBRSTR1_PWRRST_Pos

#define RCC_APBRSTR1_PWRRST_Pos (28U)

◆ RCC_APBRSTR1_SPI2RST

#define RCC_APBRSTR1_SPI2RST RCC_APBRSTR1_SPI2RST_Msk

◆ RCC_APBRSTR1_SPI2RST_Msk

#define RCC_APBRSTR1_SPI2RST_Msk (0x1UL << RCC_APBRSTR1_SPI2RST_Pos)

0x00004000

◆ RCC_APBRSTR1_SPI2RST_Pos

#define RCC_APBRSTR1_SPI2RST_Pos (14U)

◆ RCC_APBRSTR1_TIM3RST

#define RCC_APBRSTR1_TIM3RST RCC_APBRSTR1_TIM3RST_Msk

◆ RCC_APBRSTR1_TIM3RST_Msk

#define RCC_APBRSTR1_TIM3RST_Msk (0x1UL << RCC_APBRSTR1_TIM3RST_Pos)

0x00000002

◆ RCC_APBRSTR1_TIM3RST_Pos

#define RCC_APBRSTR1_TIM3RST_Pos (1U)

◆ RCC_APBRSTR1_USART2RST

#define RCC_APBRSTR1_USART2RST RCC_APBRSTR1_USART2RST_Msk

◆ RCC_APBRSTR1_USART2RST_Msk

#define RCC_APBRSTR1_USART2RST_Msk (0x1UL << RCC_APBRSTR1_USART2RST_Pos)

0x00020000

◆ RCC_APBRSTR1_USART2RST_Pos

#define RCC_APBRSTR1_USART2RST_Pos (17U)

◆ RCC_APBRSTR2_ADCRST

#define RCC_APBRSTR2_ADCRST RCC_APBRSTR2_ADCRST_Msk

◆ RCC_APBRSTR2_ADCRST_Msk

#define RCC_APBRSTR2_ADCRST_Msk (0x1UL << RCC_APBRSTR2_ADCRST_Pos)

0x00100000

◆ RCC_APBRSTR2_ADCRST_Pos

#define RCC_APBRSTR2_ADCRST_Pos (20U)

◆ RCC_APBRSTR2_SPI1RST

#define RCC_APBRSTR2_SPI1RST RCC_APBRSTR2_SPI1RST_Msk

◆ RCC_APBRSTR2_SPI1RST_Msk

#define RCC_APBRSTR2_SPI1RST_Msk (0x1UL << RCC_APBRSTR2_SPI1RST_Pos)

0x00001000

◆ RCC_APBRSTR2_SPI1RST_Pos

#define RCC_APBRSTR2_SPI1RST_Pos (12U)

◆ RCC_APBRSTR2_SYSCFGRST

#define RCC_APBRSTR2_SYSCFGRST RCC_APBRSTR2_SYSCFGRST_Msk

◆ RCC_APBRSTR2_SYSCFGRST_Msk

#define RCC_APBRSTR2_SYSCFGRST_Msk (0x1UL << RCC_APBRSTR2_SYSCFGRST_Pos)

0x00000001

◆ RCC_APBRSTR2_SYSCFGRST_Pos

#define RCC_APBRSTR2_SYSCFGRST_Pos (0U)

◆ RCC_APBRSTR2_TIM14RST

#define RCC_APBRSTR2_TIM14RST RCC_APBRSTR2_TIM14RST_Msk

◆ RCC_APBRSTR2_TIM14RST_Msk

#define RCC_APBRSTR2_TIM14RST_Msk (0x1UL << RCC_APBRSTR2_TIM14RST_Pos)

0x00008000

◆ RCC_APBRSTR2_TIM14RST_Pos

#define RCC_APBRSTR2_TIM14RST_Pos (15U)

◆ RCC_APBRSTR2_TIM16RST

#define RCC_APBRSTR2_TIM16RST RCC_APBRSTR2_TIM16RST_Msk

◆ RCC_APBRSTR2_TIM16RST_Msk

#define RCC_APBRSTR2_TIM16RST_Msk (0x1UL << RCC_APBRSTR2_TIM16RST_Pos)

0x00020000

◆ RCC_APBRSTR2_TIM16RST_Pos

#define RCC_APBRSTR2_TIM16RST_Pos (17U)

◆ RCC_APBRSTR2_TIM17RST

#define RCC_APBRSTR2_TIM17RST RCC_APBRSTR2_TIM17RST_Msk

◆ RCC_APBRSTR2_TIM17RST_Msk

#define RCC_APBRSTR2_TIM17RST_Msk (0x1UL << RCC_APBRSTR2_TIM17RST_Pos)

0x00040000

◆ RCC_APBRSTR2_TIM17RST_Pos

#define RCC_APBRSTR2_TIM17RST_Pos (18U)

◆ RCC_APBRSTR2_TIM1RST

#define RCC_APBRSTR2_TIM1RST RCC_APBRSTR2_TIM1RST_Msk

◆ RCC_APBRSTR2_TIM1RST_Msk

#define RCC_APBRSTR2_TIM1RST_Msk (0x1UL << RCC_APBRSTR2_TIM1RST_Pos)

0x00000800

◆ RCC_APBRSTR2_TIM1RST_Pos

#define RCC_APBRSTR2_TIM1RST_Pos (11U)

◆ RCC_APBRSTR2_USART1RST

#define RCC_APBRSTR2_USART1RST RCC_APBRSTR2_USART1RST_Msk

◆ RCC_APBRSTR2_USART1RST_Msk

#define RCC_APBRSTR2_USART1RST_Msk (0x1UL << RCC_APBRSTR2_USART1RST_Pos)

0x00004000

◆ RCC_APBRSTR2_USART1RST_Pos

#define RCC_APBRSTR2_USART1RST_Pos (14U)

◆ RCC_APBSMENR1_DBGSMEN

#define RCC_APBSMENR1_DBGSMEN RCC_APBSMENR1_DBGSMEN_Msk

◆ RCC_APBSMENR1_DBGSMEN_Msk

#define RCC_APBSMENR1_DBGSMEN_Msk (0x1UL << RCC_APBSMENR1_DBGSMEN_Pos)

0x08000000

◆ RCC_APBSMENR1_DBGSMEN_Pos

#define RCC_APBSMENR1_DBGSMEN_Pos (27U)

◆ RCC_APBSMENR1_I2C1SMEN

#define RCC_APBSMENR1_I2C1SMEN RCC_APBSMENR1_I2C1SMEN_Msk

◆ RCC_APBSMENR1_I2C1SMEN_Msk

#define RCC_APBSMENR1_I2C1SMEN_Msk (0x1UL << RCC_APBSMENR1_I2C1SMEN_Pos)

0x00200000

◆ RCC_APBSMENR1_I2C1SMEN_Pos

#define RCC_APBSMENR1_I2C1SMEN_Pos (21U)

◆ RCC_APBSMENR1_I2C2SMEN

#define RCC_APBSMENR1_I2C2SMEN RCC_APBSMENR1_I2C2SMEN_Msk

◆ RCC_APBSMENR1_I2C2SMEN_Msk

#define RCC_APBSMENR1_I2C2SMEN_Msk (0x1UL << RCC_APBSMENR1_I2C2SMEN_Pos)

0x00400000

◆ RCC_APBSMENR1_I2C2SMEN_Pos

#define RCC_APBSMENR1_I2C2SMEN_Pos (22U)

◆ RCC_APBSMENR1_PWRSMEN

#define RCC_APBSMENR1_PWRSMEN RCC_APBSMENR1_PWRSMEN_Msk

◆ RCC_APBSMENR1_PWRSMEN_Msk

#define RCC_APBSMENR1_PWRSMEN_Msk (0x1UL << RCC_APBSMENR1_PWRSMEN_Pos)

0x10000000

◆ RCC_APBSMENR1_PWRSMEN_Pos

#define RCC_APBSMENR1_PWRSMEN_Pos (28U)

◆ RCC_APBSMENR1_RTCAPBSMEN

#define RCC_APBSMENR1_RTCAPBSMEN RCC_APBSMENR1_RTCAPBSMEN_Msk

◆ RCC_APBSMENR1_RTCAPBSMEN_Msk

#define RCC_APBSMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APBSMENR1_RTCAPBSMEN_Pos)

0x00000400

◆ RCC_APBSMENR1_RTCAPBSMEN_Pos

#define RCC_APBSMENR1_RTCAPBSMEN_Pos (10U)

◆ RCC_APBSMENR1_SPI2SMEN

#define RCC_APBSMENR1_SPI2SMEN RCC_APBSMENR1_SPI2SMEN_Msk

◆ RCC_APBSMENR1_SPI2SMEN_Msk

#define RCC_APBSMENR1_SPI2SMEN_Msk (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos)

0x00004000

◆ RCC_APBSMENR1_SPI2SMEN_Pos

#define RCC_APBSMENR1_SPI2SMEN_Pos (14U)

◆ RCC_APBSMENR1_TIM3SMEN

#define RCC_APBSMENR1_TIM3SMEN RCC_APBSMENR1_TIM3SMEN_Msk

◆ RCC_APBSMENR1_TIM3SMEN_Msk

#define RCC_APBSMENR1_TIM3SMEN_Msk (0x1UL << RCC_APBSMENR1_TIM3SMEN_Pos)

0x00000002

◆ RCC_APBSMENR1_TIM3SMEN_Pos

#define RCC_APBSMENR1_TIM3SMEN_Pos (1U)

◆ RCC_APBSMENR1_USART2SMEN

#define RCC_APBSMENR1_USART2SMEN RCC_APBSMENR1_USART2SMEN_Msk

◆ RCC_APBSMENR1_USART2SMEN_Msk

#define RCC_APBSMENR1_USART2SMEN_Msk (0x1UL << RCC_APBSMENR1_USART2SMEN_Pos)

0x00020000

◆ RCC_APBSMENR1_USART2SMEN_Pos

#define RCC_APBSMENR1_USART2SMEN_Pos (17U)

◆ RCC_APBSMENR1_WWDGSMEN

#define RCC_APBSMENR1_WWDGSMEN RCC_APBSMENR1_WWDGSMEN_Msk

◆ RCC_APBSMENR1_WWDGSMEN_Msk

#define RCC_APBSMENR1_WWDGSMEN_Msk (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos)

0x00000800

◆ RCC_APBSMENR1_WWDGSMEN_Pos

#define RCC_APBSMENR1_WWDGSMEN_Pos (11U)

◆ RCC_APBSMENR2_ADCSMEN

#define RCC_APBSMENR2_ADCSMEN RCC_APBSMENR2_ADCSMEN_Msk

◆ RCC_APBSMENR2_ADCSMEN_Msk

#define RCC_APBSMENR2_ADCSMEN_Msk (0x1UL << RCC_APBSMENR2_ADCSMEN_Pos)

0x00100000

◆ RCC_APBSMENR2_ADCSMEN_Pos

#define RCC_APBSMENR2_ADCSMEN_Pos (20U)

◆ RCC_APBSMENR2_SPI1SMEN

#define RCC_APBSMENR2_SPI1SMEN RCC_APBSMENR2_SPI1SMEN_Msk

◆ RCC_APBSMENR2_SPI1SMEN_Msk

#define RCC_APBSMENR2_SPI1SMEN_Msk (0x1UL << RCC_APBSMENR2_SPI1SMEN_Pos)

0x00001000

◆ RCC_APBSMENR2_SPI1SMEN_Pos

#define RCC_APBSMENR2_SPI1SMEN_Pos (12U)

◆ RCC_APBSMENR2_SYSCFGSMEN

#define RCC_APBSMENR2_SYSCFGSMEN RCC_APBSMENR2_SYSCFGSMEN_Msk

◆ RCC_APBSMENR2_SYSCFGSMEN_Msk

#define RCC_APBSMENR2_SYSCFGSMEN_Msk (0x1UL << RCC_APBSMENR2_SYSCFGSMEN_Pos)

0x00000001

◆ RCC_APBSMENR2_SYSCFGSMEN_Pos

#define RCC_APBSMENR2_SYSCFGSMEN_Pos (0U)

◆ RCC_APBSMENR2_TIM14SMEN

#define RCC_APBSMENR2_TIM14SMEN RCC_APBSMENR2_TIM14SMEN_Msk

◆ RCC_APBSMENR2_TIM14SMEN_Msk

#define RCC_APBSMENR2_TIM14SMEN_Msk (0x1UL << RCC_APBSMENR2_TIM14SMEN_Pos)

0x00008000

◆ RCC_APBSMENR2_TIM14SMEN_Pos

#define RCC_APBSMENR2_TIM14SMEN_Pos (15U)

◆ RCC_APBSMENR2_TIM16SMEN

#define RCC_APBSMENR2_TIM16SMEN RCC_APBSMENR2_TIM16SMEN_Msk

◆ RCC_APBSMENR2_TIM16SMEN_Msk

#define RCC_APBSMENR2_TIM16SMEN_Msk (0x1UL << RCC_APBSMENR2_TIM16SMEN_Pos)

0x00020000

◆ RCC_APBSMENR2_TIM16SMEN_Pos

#define RCC_APBSMENR2_TIM16SMEN_Pos (17U)

◆ RCC_APBSMENR2_TIM17SMEN

#define RCC_APBSMENR2_TIM17SMEN RCC_APBSMENR2_TIM17SMEN_Msk

◆ RCC_APBSMENR2_TIM17SMEN_Msk

#define RCC_APBSMENR2_TIM17SMEN_Msk (0x1UL << RCC_APBSMENR2_TIM17SMEN_Pos)

0x00040000

◆ RCC_APBSMENR2_TIM17SMEN_Pos

#define RCC_APBSMENR2_TIM17SMEN_Pos (18U)

◆ RCC_APBSMENR2_TIM1SMEN

#define RCC_APBSMENR2_TIM1SMEN RCC_APBSMENR2_TIM1SMEN_Msk

◆ RCC_APBSMENR2_TIM1SMEN_Msk

#define RCC_APBSMENR2_TIM1SMEN_Msk (0x1UL << RCC_APBSMENR2_TIM1SMEN_Pos)

0x00000800

◆ RCC_APBSMENR2_TIM1SMEN_Pos

#define RCC_APBSMENR2_TIM1SMEN_Pos (11U)

◆ RCC_APBSMENR2_USART1SMEN

#define RCC_APBSMENR2_USART1SMEN RCC_APBSMENR2_USART1SMEN_Msk

◆ RCC_APBSMENR2_USART1SMEN_Msk

#define RCC_APBSMENR2_USART1SMEN_Msk (0x1UL << RCC_APBSMENR2_USART1SMEN_Pos)

0x00004000

◆ RCC_APBSMENR2_USART1SMEN_Pos

#define RCC_APBSMENR2_USART1SMEN_Pos (14U)

◆ RCC_BDCR_BDRST

#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk

◆ RCC_BDCR_BDRST_Msk

#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos)

0x00010000

◆ RCC_BDCR_BDRST_Pos

#define RCC_BDCR_BDRST_Pos (16U)

◆ RCC_BDCR_LSCOEN

#define RCC_BDCR_LSCOEN RCC_BDCR_LSCOEN_Msk

◆ RCC_BDCR_LSCOEN_Msk

#define RCC_BDCR_LSCOEN_Msk (0x1UL << RCC_BDCR_LSCOEN_Pos)

0x01000000

◆ RCC_BDCR_LSCOEN_Pos

#define RCC_BDCR_LSCOEN_Pos (24U)

◆ RCC_BDCR_LSCOSEL

#define RCC_BDCR_LSCOSEL RCC_BDCR_LSCOSEL_Msk

◆ RCC_BDCR_LSCOSEL_Msk

#define RCC_BDCR_LSCOSEL_Msk (0x1UL << RCC_BDCR_LSCOSEL_Pos)

0x02000000

◆ RCC_BDCR_LSCOSEL_Pos

#define RCC_BDCR_LSCOSEL_Pos (25U)

◆ RCC_BDCR_LSEBYP

#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk

◆ RCC_BDCR_LSEBYP_Msk

#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos)

0x00000004

◆ RCC_BDCR_LSEBYP_Pos

#define RCC_BDCR_LSEBYP_Pos (2U)

◆ RCC_BDCR_LSECSSD

#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk

◆ RCC_BDCR_LSECSSD_Msk

#define RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos)

0x00000040

◆ RCC_BDCR_LSECSSD_Pos

#define RCC_BDCR_LSECSSD_Pos (6U)

◆ RCC_BDCR_LSECSSON

#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk

◆ RCC_BDCR_LSECSSON_Msk

#define RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos)

0x00000020

◆ RCC_BDCR_LSECSSON_Pos

#define RCC_BDCR_LSECSSON_Pos (5U)

◆ RCC_BDCR_LSEDRV

#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk

◆ RCC_BDCR_LSEDRV_0

#define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos)

0x00000008

◆ RCC_BDCR_LSEDRV_1

#define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos)

0x00000010

◆ RCC_BDCR_LSEDRV_Msk

#define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos)

0x00000018

◆ RCC_BDCR_LSEDRV_Pos

#define RCC_BDCR_LSEDRV_Pos (3U)

◆ RCC_BDCR_LSEON

#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk

◆ RCC_BDCR_LSEON_Msk

#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos)

0x00000001

◆ RCC_BDCR_LSEON_Pos

#define RCC_BDCR_LSEON_Pos (0U)

◆ RCC_BDCR_LSERDY

#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk

◆ RCC_BDCR_LSERDY_Msk

#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos)

0x00000002

◆ RCC_BDCR_LSERDY_Pos

#define RCC_BDCR_LSERDY_Pos (1U)

◆ RCC_BDCR_RTCEN

#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk

◆ RCC_BDCR_RTCEN_Msk

#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos)

0x00008000

◆ RCC_BDCR_RTCEN_Pos

#define RCC_BDCR_RTCEN_Pos (15U)

◆ RCC_BDCR_RTCSEL

#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk

◆ RCC_BDCR_RTCSEL_0

#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos)

0x00000100

◆ RCC_BDCR_RTCSEL_1

#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos)

0x00000200

◆ RCC_BDCR_RTCSEL_Msk

#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos)

0x00000300

◆ RCC_BDCR_RTCSEL_Pos

#define RCC_BDCR_RTCSEL_Pos (8U)

◆ RCC_CCIPR_ADCSEL

#define RCC_CCIPR_ADCSEL RCC_CCIPR_ADCSEL_Msk

◆ RCC_CCIPR_ADCSEL_0

#define RCC_CCIPR_ADCSEL_0 (0x1UL << RCC_CCIPR_ADCSEL_Pos)

0x40000000

◆ RCC_CCIPR_ADCSEL_1

#define RCC_CCIPR_ADCSEL_1 (0x2UL << RCC_CCIPR_ADCSEL_Pos)

0x80000000

◆ RCC_CCIPR_ADCSEL_Msk

#define RCC_CCIPR_ADCSEL_Msk (0x3UL << RCC_CCIPR_ADCSEL_Pos)

0xC0000000

◆ RCC_CCIPR_ADCSEL_Pos

#define RCC_CCIPR_ADCSEL_Pos (30U)

◆ RCC_CCIPR_I2C1SEL

#define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk

◆ RCC_CCIPR_I2C1SEL_0

#define RCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos)

0x00001000

◆ RCC_CCIPR_I2C1SEL_1

#define RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos)

0x00002000

◆ RCC_CCIPR_I2C1SEL_Msk

#define RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos)

0x00003000

◆ RCC_CCIPR_I2C1SEL_Pos

#define RCC_CCIPR_I2C1SEL_Pos (12U)

◆ RCC_CCIPR_I2S1SEL

#define RCC_CCIPR_I2S1SEL RCC_CCIPR_I2S1SEL_Msk

◆ RCC_CCIPR_I2S1SEL_0

#define RCC_CCIPR_I2S1SEL_0 (0x1UL << RCC_CCIPR_I2S1SEL_Pos)

0x00004000

◆ RCC_CCIPR_I2S1SEL_1

#define RCC_CCIPR_I2S1SEL_1 (0x2UL << RCC_CCIPR_I2S1SEL_Pos)

0x00008000

◆ RCC_CCIPR_I2S1SEL_Msk

#define RCC_CCIPR_I2S1SEL_Msk (0x3UL << RCC_CCIPR_I2S1SEL_Pos)

0x0000C000

◆ RCC_CCIPR_I2S1SEL_Pos

#define RCC_CCIPR_I2S1SEL_Pos (14U)

◆ RCC_CCIPR_USART1SEL

#define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk

◆ RCC_CCIPR_USART1SEL_0

#define RCC_CCIPR_USART1SEL_0 (0x1UL << RCC_CCIPR_USART1SEL_Pos)

0x00000001

◆ RCC_CCIPR_USART1SEL_1

#define RCC_CCIPR_USART1SEL_1 (0x2UL << RCC_CCIPR_USART1SEL_Pos)

0x00000002

◆ RCC_CCIPR_USART1SEL_Msk

#define RCC_CCIPR_USART1SEL_Msk (0x3UL << RCC_CCIPR_USART1SEL_Pos)

0x00000003

◆ RCC_CCIPR_USART1SEL_Pos

#define RCC_CCIPR_USART1SEL_Pos (0U)

◆ RCC_CFGR_HPRE

#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk

HPRE[3:0] bits (AHB prescaler)

◆ RCC_CFGR_HPRE_0

#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos)

0x00000100

◆ RCC_CFGR_HPRE_1

#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos)

0x00000200

◆ RCC_CFGR_HPRE_2

#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos)

0x00000400

◆ RCC_CFGR_HPRE_3

#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos)

0x00000800 PPRE configuration

◆ RCC_CFGR_HPRE_Msk

#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos)

0x00000F00

◆ RCC_CFGR_HPRE_Pos

#define RCC_CFGR_HPRE_Pos (8U)

◆ RCC_CFGR_MCOPRE

#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk

MCO prescaler [2:0]

◆ RCC_CFGR_MCOPRE_0

#define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos)

0x10000000

◆ RCC_CFGR_MCOPRE_1

#define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos)

0x20000000

◆ RCC_CFGR_MCOPRE_2

#define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos)

0x40000000

◆ RCC_CFGR_MCOPRE_Msk

#define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos)

0x70000000

◆ RCC_CFGR_MCOPRE_Pos

#define RCC_CFGR_MCOPRE_Pos (28U)

◆ RCC_CFGR_MCOSEL

#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk

MCOSEL [2:0] bits (Clock output selection)

◆ RCC_CFGR_MCOSEL_0

#define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos)

0x01000000

◆ RCC_CFGR_MCOSEL_1

#define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos)

0x02000000

◆ RCC_CFGR_MCOSEL_2

#define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos)

0x04000000 MCO Prescaler configuration

◆ RCC_CFGR_MCOSEL_Msk

#define RCC_CFGR_MCOSEL_Msk (0x7UL << RCC_CFGR_MCOSEL_Pos)

0x07000000

◆ RCC_CFGR_MCOSEL_Pos

#define RCC_CFGR_MCOSEL_Pos (24U)

◆ RCC_CFGR_PPRE

#define RCC_CFGR_PPRE RCC_CFGR_PPRE_Msk

PRE1[2:0] bits (APB prescaler)

◆ RCC_CFGR_PPRE_0

#define RCC_CFGR_PPRE_0 (0x1UL << RCC_CFGR_PPRE_Pos)

0x00001000

◆ RCC_CFGR_PPRE_1

#define RCC_CFGR_PPRE_1 (0x2UL << RCC_CFGR_PPRE_Pos)

0x00002000

◆ RCC_CFGR_PPRE_2

#define RCC_CFGR_PPRE_2 (0x4UL << RCC_CFGR_PPRE_Pos)

0x00004000 MCOSEL configuration

◆ RCC_CFGR_PPRE_Msk

#define RCC_CFGR_PPRE_Msk (0x7UL << RCC_CFGR_PPRE_Pos)

0x00007000

◆ RCC_CFGR_PPRE_Pos

#define RCC_CFGR_PPRE_Pos (12U)

◆ RCC_CFGR_SW

#define RCC_CFGR_SW RCC_CFGR_SW_Msk

SW[2:0] bits (System clock Switch)

◆ RCC_CFGR_SW_0

#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)

0x00000001

◆ RCC_CFGR_SW_1

#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)

0x00000002

◆ RCC_CFGR_SW_2

#define RCC_CFGR_SW_2 (0x4UL << RCC_CFGR_SW_Pos)

0x00000004 SWS configuration

◆ RCC_CFGR_SW_Msk

#define RCC_CFGR_SW_Msk (0x7UL << RCC_CFGR_SW_Pos)

0x00000007

◆ RCC_CFGR_SW_Pos

#define RCC_CFGR_SW_Pos (0U)

< SW configuration

◆ RCC_CFGR_SWS

#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk

SWS[2:0] bits (System Clock Switch Status)

◆ RCC_CFGR_SWS_0

#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)

0x00000008

◆ RCC_CFGR_SWS_1

#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)

0x00000010

◆ RCC_CFGR_SWS_2

#define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos)

0x00000020 HPRE configuration

◆ RCC_CFGR_SWS_Msk

#define RCC_CFGR_SWS_Msk (0x7UL << RCC_CFGR_SWS_Pos)

0x00000038

◆ RCC_CFGR_SWS_Pos

#define RCC_CFGR_SWS_Pos (3U)

◆ RCC_CICR_CSSC

#define RCC_CICR_CSSC RCC_CICR_CSSC_Msk

◆ RCC_CICR_CSSC_Msk

#define RCC_CICR_CSSC_Msk (0x1UL << RCC_CICR_CSSC_Pos)

0x00000100

◆ RCC_CICR_CSSC_Pos

#define RCC_CICR_CSSC_Pos (8U)

◆ RCC_CICR_HSERDYC

#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk

◆ RCC_CICR_HSERDYC_Msk

#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos)

0x00000010

◆ RCC_CICR_HSERDYC_Pos

#define RCC_CICR_HSERDYC_Pos (4U)

◆ RCC_CICR_HSIRDYC

#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk

◆ RCC_CICR_HSIRDYC_Msk

#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos)

0x00000008

◆ RCC_CICR_HSIRDYC_Pos

#define RCC_CICR_HSIRDYC_Pos (3U)

◆ RCC_CICR_LSECSSC

#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk

◆ RCC_CICR_LSECSSC_Msk

#define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos)

0x00000200

◆ RCC_CICR_LSECSSC_Pos

#define RCC_CICR_LSECSSC_Pos (9U)

◆ RCC_CICR_LSERDYC

#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk

◆ RCC_CICR_LSERDYC_Msk

#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos)

0x00000002

◆ RCC_CICR_LSERDYC_Pos

#define RCC_CICR_LSERDYC_Pos (1U)

◆ RCC_CICR_LSIRDYC

#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk

◆ RCC_CICR_LSIRDYC_Msk

#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos)

0x00000001

◆ RCC_CICR_LSIRDYC_Pos

#define RCC_CICR_LSIRDYC_Pos (0U)

◆ RCC_CICR_PLLRDYC

#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk

◆ RCC_CICR_PLLRDYC_Msk

#define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos)

0x00000020

◆ RCC_CICR_PLLRDYC_Pos

#define RCC_CICR_PLLRDYC_Pos (5U)

◆ RCC_CIER_HSERDYIE

#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk

◆ RCC_CIER_HSERDYIE_Msk

#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos)

0x00000010

◆ RCC_CIER_HSERDYIE_Pos

#define RCC_CIER_HSERDYIE_Pos (4U)

◆ RCC_CIER_HSIRDYIE

#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk

◆ RCC_CIER_HSIRDYIE_Msk

#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos)

0x00000008

◆ RCC_CIER_HSIRDYIE_Pos

#define RCC_CIER_HSIRDYIE_Pos (3U)

◆ RCC_CIER_LSERDYIE

#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk

◆ RCC_CIER_LSERDYIE_Msk

#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos)

0x00000002

◆ RCC_CIER_LSERDYIE_Pos

#define RCC_CIER_LSERDYIE_Pos (1U)

◆ RCC_CIER_LSIRDYIE

#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk

◆ RCC_CIER_LSIRDYIE_Msk

#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos)

0x00000001

◆ RCC_CIER_LSIRDYIE_Pos

#define RCC_CIER_LSIRDYIE_Pos (0U)

◆ RCC_CIER_PLLRDYIE

#define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk

◆ RCC_CIER_PLLRDYIE_Msk

#define RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos)

0x00000020

◆ RCC_CIER_PLLRDYIE_Pos

#define RCC_CIER_PLLRDYIE_Pos (5U)

◆ RCC_CIFR_CSSF

#define RCC_CIFR_CSSF RCC_CIFR_CSSF_Msk

◆ RCC_CIFR_CSSF_Msk

#define RCC_CIFR_CSSF_Msk (0x1UL << RCC_CIFR_CSSF_Pos)

0x00000100

◆ RCC_CIFR_CSSF_Pos

#define RCC_CIFR_CSSF_Pos (8U)

◆ RCC_CIFR_HSERDYF

#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk

◆ RCC_CIFR_HSERDYF_Msk

#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos)

0x00000010

◆ RCC_CIFR_HSERDYF_Pos

#define RCC_CIFR_HSERDYF_Pos (4U)

◆ RCC_CIFR_HSIRDYF

#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk

◆ RCC_CIFR_HSIRDYF_Msk

#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos)

0x00000008

◆ RCC_CIFR_HSIRDYF_Pos

#define RCC_CIFR_HSIRDYF_Pos (3U)

◆ RCC_CIFR_LSECSSF

#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk

◆ RCC_CIFR_LSECSSF_Msk

#define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos)

0x00000200

◆ RCC_CIFR_LSECSSF_Pos

#define RCC_CIFR_LSECSSF_Pos (9U)

◆ RCC_CIFR_LSERDYF

#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk

◆ RCC_CIFR_LSERDYF_Msk

#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos)

0x00000002

◆ RCC_CIFR_LSERDYF_Pos

#define RCC_CIFR_LSERDYF_Pos (1U)

◆ RCC_CIFR_LSIRDYF

#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk

◆ RCC_CIFR_LSIRDYF_Msk

#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos)

0x00000001

◆ RCC_CIFR_LSIRDYF_Pos

#define RCC_CIFR_LSIRDYF_Pos (0U)

◆ RCC_CIFR_PLLRDYF

#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk

◆ RCC_CIFR_PLLRDYF_Msk

#define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos)

0x00000020

◆ RCC_CIFR_PLLRDYF_Pos

#define RCC_CIFR_PLLRDYF_Pos (5U)

◆ RCC_CR_CSSON

#define RCC_CR_CSSON RCC_CR_CSSON_Msk

HSE Clock Security System enable

◆ RCC_CR_CSSON_Msk

#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos)

0x00080000

◆ RCC_CR_CSSON_Pos

#define RCC_CR_CSSON_Pos (19U)

◆ RCC_CR_HSEBYP

#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk

External High Speed clock Bypass

◆ RCC_CR_HSEBYP_Msk

#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos)

0x00040000

◆ RCC_CR_HSEBYP_Pos

#define RCC_CR_HSEBYP_Pos (18U)

◆ RCC_CR_HSEON

#define RCC_CR_HSEON RCC_CR_HSEON_Msk

External High Speed clock enable

◆ RCC_CR_HSEON_Msk

#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)

0x00010000

◆ RCC_CR_HSEON_Pos

#define RCC_CR_HSEON_Pos (16U)

◆ RCC_CR_HSERDY

#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk

External High Speed clock ready

◆ RCC_CR_HSERDY_Msk

#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)

0x00020000

◆ RCC_CR_HSERDY_Pos

#define RCC_CR_HSERDY_Pos (17U)

◆ RCC_CR_HSIDIV

#define RCC_CR_HSIDIV RCC_CR_HSIDIV_Msk

HSIDIV[13:11] Internal High Speed clock division factor

◆ RCC_CR_HSIDIV_0

#define RCC_CR_HSIDIV_0 (0x1UL << RCC_CR_HSIDIV_Pos)

0x00000800

◆ RCC_CR_HSIDIV_1

#define RCC_CR_HSIDIV_1 (0x2UL << RCC_CR_HSIDIV_Pos)

0x00001000

◆ RCC_CR_HSIDIV_2

#define RCC_CR_HSIDIV_2 (0x4UL << RCC_CR_HSIDIV_Pos)

0x00002000

◆ RCC_CR_HSIDIV_Msk

#define RCC_CR_HSIDIV_Msk (0x7UL << RCC_CR_HSIDIV_Pos)

0x00003800

◆ RCC_CR_HSIDIV_Pos

#define RCC_CR_HSIDIV_Pos (11U)

◆ RCC_CR_HSIKERON

#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk

Internal High Speed clock enable for some IPs Kernel

◆ RCC_CR_HSIKERON_Msk

#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos)

0x00000200

◆ RCC_CR_HSIKERON_Pos

#define RCC_CR_HSIKERON_Pos (9U)

◆ RCC_CR_HSION

#define RCC_CR_HSION RCC_CR_HSION_Msk

Internal High Speed clock enable

◆ RCC_CR_HSION_Msk

#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos)

0x00000100

◆ RCC_CR_HSION_Pos

#define RCC_CR_HSION_Pos (8U)

◆ RCC_CR_HSIRDY

#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk

Internal High Speed clock ready flag

◆ RCC_CR_HSIRDY_Msk

#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)

0x00000400

◆ RCC_CR_HSIRDY_Pos

#define RCC_CR_HSIRDY_Pos (10U)

◆ RCC_CR_PLLON

#define RCC_CR_PLLON RCC_CR_PLLON_Msk

System PLL clock enable

◆ RCC_CR_PLLON_Msk

#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)

0x01000000

◆ RCC_CR_PLLON_Pos

#define RCC_CR_PLLON_Pos (24U)

◆ RCC_CR_PLLRDY

#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk

System PLL clock ready

◆ RCC_CR_PLLRDY_Msk

#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)

0x02000000

◆ RCC_CR_PLLRDY_Pos

#define RCC_CR_PLLRDY_Pos (25U)

◆ RCC_CSR_IWDGRSTF

#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk

◆ RCC_CSR_IWDGRSTF_Msk

#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos)

0x20000000

◆ RCC_CSR_IWDGRSTF_Pos

#define RCC_CSR_IWDGRSTF_Pos (29U)

◆ RCC_CSR_LPWRRSTF

#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk

◆ RCC_CSR_LPWRRSTF_Msk

#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos)

0x80000000

◆ RCC_CSR_LPWRRSTF_Pos

#define RCC_CSR_LPWRRSTF_Pos (31U)

◆ RCC_CSR_LSION

#define RCC_CSR_LSION RCC_CSR_LSION_Msk

◆ RCC_CSR_LSION_Msk

#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos)

0x00000001

◆ RCC_CSR_LSION_Pos

#define RCC_CSR_LSION_Pos (0U)

◆ RCC_CSR_LSIRDY

#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk

◆ RCC_CSR_LSIRDY_Msk

#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos)

0x00000002

◆ RCC_CSR_LSIRDY_Pos

#define RCC_CSR_LSIRDY_Pos (1U)

◆ RCC_CSR_OBLRSTF

#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk

◆ RCC_CSR_OBLRSTF_Msk

#define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos)

0x02000000

◆ RCC_CSR_OBLRSTF_Pos

#define RCC_CSR_OBLRSTF_Pos (25U)

◆ RCC_CSR_PINRSTF

#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk

◆ RCC_CSR_PINRSTF_Msk

#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos)

0x04000000

◆ RCC_CSR_PINRSTF_Pos

#define RCC_CSR_PINRSTF_Pos (26U)

◆ RCC_CSR_PWRRSTF

#define RCC_CSR_PWRRSTF RCC_CSR_PWRRSTF_Msk

◆ RCC_CSR_PWRRSTF_Msk

#define RCC_CSR_PWRRSTF_Msk (0x1UL << RCC_CSR_PWRRSTF_Pos)

0x08000000

◆ RCC_CSR_PWRRSTF_Pos

#define RCC_CSR_PWRRSTF_Pos (27U)

◆ RCC_CSR_RMVF

#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk

◆ RCC_CSR_RMVF_Msk

#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos)

0x00800000

◆ RCC_CSR_RMVF_Pos

#define RCC_CSR_RMVF_Pos (23U)

◆ RCC_CSR_SFTRSTF

#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk

◆ RCC_CSR_SFTRSTF_Msk

#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos)

0x10000000

◆ RCC_CSR_SFTRSTF_Pos

#define RCC_CSR_SFTRSTF_Pos (28U)

◆ RCC_CSR_WWDGRSTF

#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk

◆ RCC_CSR_WWDGRSTF_Msk

#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos)

0x40000000

◆ RCC_CSR_WWDGRSTF_Pos

#define RCC_CSR_WWDGRSTF_Pos (30U)

◆ RCC_ICSCR_HSICAL

#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk

HSICAL[7:0] bits

◆ RCC_ICSCR_HSICAL_0

#define RCC_ICSCR_HSICAL_0 (0x01UL << RCC_ICSCR_HSICAL_Pos)

0x00000001

◆ RCC_ICSCR_HSICAL_1

#define RCC_ICSCR_HSICAL_1 (0x02UL << RCC_ICSCR_HSICAL_Pos)

0x00000002

◆ RCC_ICSCR_HSICAL_2

#define RCC_ICSCR_HSICAL_2 (0x04UL << RCC_ICSCR_HSICAL_Pos)

0x00000004

◆ RCC_ICSCR_HSICAL_3

#define RCC_ICSCR_HSICAL_3 (0x08UL << RCC_ICSCR_HSICAL_Pos)

0x00000008

◆ RCC_ICSCR_HSICAL_4

#define RCC_ICSCR_HSICAL_4 (0x10UL << RCC_ICSCR_HSICAL_Pos)

0x00000010

◆ RCC_ICSCR_HSICAL_5

#define RCC_ICSCR_HSICAL_5 (0x20UL << RCC_ICSCR_HSICAL_Pos)

0x00000020

◆ RCC_ICSCR_HSICAL_6

#define RCC_ICSCR_HSICAL_6 (0x40UL << RCC_ICSCR_HSICAL_Pos)

0x00000040

◆ RCC_ICSCR_HSICAL_7

#define RCC_ICSCR_HSICAL_7 (0x80UL << RCC_ICSCR_HSICAL_Pos)

0x00000080 HSITRIM configuration

◆ RCC_ICSCR_HSICAL_Msk

#define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos)

0x000000FF

◆ RCC_ICSCR_HSICAL_Pos

#define RCC_ICSCR_HSICAL_Pos (0U)

< HSICAL configuration

◆ RCC_ICSCR_HSITRIM

#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk

HSITRIM[14:8] bits

◆ RCC_ICSCR_HSITRIM_0

#define RCC_ICSCR_HSITRIM_0 (0x01UL << RCC_ICSCR_HSITRIM_Pos)

0x00000100

◆ RCC_ICSCR_HSITRIM_1

#define RCC_ICSCR_HSITRIM_1 (0x02UL << RCC_ICSCR_HSITRIM_Pos)

0x00000200

◆ RCC_ICSCR_HSITRIM_2

#define RCC_ICSCR_HSITRIM_2 (0x04UL << RCC_ICSCR_HSITRIM_Pos)

0x00000400

◆ RCC_ICSCR_HSITRIM_3

#define RCC_ICSCR_HSITRIM_3 (0x08UL << RCC_ICSCR_HSITRIM_Pos)

0x00000800

◆ RCC_ICSCR_HSITRIM_4

#define RCC_ICSCR_HSITRIM_4 (0x10UL << RCC_ICSCR_HSITRIM_Pos)

0x00001000

◆ RCC_ICSCR_HSITRIM_5

#define RCC_ICSCR_HSITRIM_5 (0x20UL << RCC_ICSCR_HSITRIM_Pos)

0x00002000

◆ RCC_ICSCR_HSITRIM_6

#define RCC_ICSCR_HSITRIM_6 (0x40UL << RCC_ICSCR_HSITRIM_Pos)

0x00004000

◆ RCC_ICSCR_HSITRIM_Msk

#define RCC_ICSCR_HSITRIM_Msk (0x7FUL << RCC_ICSCR_HSITRIM_Pos)

0x00007F00

◆ RCC_ICSCR_HSITRIM_Pos

#define RCC_ICSCR_HSITRIM_Pos (8U)

◆ RCC_IOPENR_GPIOAEN

#define RCC_IOPENR_GPIOAEN RCC_IOPENR_GPIOAEN_Msk

◆ RCC_IOPENR_GPIOAEN_Msk

#define RCC_IOPENR_GPIOAEN_Msk (0x1UL << RCC_IOPENR_GPIOAEN_Pos)

0x00000001

◆ RCC_IOPENR_GPIOAEN_Pos

#define RCC_IOPENR_GPIOAEN_Pos (0U)

◆ RCC_IOPENR_GPIOBEN

#define RCC_IOPENR_GPIOBEN RCC_IOPENR_GPIOBEN_Msk

◆ RCC_IOPENR_GPIOBEN_Msk

#define RCC_IOPENR_GPIOBEN_Msk (0x1UL << RCC_IOPENR_GPIOBEN_Pos)

0x00000002

◆ RCC_IOPENR_GPIOBEN_Pos

#define RCC_IOPENR_GPIOBEN_Pos (1U)

◆ RCC_IOPENR_GPIOCEN

#define RCC_IOPENR_GPIOCEN RCC_IOPENR_GPIOCEN_Msk

◆ RCC_IOPENR_GPIOCEN_Msk

#define RCC_IOPENR_GPIOCEN_Msk (0x1UL << RCC_IOPENR_GPIOCEN_Pos)

0x00000004

◆ RCC_IOPENR_GPIOCEN_Pos

#define RCC_IOPENR_GPIOCEN_Pos (2U)

◆ RCC_IOPENR_GPIODEN

#define RCC_IOPENR_GPIODEN RCC_IOPENR_GPIODEN_Msk

◆ RCC_IOPENR_GPIODEN_Msk

#define RCC_IOPENR_GPIODEN_Msk (0x1UL << RCC_IOPENR_GPIODEN_Pos)

0x00000008

◆ RCC_IOPENR_GPIODEN_Pos

#define RCC_IOPENR_GPIODEN_Pos (3U)

◆ RCC_IOPENR_GPIOFEN

#define RCC_IOPENR_GPIOFEN RCC_IOPENR_GPIOFEN_Msk

◆ RCC_IOPENR_GPIOFEN_Msk

#define RCC_IOPENR_GPIOFEN_Msk (0x1UL << RCC_IOPENR_GPIOFEN_Pos)

0x00000020

◆ RCC_IOPENR_GPIOFEN_Pos

#define RCC_IOPENR_GPIOFEN_Pos (5U)

◆ RCC_IOPRSTR_GPIOARST

#define RCC_IOPRSTR_GPIOARST RCC_IOPRSTR_GPIOARST_Msk

◆ RCC_IOPRSTR_GPIOARST_Msk

#define RCC_IOPRSTR_GPIOARST_Msk (0x1UL << RCC_IOPRSTR_GPIOARST_Pos)

0x00000001

◆ RCC_IOPRSTR_GPIOARST_Pos

#define RCC_IOPRSTR_GPIOARST_Pos (0U)

◆ RCC_IOPRSTR_GPIOBRST

#define RCC_IOPRSTR_GPIOBRST RCC_IOPRSTR_GPIOBRST_Msk

◆ RCC_IOPRSTR_GPIOBRST_Msk

#define RCC_IOPRSTR_GPIOBRST_Msk (0x1UL << RCC_IOPRSTR_GPIOBRST_Pos)

0x00000002

◆ RCC_IOPRSTR_GPIOBRST_Pos

#define RCC_IOPRSTR_GPIOBRST_Pos (1U)

◆ RCC_IOPRSTR_GPIOCRST

#define RCC_IOPRSTR_GPIOCRST RCC_IOPRSTR_GPIOCRST_Msk

◆ RCC_IOPRSTR_GPIOCRST_Msk

#define RCC_IOPRSTR_GPIOCRST_Msk (0x1UL << RCC_IOPRSTR_GPIOCRST_Pos)

0x00000004

◆ RCC_IOPRSTR_GPIOCRST_Pos

#define RCC_IOPRSTR_GPIOCRST_Pos (2U)

◆ RCC_IOPRSTR_GPIODRST

#define RCC_IOPRSTR_GPIODRST RCC_IOPRSTR_GPIODRST_Msk

◆ RCC_IOPRSTR_GPIODRST_Msk

#define RCC_IOPRSTR_GPIODRST_Msk (0x1UL << RCC_IOPRSTR_GPIODRST_Pos)

0x00000008

◆ RCC_IOPRSTR_GPIODRST_Pos

#define RCC_IOPRSTR_GPIODRST_Pos (3U)

◆ RCC_IOPRSTR_GPIOFRST

#define RCC_IOPRSTR_GPIOFRST RCC_IOPRSTR_GPIOFRST_Msk

◆ RCC_IOPRSTR_GPIOFRST_Msk

#define RCC_IOPRSTR_GPIOFRST_Msk (0x1UL << RCC_IOPRSTR_GPIOFRST_Pos)

0x00000020

◆ RCC_IOPRSTR_GPIOFRST_Pos

#define RCC_IOPRSTR_GPIOFRST_Pos (5U)

◆ RCC_IOPSMENR_GPIOASMEN

#define RCC_IOPSMENR_GPIOASMEN RCC_IOPSMENR_GPIOASMEN_Msk

◆ RCC_IOPSMENR_GPIOASMEN_Msk

#define RCC_IOPSMENR_GPIOASMEN_Msk (0x1UL << RCC_IOPSMENR_GPIOASMEN_Pos)

0x00000001

◆ RCC_IOPSMENR_GPIOASMEN_Pos

#define RCC_IOPSMENR_GPIOASMEN_Pos (0U)

◆ RCC_IOPSMENR_GPIOBSMEN

#define RCC_IOPSMENR_GPIOBSMEN RCC_IOPSMENR_GPIOBSMEN_Msk

◆ RCC_IOPSMENR_GPIOBSMEN_Msk

#define RCC_IOPSMENR_GPIOBSMEN_Msk (0x1UL << RCC_IOPSMENR_GPIOBSMEN_Pos)

0x00000002

◆ RCC_IOPSMENR_GPIOBSMEN_Pos

#define RCC_IOPSMENR_GPIOBSMEN_Pos (1U)

◆ RCC_IOPSMENR_GPIOCSMEN

#define RCC_IOPSMENR_GPIOCSMEN RCC_IOPSMENR_GPIOCSMEN_Msk

◆ RCC_IOPSMENR_GPIOCSMEN_Msk

#define RCC_IOPSMENR_GPIOCSMEN_Msk (0x1UL << RCC_IOPSMENR_GPIOCSMEN_Pos)

0x00000004

◆ RCC_IOPSMENR_GPIOCSMEN_Pos

#define RCC_IOPSMENR_GPIOCSMEN_Pos (2U)

◆ RCC_IOPSMENR_GPIODSMEN

#define RCC_IOPSMENR_GPIODSMEN RCC_IOPSMENR_GPIODSMEN_Msk

◆ RCC_IOPSMENR_GPIODSMEN_Msk

#define RCC_IOPSMENR_GPIODSMEN_Msk (0x1UL << RCC_IOPSMENR_GPIODSMEN_Pos)

0x00000008

◆ RCC_IOPSMENR_GPIODSMEN_Pos

#define RCC_IOPSMENR_GPIODSMEN_Pos (3U)

◆ RCC_IOPSMENR_GPIOFSMEN

#define RCC_IOPSMENR_GPIOFSMEN RCC_IOPSMENR_GPIOFSMEN_Msk

◆ RCC_IOPSMENR_GPIOFSMEN_Msk

#define RCC_IOPSMENR_GPIOFSMEN_Msk (0x1UL << RCC_IOPSMENR_GPIOFSMEN_Pos)

0x00000020

◆ RCC_IOPSMENR_GPIOFSMEN_Pos

#define RCC_IOPSMENR_GPIOFSMEN_Pos (5U)

◆ RCC_PLLCFGR_PLLM

#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk

◆ RCC_PLLCFGR_PLLM_0

#define RCC_PLLCFGR_PLLM_0 (0x1UL << RCC_PLLCFGR_PLLM_Pos)

0x00000010

◆ RCC_PLLCFGR_PLLM_1

#define RCC_PLLCFGR_PLLM_1 (0x2UL << RCC_PLLCFGR_PLLM_Pos)

0x00000020

◆ RCC_PLLCFGR_PLLM_2

#define RCC_PLLCFGR_PLLM_2 (0x4UL << RCC_PLLCFGR_PLLM_Pos)

0x00000040

◆ RCC_PLLCFGR_PLLM_Msk

#define RCC_PLLCFGR_PLLM_Msk (0x7UL << RCC_PLLCFGR_PLLM_Pos)

0x00000070

◆ RCC_PLLCFGR_PLLM_Pos

#define RCC_PLLCFGR_PLLM_Pos (4U)

◆ RCC_PLLCFGR_PLLN

#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk

◆ RCC_PLLCFGR_PLLN_0

#define RCC_PLLCFGR_PLLN_0 (0x01UL << RCC_PLLCFGR_PLLN_Pos)

0x00000100

◆ RCC_PLLCFGR_PLLN_1

#define RCC_PLLCFGR_PLLN_1 (0x02UL << RCC_PLLCFGR_PLLN_Pos)

0x00000200

◆ RCC_PLLCFGR_PLLN_2

#define RCC_PLLCFGR_PLLN_2 (0x04UL << RCC_PLLCFGR_PLLN_Pos)

0x00000400

◆ RCC_PLLCFGR_PLLN_3

#define RCC_PLLCFGR_PLLN_3 (0x08UL << RCC_PLLCFGR_PLLN_Pos)

0x00000800

◆ RCC_PLLCFGR_PLLN_4

#define RCC_PLLCFGR_PLLN_4 (0x10UL << RCC_PLLCFGR_PLLN_Pos)

0x00001000

◆ RCC_PLLCFGR_PLLN_5

#define RCC_PLLCFGR_PLLN_5 (0x20UL << RCC_PLLCFGR_PLLN_Pos)

0x00002000

◆ RCC_PLLCFGR_PLLN_6

#define RCC_PLLCFGR_PLLN_6 (0x40UL << RCC_PLLCFGR_PLLN_Pos)

0x00004000

◆ RCC_PLLCFGR_PLLN_Msk

#define RCC_PLLCFGR_PLLN_Msk (0x7FUL << RCC_PLLCFGR_PLLN_Pos)

0x00007F00

◆ RCC_PLLCFGR_PLLN_Pos

#define RCC_PLLCFGR_PLLN_Pos (8U)

◆ RCC_PLLCFGR_PLLP

#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk

◆ RCC_PLLCFGR_PLLP_0

#define RCC_PLLCFGR_PLLP_0 (0x01UL << RCC_PLLCFGR_PLLP_Pos)

0x00020000

◆ RCC_PLLCFGR_PLLP_1

#define RCC_PLLCFGR_PLLP_1 (0x02UL << RCC_PLLCFGR_PLLP_Pos)

0x00040000

◆ RCC_PLLCFGR_PLLP_2

#define RCC_PLLCFGR_PLLP_2 (0x04UL << RCC_PLLCFGR_PLLP_Pos)

0x00080000

◆ RCC_PLLCFGR_PLLP_3

#define RCC_PLLCFGR_PLLP_3 (0x08UL << RCC_PLLCFGR_PLLP_Pos)

0x00100000

◆ RCC_PLLCFGR_PLLP_4

#define RCC_PLLCFGR_PLLP_4 (0x10UL << RCC_PLLCFGR_PLLP_Pos)

0x00200000

◆ RCC_PLLCFGR_PLLP_Msk

#define RCC_PLLCFGR_PLLP_Msk (0x1FUL << RCC_PLLCFGR_PLLP_Pos)

0x003E0000

◆ RCC_PLLCFGR_PLLP_Pos

#define RCC_PLLCFGR_PLLP_Pos (17U)

◆ RCC_PLLCFGR_PLLPEN

#define RCC_PLLCFGR_PLLPEN RCC_PLLCFGR_PLLPEN_Msk

◆ RCC_PLLCFGR_PLLPEN_Msk

#define RCC_PLLCFGR_PLLPEN_Msk (0x1UL << RCC_PLLCFGR_PLLPEN_Pos)

0x00010000

◆ RCC_PLLCFGR_PLLPEN_Pos

#define RCC_PLLCFGR_PLLPEN_Pos (16U)

◆ RCC_PLLCFGR_PLLR

#define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk

◆ RCC_PLLCFGR_PLLR_0

#define RCC_PLLCFGR_PLLR_0 (0x1UL << RCC_PLLCFGR_PLLR_Pos)

0x20000000

◆ RCC_PLLCFGR_PLLR_1

#define RCC_PLLCFGR_PLLR_1 (0x2UL << RCC_PLLCFGR_PLLR_Pos)

0x40000000

◆ RCC_PLLCFGR_PLLR_2

#define RCC_PLLCFGR_PLLR_2 (0x4UL << RCC_PLLCFGR_PLLR_Pos)

0x80000000

◆ RCC_PLLCFGR_PLLR_Msk

#define RCC_PLLCFGR_PLLR_Msk (0x7UL << RCC_PLLCFGR_PLLR_Pos)

0xE0000000

◆ RCC_PLLCFGR_PLLR_Pos

#define RCC_PLLCFGR_PLLR_Pos (29U)

◆ RCC_PLLCFGR_PLLREN

#define RCC_PLLCFGR_PLLREN RCC_PLLCFGR_PLLREN_Msk

◆ RCC_PLLCFGR_PLLREN_Msk

#define RCC_PLLCFGR_PLLREN_Msk (0x1UL << RCC_PLLCFGR_PLLREN_Pos)

0x10000000

◆ RCC_PLLCFGR_PLLREN_Pos

#define RCC_PLLCFGR_PLLREN_Pos (28U)

◆ RCC_PLLCFGR_PLLSRC

#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk

◆ RCC_PLLCFGR_PLLSRC_0

#define RCC_PLLCFGR_PLLSRC_0 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)

0x00000001

◆ RCC_PLLCFGR_PLLSRC_1

#define RCC_PLLCFGR_PLLSRC_1 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos)

0x00000002

◆ RCC_PLLCFGR_PLLSRC_HSE

#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk

HSE source clock selected

◆ RCC_PLLCFGR_PLLSRC_HSE_Msk

#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)

0x00000003

◆ RCC_PLLCFGR_PLLSRC_HSE_Pos

#define RCC_PLLCFGR_PLLSRC_HSE_Pos (0U)

◆ RCC_PLLCFGR_PLLSRC_HSI

#define RCC_PLLCFGR_PLLSRC_HSI RCC_PLLCFGR_PLLSRC_HSI_Msk

HSI source clock selected

◆ RCC_PLLCFGR_PLLSRC_HSI_Msk

#define RCC_PLLCFGR_PLLSRC_HSI_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSI_Pos)

0x00000002

◆ RCC_PLLCFGR_PLLSRC_HSI_Pos

#define RCC_PLLCFGR_PLLSRC_HSI_Pos (1U)

◆ RCC_PLLCFGR_PLLSRC_Msk

#define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos)

0x00000003

◆ RCC_PLLCFGR_PLLSRC_NONE

#define RCC_PLLCFGR_PLLSRC_NONE (0x00000000UL)

No clock sent to PLL

◆ RCC_PLLCFGR_PLLSRC_Pos

#define RCC_PLLCFGR_PLLSRC_Pos (0U)

◆ RTC_ALRMAR_DT

#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk

◆ RTC_ALRMAR_DT_0

#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos)

0x10000000

◆ RTC_ALRMAR_DT_1

#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos)

0x20000000

◆ RTC_ALRMAR_DT_Msk

#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos)

0x30000000

◆ RTC_ALRMAR_DT_Pos

#define RTC_ALRMAR_DT_Pos (28U)

◆ RTC_ALRMAR_DU

#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk

◆ RTC_ALRMAR_DU_0

#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos)

0x01000000

◆ RTC_ALRMAR_DU_1

#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos)

0x02000000

◆ RTC_ALRMAR_DU_2

#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos)

0x04000000

◆ RTC_ALRMAR_DU_3

#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos)

0x08000000

◆ RTC_ALRMAR_DU_Msk

#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos)

0x0F000000

◆ RTC_ALRMAR_DU_Pos

#define RTC_ALRMAR_DU_Pos (24U)

◆ RTC_ALRMAR_HT

#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk

◆ RTC_ALRMAR_HT_0

#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos)

0x00100000

◆ RTC_ALRMAR_HT_1

#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos)

0x00200000

◆ RTC_ALRMAR_HT_Msk

#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos)

0x00300000

◆ RTC_ALRMAR_HT_Pos

#define RTC_ALRMAR_HT_Pos (20U)

◆ RTC_ALRMAR_HU

#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk

◆ RTC_ALRMAR_HU_0

#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos)

0x00010000

◆ RTC_ALRMAR_HU_1

#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos)

0x00020000

◆ RTC_ALRMAR_HU_2

#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos)

0x00040000

◆ RTC_ALRMAR_HU_3

#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos)

0x00080000

◆ RTC_ALRMAR_HU_Msk

#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos)

0x000F0000

◆ RTC_ALRMAR_HU_Pos

#define RTC_ALRMAR_HU_Pos (16U)

◆ RTC_ALRMAR_MNT

#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk

◆ RTC_ALRMAR_MNT_0

#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos)

0x00001000

◆ RTC_ALRMAR_MNT_1

#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos)

0x00002000

◆ RTC_ALRMAR_MNT_2

#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos)

0x00004000

◆ RTC_ALRMAR_MNT_Msk

#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos)

0x00007000

◆ RTC_ALRMAR_MNT_Pos

#define RTC_ALRMAR_MNT_Pos (12U)

◆ RTC_ALRMAR_MNU

#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk

◆ RTC_ALRMAR_MNU_0

#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos)

0x00000100

◆ RTC_ALRMAR_MNU_1

#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos)

0x00000200

◆ RTC_ALRMAR_MNU_2

#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos)

0x00000400

◆ RTC_ALRMAR_MNU_3

#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos)

0x00000800

◆ RTC_ALRMAR_MNU_Msk

#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos)

0x00000F00

◆ RTC_ALRMAR_MNU_Pos

#define RTC_ALRMAR_MNU_Pos (8U)

◆ RTC_ALRMAR_MSK1

#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk

◆ RTC_ALRMAR_MSK1_Msk

#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos)

0x00000080

◆ RTC_ALRMAR_MSK1_Pos

#define RTC_ALRMAR_MSK1_Pos (7U)

◆ RTC_ALRMAR_MSK2

#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk

◆ RTC_ALRMAR_MSK2_Msk

#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos)

0x00008000

◆ RTC_ALRMAR_MSK2_Pos

#define RTC_ALRMAR_MSK2_Pos (15U)

◆ RTC_ALRMAR_MSK3

#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk

◆ RTC_ALRMAR_MSK3_Msk

#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos)

0x00800000

◆ RTC_ALRMAR_MSK3_Pos

#define RTC_ALRMAR_MSK3_Pos (23U)

◆ RTC_ALRMAR_MSK4

#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk

◆ RTC_ALRMAR_MSK4_Msk

#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos)

0x80000000

◆ RTC_ALRMAR_MSK4_Pos

#define RTC_ALRMAR_MSK4_Pos (31U)

◆ RTC_ALRMAR_PM

#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk

◆ RTC_ALRMAR_PM_Msk

#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos)

0x00400000

◆ RTC_ALRMAR_PM_Pos

#define RTC_ALRMAR_PM_Pos (22U)

◆ RTC_ALRMAR_ST

#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk

◆ RTC_ALRMAR_ST_0

#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos)

0x00000010

◆ RTC_ALRMAR_ST_1

#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos)

0x00000020

◆ RTC_ALRMAR_ST_2

#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos)

0x00000040

◆ RTC_ALRMAR_ST_Msk

#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos)

0x00000070

◆ RTC_ALRMAR_ST_Pos

#define RTC_ALRMAR_ST_Pos (4U)

◆ RTC_ALRMAR_SU

#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk

◆ RTC_ALRMAR_SU_0

#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos)

0x00000001

◆ RTC_ALRMAR_SU_1

#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos)

0x00000002

◆ RTC_ALRMAR_SU_2

#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos)

0x00000004

◆ RTC_ALRMAR_SU_3

#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos)

0x00000008

◆ RTC_ALRMAR_SU_Msk

#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos)

0x0000000F

◆ RTC_ALRMAR_SU_Pos

#define RTC_ALRMAR_SU_Pos (0U)

◆ RTC_ALRMAR_WDSEL

#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk

◆ RTC_ALRMAR_WDSEL_Msk

#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos)

0x40000000

◆ RTC_ALRMAR_WDSEL_Pos

#define RTC_ALRMAR_WDSEL_Pos (30U)

◆ RTC_ALRMASSR_MASKSS

#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk

◆ RTC_ALRMASSR_MASKSS_0

#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos)

0x01000000

◆ RTC_ALRMASSR_MASKSS_1

#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos)

0x02000000

◆ RTC_ALRMASSR_MASKSS_2

#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos)

0x04000000

◆ RTC_ALRMASSR_MASKSS_3

#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos)

0x08000000

◆ RTC_ALRMASSR_MASKSS_Msk

#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos)

0x0F000000

◆ RTC_ALRMASSR_MASKSS_Pos

#define RTC_ALRMASSR_MASKSS_Pos (24U)

◆ RTC_ALRMASSR_SS

#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk

◆ RTC_ALRMASSR_SS_Msk

#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos)

0x00007FFF

◆ RTC_ALRMASSR_SS_Pos

#define RTC_ALRMASSR_SS_Pos (0U)

◆ RTC_ALRMBR_DT

#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk

◆ RTC_ALRMBR_DT_0

#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos)

0x10000000

◆ RTC_ALRMBR_DT_1

#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos)

0x20000000

◆ RTC_ALRMBR_DT_Msk

#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos)

0x30000000

◆ RTC_ALRMBR_DT_Pos

#define RTC_ALRMBR_DT_Pos (28U)

◆ RTC_ALRMBR_DU

#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk

◆ RTC_ALRMBR_DU_0

#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos)

0x01000000

◆ RTC_ALRMBR_DU_1

#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos)

0x02000000

◆ RTC_ALRMBR_DU_2

#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos)

0x04000000

◆ RTC_ALRMBR_DU_3

#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos)

0x08000000

◆ RTC_ALRMBR_DU_Msk

#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos)

0x0F000000

◆ RTC_ALRMBR_DU_Pos

#define RTC_ALRMBR_DU_Pos (24U)

◆ RTC_ALRMBR_HT

#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk

◆ RTC_ALRMBR_HT_0

#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos)

0x00100000

◆ RTC_ALRMBR_HT_1

#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos)

0x00200000

◆ RTC_ALRMBR_HT_Msk

#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos)

0x00300000

◆ RTC_ALRMBR_HT_Pos

#define RTC_ALRMBR_HT_Pos (20U)

◆ RTC_ALRMBR_HU

#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk

◆ RTC_ALRMBR_HU_0

#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos)

0x00010000

◆ RTC_ALRMBR_HU_1

#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos)

0x00020000

◆ RTC_ALRMBR_HU_2

#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos)

0x00040000

◆ RTC_ALRMBR_HU_3

#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos)

0x00080000

◆ RTC_ALRMBR_HU_Msk

#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos)

0x000F0000

◆ RTC_ALRMBR_HU_Pos

#define RTC_ALRMBR_HU_Pos (16U)

◆ RTC_ALRMBR_MNT

#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk

◆ RTC_ALRMBR_MNT_0

#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos)

0x00001000

◆ RTC_ALRMBR_MNT_1

#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos)

0x00002000

◆ RTC_ALRMBR_MNT_2

#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos)

0x00004000

◆ RTC_ALRMBR_MNT_Msk

#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos)

0x00007000

◆ RTC_ALRMBR_MNT_Pos

#define RTC_ALRMBR_MNT_Pos (12U)

◆ RTC_ALRMBR_MNU

#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk

◆ RTC_ALRMBR_MNU_0

#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos)

0x00000100

◆ RTC_ALRMBR_MNU_1

#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos)

0x00000200

◆ RTC_ALRMBR_MNU_2

#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos)

0x00000400

◆ RTC_ALRMBR_MNU_3

#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos)

0x00000800

◆ RTC_ALRMBR_MNU_Msk

#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos)

0x00000F00

◆ RTC_ALRMBR_MNU_Pos

#define RTC_ALRMBR_MNU_Pos (8U)

◆ RTC_ALRMBR_MSK1

#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk

◆ RTC_ALRMBR_MSK1_Msk

#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos)

0x00000080

◆ RTC_ALRMBR_MSK1_Pos

#define RTC_ALRMBR_MSK1_Pos (7U)

◆ RTC_ALRMBR_MSK2

#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk

◆ RTC_ALRMBR_MSK2_Msk

#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos)

0x00008000

◆ RTC_ALRMBR_MSK2_Pos

#define RTC_ALRMBR_MSK2_Pos (15U)

◆ RTC_ALRMBR_MSK3

#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk

◆ RTC_ALRMBR_MSK3_Msk

#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos)

0x00800000

◆ RTC_ALRMBR_MSK3_Pos

#define RTC_ALRMBR_MSK3_Pos (23U)

◆ RTC_ALRMBR_MSK4

#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk

◆ RTC_ALRMBR_MSK4_Msk

#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos)

0x80000000

◆ RTC_ALRMBR_MSK4_Pos

#define RTC_ALRMBR_MSK4_Pos (31U)

◆ RTC_ALRMBR_PM

#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk

◆ RTC_ALRMBR_PM_Msk

#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos)

0x00400000

◆ RTC_ALRMBR_PM_Pos

#define RTC_ALRMBR_PM_Pos (22U)

◆ RTC_ALRMBR_ST

#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk

◆ RTC_ALRMBR_ST_0

#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos)

0x00000010

◆ RTC_ALRMBR_ST_1

#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos)

0x00000020

◆ RTC_ALRMBR_ST_2

#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos)

0x00000040

◆ RTC_ALRMBR_ST_Msk

#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos)

0x00000070

◆ RTC_ALRMBR_ST_Pos

#define RTC_ALRMBR_ST_Pos (4U)

◆ RTC_ALRMBR_SU

#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk

◆ RTC_ALRMBR_SU_0

#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos)

0x00000001

◆ RTC_ALRMBR_SU_1

#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos)

0x00000002

◆ RTC_ALRMBR_SU_2

#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos)

0x00000004

◆ RTC_ALRMBR_SU_3

#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos)

0x00000008

◆ RTC_ALRMBR_SU_Msk

#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos)

0x0000000F

◆ RTC_ALRMBR_SU_Pos

#define RTC_ALRMBR_SU_Pos (0U)

◆ RTC_ALRMBR_WDSEL

#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk

◆ RTC_ALRMBR_WDSEL_Msk

#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos)

0x40000000

◆ RTC_ALRMBR_WDSEL_Pos

#define RTC_ALRMBR_WDSEL_Pos (30U)

◆ RTC_ALRMBSSR_MASKSS

#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk

◆ RTC_ALRMBSSR_MASKSS_0

#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)

0x01000000

◆ RTC_ALRMBSSR_MASKSS_1

#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)

0x02000000

◆ RTC_ALRMBSSR_MASKSS_2

#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)

0x04000000

◆ RTC_ALRMBSSR_MASKSS_3

#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)

0x08000000

◆ RTC_ALRMBSSR_MASKSS_Msk

#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)

0x0F000000

◆ RTC_ALRMBSSR_MASKSS_Pos

#define RTC_ALRMBSSR_MASKSS_Pos (24U)

◆ RTC_ALRMBSSR_SS

#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk

◆ RTC_ALRMBSSR_SS_Msk

#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)

0x00007FFF

◆ RTC_ALRMBSSR_SS_Pos

#define RTC_ALRMBSSR_SS_Pos (0U)

◆ RTC_BACKUP_SUPPORT

#define RTC_BACKUP_SUPPORT

◆ RTC_CALR_CALM

#define RTC_CALR_CALM RTC_CALR_CALM_Msk

◆ RTC_CALR_CALM_0

#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos)

0x00000001

◆ RTC_CALR_CALM_1

#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos)

0x00000002

◆ RTC_CALR_CALM_2

#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos)

0x00000004

◆ RTC_CALR_CALM_3

#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos)

0x00000008

◆ RTC_CALR_CALM_4

#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos)

0x00000010

◆ RTC_CALR_CALM_5

#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos)

0x00000020

◆ RTC_CALR_CALM_6

#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos)

0x00000040

◆ RTC_CALR_CALM_7

#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos)

0x00000080

◆ RTC_CALR_CALM_8

#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos)

0x00000100

◆ RTC_CALR_CALM_Msk

#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos)

0x000001FF

◆ RTC_CALR_CALM_Pos

#define RTC_CALR_CALM_Pos (0U)

◆ RTC_CALR_CALP

#define RTC_CALR_CALP RTC_CALR_CALP_Msk

◆ RTC_CALR_CALP_Msk

#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos)

0x00008000

◆ RTC_CALR_CALP_Pos

#define RTC_CALR_CALP_Pos (15U)

◆ RTC_CALR_CALW16

#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk

◆ RTC_CALR_CALW16_Msk

#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos)

0x00002000

◆ RTC_CALR_CALW16_Pos

#define RTC_CALR_CALW16_Pos (13U)

◆ RTC_CALR_CALW8

#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk

◆ RTC_CALR_CALW8_Msk

#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos)

0x00004000

◆ RTC_CALR_CALW8_Pos

#define RTC_CALR_CALW8_Pos (14U)

◆ RTC_CR_ADD1H

#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk

◆ RTC_CR_ADD1H_Msk

#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos)

0x00010000

◆ RTC_CR_ADD1H_Pos

#define RTC_CR_ADD1H_Pos (16U)

◆ RTC_CR_ALRAE

#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk

◆ RTC_CR_ALRAE_Msk

#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos)

0x00000100

◆ RTC_CR_ALRAE_Pos

#define RTC_CR_ALRAE_Pos (8U)

◆ RTC_CR_ALRAIE

#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk

◆ RTC_CR_ALRAIE_Msk

#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos)

0x00001000

◆ RTC_CR_ALRAIE_Pos

#define RTC_CR_ALRAIE_Pos (12U)

◆ RTC_CR_ALRBE

#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk

◆ RTC_CR_ALRBE_Msk

#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos)

0x00000200

◆ RTC_CR_ALRBE_Pos

#define RTC_CR_ALRBE_Pos (9U)

◆ RTC_CR_ALRBIE

#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk

◆ RTC_CR_ALRBIE_Msk

#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos)

0x00002000

◆ RTC_CR_ALRBIE_Pos

#define RTC_CR_ALRBIE_Pos (13U)

◆ RTC_CR_BKP

#define RTC_CR_BKP RTC_CR_BKP_Msk

◆ RTC_CR_BKP_Msk

#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos)

0x00040000

◆ RTC_CR_BKP_Pos

#define RTC_CR_BKP_Pos (18U)

◆ RTC_CR_BYPSHAD

#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk

◆ RTC_CR_BYPSHAD_Msk

#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos)

0x00000020

◆ RTC_CR_BYPSHAD_Pos

#define RTC_CR_BYPSHAD_Pos (5U)

◆ RTC_CR_COE

#define RTC_CR_COE RTC_CR_COE_Msk

◆ RTC_CR_COE_Msk

#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos)

0x00800000

◆ RTC_CR_COE_Pos

#define RTC_CR_COE_Pos (23U)

◆ RTC_CR_COSEL

#define RTC_CR_COSEL RTC_CR_COSEL_Msk

◆ RTC_CR_COSEL_Msk

#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos)

0x00080000

◆ RTC_CR_COSEL_Pos

#define RTC_CR_COSEL_Pos (19U)

◆ RTC_CR_FMT

#define RTC_CR_FMT RTC_CR_FMT_Msk

◆ RTC_CR_FMT_Msk

#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos)

0x00000040

◆ RTC_CR_FMT_Pos

#define RTC_CR_FMT_Pos (6U)

◆ RTC_CR_ITSE

#define RTC_CR_ITSE RTC_CR_ITSE_Msk

Timestamp on internal event enable

◆ RTC_CR_ITSE_Msk

#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos)

0x01000000

◆ RTC_CR_ITSE_Pos

#define RTC_CR_ITSE_Pos (24U)

◆ RTC_CR_OSEL

#define RTC_CR_OSEL RTC_CR_OSEL_Msk

◆ RTC_CR_OSEL_0

#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos)

0x00200000

◆ RTC_CR_OSEL_1

#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos)

0x00400000

◆ RTC_CR_OSEL_Msk

#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos)

0x00600000

◆ RTC_CR_OSEL_Pos

#define RTC_CR_OSEL_Pos (21U)

◆ RTC_CR_OUT2EN

#define RTC_CR_OUT2EN RTC_CR_OUT2EN_Msk

RTC_OUT2 output enable

◆ RTC_CR_OUT2EN_Msk

#define RTC_CR_OUT2EN_Msk (0x1UL << RTC_CR_OUT2EN_Pos)

0x80000000

◆ RTC_CR_OUT2EN_Pos

#define RTC_CR_OUT2EN_Pos (31U)

◆ RTC_CR_POL

#define RTC_CR_POL RTC_CR_POL_Msk

◆ RTC_CR_POL_Msk

#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos)

0x00100000

◆ RTC_CR_POL_Pos

#define RTC_CR_POL_Pos (20U)

◆ RTC_CR_REFCKON

#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk

◆ RTC_CR_REFCKON_Msk

#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos)

0x00000010

◆ RTC_CR_REFCKON_Pos

#define RTC_CR_REFCKON_Pos (4U)

◆ RTC_CR_SUB1H

#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk

◆ RTC_CR_SUB1H_Msk

#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos)

0x00020000

◆ RTC_CR_SUB1H_Pos

#define RTC_CR_SUB1H_Pos (17U)

◆ RTC_CR_TAMPALRM_PU

#define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk

TAMPALARM output pull-up config

◆ RTC_CR_TAMPALRM_PU_Msk

#define RTC_CR_TAMPALRM_PU_Msk (0x1UL << RTC_CR_TAMPALRM_PU_Pos)

0x20000000

◆ RTC_CR_TAMPALRM_PU_Pos

#define RTC_CR_TAMPALRM_PU_Pos (29U)

◆ RTC_CR_TAMPALRM_TYPE

#define RTC_CR_TAMPALRM_TYPE RTC_CR_TAMPALRM_TYPE_Msk

TAMPALARM output type

◆ RTC_CR_TAMPALRM_TYPE_Msk

#define RTC_CR_TAMPALRM_TYPE_Msk (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos)

0x40000000

◆ RTC_CR_TAMPALRM_TYPE_Pos

#define RTC_CR_TAMPALRM_TYPE_Pos (30U)

◆ RTC_CR_TAMPOE

#define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk

Tamper detection output enable on TAMPALARM

◆ RTC_CR_TAMPOE_Msk

#define RTC_CR_TAMPOE_Msk (0x1UL << RTC_CR_TAMPOE_Pos)

0x04000000

◆ RTC_CR_TAMPOE_Pos

#define RTC_CR_TAMPOE_Pos (26U)

◆ RTC_CR_TAMPTS

#define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk

Activate timestamp on tamper detection event

◆ RTC_CR_TAMPTS_Msk

#define RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos)

0x02000000

◆ RTC_CR_TAMPTS_Pos

#define RTC_CR_TAMPTS_Pos (25U)

◆ RTC_CR_TSE

#define RTC_CR_TSE RTC_CR_TSE_Msk

timestamp enable >

◆ RTC_CR_TSE_Msk

#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos)

0x00000800

◆ RTC_CR_TSE_Pos

#define RTC_CR_TSE_Pos (11U)

◆ RTC_CR_TSEDGE

#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk

Timestamp event active edge >

◆ RTC_CR_TSEDGE_Msk

#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos)

0x00000008

◆ RTC_CR_TSEDGE_Pos

#define RTC_CR_TSEDGE_Pos (3U)

◆ RTC_CR_TSIE

#define RTC_CR_TSIE RTC_CR_TSIE_Msk

Timestamp interrupt enable >

◆ RTC_CR_TSIE_Msk

#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos)

0x00008000

◆ RTC_CR_TSIE_Pos

#define RTC_CR_TSIE_Pos (15U)

◆ RTC_CR_WUCKSEL

#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk

Wakeup clock selection >

◆ RTC_CR_WUCKSEL_0

#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos)

0x00000001

◆ RTC_CR_WUCKSEL_1

#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos)

0x00000002

◆ RTC_CR_WUCKSEL_2

#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos)

0x00000004

◆ RTC_CR_WUCKSEL_Msk

#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos)

0x00000007

◆ RTC_CR_WUCKSEL_Pos

#define RTC_CR_WUCKSEL_Pos (0U)

◆ RTC_CR_WUTE

#define RTC_CR_WUTE RTC_CR_WUTE_Msk

Wakeup timer enable >

◆ RTC_CR_WUTE_Msk

#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos)

0x00000400

◆ RTC_CR_WUTE_Pos

#define RTC_CR_WUTE_Pos (10U)

◆ RTC_CR_WUTIE

#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk

Wakeup timer interrupt enable >

◆ RTC_CR_WUTIE_Msk

#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos)

0x00004000

◆ RTC_CR_WUTIE_Pos

#define RTC_CR_WUTIE_Pos (14U)

◆ RTC_DR_DT

#define RTC_DR_DT RTC_DR_DT_Msk

◆ RTC_DR_DT_0

#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos)

0x00000010

◆ RTC_DR_DT_1

#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos)

0x00000020

◆ RTC_DR_DT_Msk

#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos)

0x00000030

◆ RTC_DR_DT_Pos

#define RTC_DR_DT_Pos (4U)

◆ RTC_DR_DU

#define RTC_DR_DU RTC_DR_DU_Msk

◆ RTC_DR_DU_0

#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos)

0x00000001

◆ RTC_DR_DU_1

#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos)

0x00000002

◆ RTC_DR_DU_2

#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos)

0x00000004

◆ RTC_DR_DU_3

#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos)

0x00000008

◆ RTC_DR_DU_Msk

#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos)

0x0000000F

◆ RTC_DR_DU_Pos

#define RTC_DR_DU_Pos (0U)

◆ RTC_DR_MT

#define RTC_DR_MT RTC_DR_MT_Msk

◆ RTC_DR_MT_Msk

#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos)

0x00001000

◆ RTC_DR_MT_Pos

#define RTC_DR_MT_Pos (12U)

◆ RTC_DR_MU

#define RTC_DR_MU RTC_DR_MU_Msk

◆ RTC_DR_MU_0

#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos)

0x00000100

◆ RTC_DR_MU_1

#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos)

0x00000200

◆ RTC_DR_MU_2

#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos)

0x00000400

◆ RTC_DR_MU_3

#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos)

0x00000800

◆ RTC_DR_MU_Msk

#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos)

0x00000F00

◆ RTC_DR_MU_Pos

#define RTC_DR_MU_Pos (8U)

◆ RTC_DR_WDU

#define RTC_DR_WDU RTC_DR_WDU_Msk

◆ RTC_DR_WDU_0

#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos)

0x00002000

◆ RTC_DR_WDU_1

#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos)

0x00004000

◆ RTC_DR_WDU_2

#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos)

0x00008000

◆ RTC_DR_WDU_Msk

#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos)

0x0000E000

◆ RTC_DR_WDU_Pos

#define RTC_DR_WDU_Pos (13U)

◆ RTC_DR_YT

#define RTC_DR_YT RTC_DR_YT_Msk

◆ RTC_DR_YT_0

#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos)

0x00100000

◆ RTC_DR_YT_1

#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos)

0x00200000

◆ RTC_DR_YT_2

#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos)

0x00400000

◆ RTC_DR_YT_3

#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos)

0x00800000

◆ RTC_DR_YT_Msk

#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos)

0x00F00000

◆ RTC_DR_YT_Pos

#define RTC_DR_YT_Pos (20U)

◆ RTC_DR_YU

#define RTC_DR_YU RTC_DR_YU_Msk

◆ RTC_DR_YU_0

#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos)

0x00010000

◆ RTC_DR_YU_1

#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos)

0x00020000

◆ RTC_DR_YU_2

#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos)

0x00040000

◆ RTC_DR_YU_3

#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos)

0x00080000

◆ RTC_DR_YU_Msk

#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos)

0x000F0000

◆ RTC_DR_YU_Pos

#define RTC_DR_YU_Pos (16U)

◆ RTC_ICSR_ALRAWF

#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk

◆ RTC_ICSR_ALRAWF_Msk

#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos)

0x00000001

◆ RTC_ICSR_ALRAWF_Pos

#define RTC_ICSR_ALRAWF_Pos (0U)

◆ RTC_ICSR_ALRBWF

#define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk

◆ RTC_ICSR_ALRBWF_Msk

#define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos)

0x00000002

◆ RTC_ICSR_ALRBWF_Pos

#define RTC_ICSR_ALRBWF_Pos (1U)

◆ RTC_ICSR_INIT

#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk

◆ RTC_ICSR_INIT_Msk

#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos)

0x00000080

◆ RTC_ICSR_INIT_Pos

#define RTC_ICSR_INIT_Pos (7U)

◆ RTC_ICSR_INITF

#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk

◆ RTC_ICSR_INITF_Msk

#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos)

0x00000040

◆ RTC_ICSR_INITF_Pos

#define RTC_ICSR_INITF_Pos (6U)

◆ RTC_ICSR_INITS

#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk

◆ RTC_ICSR_INITS_Msk

#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos)

0x00000010

◆ RTC_ICSR_INITS_Pos

#define RTC_ICSR_INITS_Pos (4U)

◆ RTC_ICSR_RECALPF

#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk

◆ RTC_ICSR_RECALPF_Msk

#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos)

0x00010000

◆ RTC_ICSR_RECALPF_Pos

#define RTC_ICSR_RECALPF_Pos (16U)

◆ RTC_ICSR_RSF

#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk

◆ RTC_ICSR_RSF_Msk

#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos)

0x00000020

◆ RTC_ICSR_RSF_Pos

#define RTC_ICSR_RSF_Pos (5U)

◆ RTC_ICSR_SHPF

#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk

◆ RTC_ICSR_SHPF_Msk

#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos)

0x00000008

◆ RTC_ICSR_SHPF_Pos

#define RTC_ICSR_SHPF_Pos (3U)

◆ RTC_ICSR_WUTWF

#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk

Wakeup timer write flag >

◆ RTC_ICSR_WUTWF_Msk

#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos)

0x00000004

◆ RTC_ICSR_WUTWF_Pos

#define RTC_ICSR_WUTWF_Pos (2U)

◆ RTC_MISR_ALRAMF

#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk

◆ RTC_MISR_ALRAMF_Msk

#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos)

0x00000001

◆ RTC_MISR_ALRAMF_Pos

#define RTC_MISR_ALRAMF_Pos (0U)

◆ RTC_MISR_ALRBMF

#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk

◆ RTC_MISR_ALRBMF_Msk

#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos)

0x00000002

◆ RTC_MISR_ALRBMF_Pos

#define RTC_MISR_ALRBMF_Pos (1U)

◆ RTC_MISR_ITSMF

#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk

◆ RTC_MISR_ITSMF_Msk

#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos)

0x00000020

◆ RTC_MISR_ITSMF_Pos

#define RTC_MISR_ITSMF_Pos (5U)

◆ RTC_MISR_TSMF

#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk

Timestamp masked flag >

◆ RTC_MISR_TSMF_Msk

#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos)

0x00000008

◆ RTC_MISR_TSMF_Pos

#define RTC_MISR_TSMF_Pos (3U)

◆ RTC_MISR_TSOVMF

#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk

Timestamp overflow masked flag >

◆ RTC_MISR_TSOVMF_Msk

#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos)

0x00000010

◆ RTC_MISR_TSOVMF_Pos

#define RTC_MISR_TSOVMF_Pos (4U)

◆ RTC_MISR_WUTMF

#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk

Wakeup timer masked flag >

◆ RTC_MISR_WUTMF_Msk

#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos)

0x00000004

◆ RTC_MISR_WUTMF_Pos

#define RTC_MISR_WUTMF_Pos (2U)

◆ RTC_PRER_PREDIV_A

#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk

◆ RTC_PRER_PREDIV_A_Msk

#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos)

0x007F0000

◆ RTC_PRER_PREDIV_A_Pos

#define RTC_PRER_PREDIV_A_Pos (16U)

◆ RTC_PRER_PREDIV_S

#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk

◆ RTC_PRER_PREDIV_S_Msk

#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)

0x00007FFF

◆ RTC_PRER_PREDIV_S_Pos

#define RTC_PRER_PREDIV_S_Pos (0U)

◆ RTC_SCR_CALRAF

#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk

◆ RTC_SCR_CALRAF_Msk

#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos)

0x00000001

◆ RTC_SCR_CALRAF_Pos

#define RTC_SCR_CALRAF_Pos (0U)

◆ RTC_SCR_CALRBF

#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk

◆ RTC_SCR_CALRBF_Msk

#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos)

0x00000002

◆ RTC_SCR_CALRBF_Pos

#define RTC_SCR_CALRBF_Pos (1U)

◆ RTC_SCR_CITSF

#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk

◆ RTC_SCR_CITSF_Msk

#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos)

0x00000020

◆ RTC_SCR_CITSF_Pos

#define RTC_SCR_CITSF_Pos (5U)

◆ RTC_SCR_CTSF

#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk

Clear timestamp flag >

◆ RTC_SCR_CTSF_Msk

#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos)

0x00000008

◆ RTC_SCR_CTSF_Pos

#define RTC_SCR_CTSF_Pos (3U)

◆ RTC_SCR_CTSOVF

#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk

Clear timestamp overflow flag >

◆ RTC_SCR_CTSOVF_Msk

#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos)

0x00000010

◆ RTC_SCR_CTSOVF_Pos

#define RTC_SCR_CTSOVF_Pos (4U)

◆ RTC_SCR_CWUTF

#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk

Clear wakeup timer flag >

◆ RTC_SCR_CWUTF_Msk

#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos)

0x00000004

◆ RTC_SCR_CWUTF_Pos

#define RTC_SCR_CWUTF_Pos (2U)

◆ RTC_SHIFTR_ADD1S

#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk

◆ RTC_SHIFTR_ADD1S_Msk

#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos)

0x80000000

◆ RTC_SHIFTR_ADD1S_Pos

#define RTC_SHIFTR_ADD1S_Pos (31U)

◆ RTC_SHIFTR_SUBFS

#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk

◆ RTC_SHIFTR_SUBFS_Msk

#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)

0x00007FFF

◆ RTC_SHIFTR_SUBFS_Pos

#define RTC_SHIFTR_SUBFS_Pos (0U)

◆ RTC_SR_ALRAF

#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk

◆ RTC_SR_ALRAF_Msk

#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos)

0x00000001

◆ RTC_SR_ALRAF_Pos

#define RTC_SR_ALRAF_Pos (0U)

◆ RTC_SR_ALRBF

#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk

◆ RTC_SR_ALRBF_Msk

#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos)

0x00000002

◆ RTC_SR_ALRBF_Pos

#define RTC_SR_ALRBF_Pos (1U)

◆ RTC_SR_ITSF

#define RTC_SR_ITSF RTC_SR_ITSF_Msk

◆ RTC_SR_ITSF_Msk

#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos)

0x00000020

◆ RTC_SR_ITSF_Pos

#define RTC_SR_ITSF_Pos (5U)

◆ RTC_SR_TSF

#define RTC_SR_TSF RTC_SR_TSF_Msk

Timestamp flag >

◆ RTC_SR_TSF_Msk

#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos)

0x00000008

◆ RTC_SR_TSF_Pos

#define RTC_SR_TSF_Pos (3U)

◆ RTC_SR_TSOVF

#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk

Timestamp overflow flag >

◆ RTC_SR_TSOVF_Msk

#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos)

0x00000010

◆ RTC_SR_TSOVF_Pos

#define RTC_SR_TSOVF_Pos (4U)

◆ RTC_SR_WUTF

#define RTC_SR_WUTF RTC_SR_WUTF_Msk

Wakeup timer flag >

◆ RTC_SR_WUTF_Msk

#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos)

0x00000004

◆ RTC_SR_WUTF_Pos

#define RTC_SR_WUTF_Pos (2U)

◆ RTC_SSR_SS

#define RTC_SSR_SS RTC_SSR_SS_Msk

◆ RTC_SSR_SS_Msk

#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos)

0x0000FFFF

◆ RTC_SSR_SS_Pos

#define RTC_SSR_SS_Pos (0U)

◆ RTC_TR_HT

#define RTC_TR_HT RTC_TR_HT_Msk

◆ RTC_TR_HT_0

#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos)

0x00100000

◆ RTC_TR_HT_1

#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos)

0x00200000

◆ RTC_TR_HT_Msk

#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos)

0x00300000

◆ RTC_TR_HT_Pos

#define RTC_TR_HT_Pos (20U)

◆ RTC_TR_HU

#define RTC_TR_HU RTC_TR_HU_Msk

◆ RTC_TR_HU_0

#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos)

0x00010000

◆ RTC_TR_HU_1

#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos)

0x00020000

◆ RTC_TR_HU_2

#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos)

0x00040000

◆ RTC_TR_HU_3

#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos)

0x00080000

◆ RTC_TR_HU_Msk

#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos)

0x000F0000

◆ RTC_TR_HU_Pos

#define RTC_TR_HU_Pos (16U)

◆ RTC_TR_MNT

#define RTC_TR_MNT RTC_TR_MNT_Msk

◆ RTC_TR_MNT_0

#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos)

0x00001000

◆ RTC_TR_MNT_1

#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos)

0x00002000

◆ RTC_TR_MNT_2

#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos)

0x00004000

◆ RTC_TR_MNT_Msk

#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos)

0x00007000

◆ RTC_TR_MNT_Pos

#define RTC_TR_MNT_Pos (12U)

◆ RTC_TR_MNU

#define RTC_TR_MNU RTC_TR_MNU_Msk

◆ RTC_TR_MNU_0

#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos)

0x00000100

◆ RTC_TR_MNU_1

#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos)

0x00000200

◆ RTC_TR_MNU_2

#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos)

0x00000400

◆ RTC_TR_MNU_3

#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos)

0x00000800

◆ RTC_TR_MNU_Msk

#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos)

0x00000F00

◆ RTC_TR_MNU_Pos

#define RTC_TR_MNU_Pos (8U)

◆ RTC_TR_PM

#define RTC_TR_PM RTC_TR_PM_Msk

◆ RTC_TR_PM_Msk

#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos)

0x00400000

◆ RTC_TR_PM_Pos

#define RTC_TR_PM_Pos (22U)

◆ RTC_TR_ST

#define RTC_TR_ST RTC_TR_ST_Msk

◆ RTC_TR_ST_0

#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos)

0x00000010

◆ RTC_TR_ST_1

#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos)

0x00000020

◆ RTC_TR_ST_2

#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos)

0x00000040

◆ RTC_TR_ST_Msk

#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos)

0x00000070

◆ RTC_TR_ST_Pos

#define RTC_TR_ST_Pos (4U)

◆ RTC_TR_SU

#define RTC_TR_SU RTC_TR_SU_Msk

◆ RTC_TR_SU_0

#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos)

0x00000001

◆ RTC_TR_SU_1

#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos)

0x00000002

◆ RTC_TR_SU_2

#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos)

0x00000004

◆ RTC_TR_SU_3

#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos)

0x00000008

◆ RTC_TR_SU_Msk

#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos)

0x0000000F

◆ RTC_TR_SU_Pos

#define RTC_TR_SU_Pos (0U)

◆ RTC_TSDR_DT

#define RTC_TSDR_DT RTC_TSDR_DT_Msk

◆ RTC_TSDR_DT_0

#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos)

0x00000010

◆ RTC_TSDR_DT_1

#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos)

0x00000020

◆ RTC_TSDR_DT_Msk

#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos)

0x00000030

◆ RTC_TSDR_DT_Pos

#define RTC_TSDR_DT_Pos (4U)

◆ RTC_TSDR_DU

#define RTC_TSDR_DU RTC_TSDR_DU_Msk

◆ RTC_TSDR_DU_0

#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos)

0x00000001

◆ RTC_TSDR_DU_1

#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos)

0x00000002

◆ RTC_TSDR_DU_2

#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos)

0x00000004

◆ RTC_TSDR_DU_3

#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos)

0x00000008

◆ RTC_TSDR_DU_Msk

#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos)

0x0000000F

◆ RTC_TSDR_DU_Pos

#define RTC_TSDR_DU_Pos (0U)

◆ RTC_TSDR_MT

#define RTC_TSDR_MT RTC_TSDR_MT_Msk

◆ RTC_TSDR_MT_Msk

#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos)

0x00001000

◆ RTC_TSDR_MT_Pos

#define RTC_TSDR_MT_Pos (12U)

◆ RTC_TSDR_MU

#define RTC_TSDR_MU RTC_TSDR_MU_Msk

◆ RTC_TSDR_MU_0

#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos)

0x00000100

◆ RTC_TSDR_MU_1

#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos)

0x00000200

◆ RTC_TSDR_MU_2

#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos)

0x00000400

◆ RTC_TSDR_MU_3

#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos)

0x00000800

◆ RTC_TSDR_MU_Msk

#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos)

0x00000F00

◆ RTC_TSDR_MU_Pos

#define RTC_TSDR_MU_Pos (8U)

◆ RTC_TSDR_WDU

#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk

Week day units >

◆ RTC_TSDR_WDU_0

#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos)

0x00002000

◆ RTC_TSDR_WDU_1

#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos)

0x00004000

◆ RTC_TSDR_WDU_2

#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos)

0x00008000

◆ RTC_TSDR_WDU_Msk

#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos)

0x0000E000

◆ RTC_TSDR_WDU_Pos

#define RTC_TSDR_WDU_Pos (13U)

◆ RTC_TSSSR_SS

#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk

Sub second value >

◆ RTC_TSSSR_SS_Msk

#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos)

0x0000FFFF

◆ RTC_TSSSR_SS_Pos

#define RTC_TSSSR_SS_Pos (0U)

◆ RTC_TSTR_HT

#define RTC_TSTR_HT RTC_TSTR_HT_Msk

◆ RTC_TSTR_HT_0

#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos)

0x00100000

◆ RTC_TSTR_HT_1

#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos)

0x00200000

◆ RTC_TSTR_HT_Msk

#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos)

0x00300000

◆ RTC_TSTR_HT_Pos

#define RTC_TSTR_HT_Pos (20U)

◆ RTC_TSTR_HU

#define RTC_TSTR_HU RTC_TSTR_HU_Msk

◆ RTC_TSTR_HU_0

#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos)

0x00010000

◆ RTC_TSTR_HU_1

#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos)

0x00020000

◆ RTC_TSTR_HU_2

#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos)

0x00040000

◆ RTC_TSTR_HU_3

#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos)

0x00080000

◆ RTC_TSTR_HU_Msk

#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos)

0x000F0000

◆ RTC_TSTR_HU_Pos

#define RTC_TSTR_HU_Pos (16U)

◆ RTC_TSTR_MNT

#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk

◆ RTC_TSTR_MNT_0

#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos)

0x00001000

◆ RTC_TSTR_MNT_1

#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos)

0x00002000

◆ RTC_TSTR_MNT_2

#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos)

0x00004000

◆ RTC_TSTR_MNT_Msk

#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos)

0x00007000

◆ RTC_TSTR_MNT_Pos

#define RTC_TSTR_MNT_Pos (12U)

◆ RTC_TSTR_MNU

#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk

◆ RTC_TSTR_MNU_0

#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos)

0x00000100

◆ RTC_TSTR_MNU_1

#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos)

0x00000200

◆ RTC_TSTR_MNU_2

#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos)

0x00000400

◆ RTC_TSTR_MNU_3

#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos)

0x00000800

◆ RTC_TSTR_MNU_Msk

#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos)

0x00000F00

◆ RTC_TSTR_MNU_Pos

#define RTC_TSTR_MNU_Pos (8U)

◆ RTC_TSTR_PM

#define RTC_TSTR_PM RTC_TSTR_PM_Msk

AM-PM notation >

◆ RTC_TSTR_PM_Msk

#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos)

0x00400000

◆ RTC_TSTR_PM_Pos

#define RTC_TSTR_PM_Pos (22U)

◆ RTC_TSTR_ST

#define RTC_TSTR_ST RTC_TSTR_ST_Msk

◆ RTC_TSTR_ST_0

#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos)

0x00000010

◆ RTC_TSTR_ST_1

#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos)

0x00000020

◆ RTC_TSTR_ST_2

#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos)

0x00000040

◆ RTC_TSTR_ST_Msk

#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos)

0x00000070

◆ RTC_TSTR_ST_Pos

#define RTC_TSTR_ST_Pos (4U)

◆ RTC_TSTR_SU

#define RTC_TSTR_SU RTC_TSTR_SU_Msk

◆ RTC_TSTR_SU_0

#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos)

0x00000001

◆ RTC_TSTR_SU_1

#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos)

0x00000002

◆ RTC_TSTR_SU_2

#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos)

0x00000004

◆ RTC_TSTR_SU_3

#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos)

0x00000008

◆ RTC_TSTR_SU_Msk

#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos)

0x0000000F

◆ RTC_TSTR_SU_Pos

#define RTC_TSTR_SU_Pos (0U)

◆ RTC_WAKEUP_SUPPORT

#define RTC_WAKEUP_SUPPORT

◆ RTC_WPR_KEY

#define RTC_WPR_KEY RTC_WPR_KEY_Msk

◆ RTC_WPR_KEY_Msk

#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos)

0x000000FF

◆ RTC_WPR_KEY_Pos

#define RTC_WPR_KEY_Pos (0U)

◆ RTC_WUTR_WUT

#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk

Wakeup auto-reload value bits >

◆ RTC_WUTR_WUT_Msk

#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos)

0x0000FFFF

◆ RTC_WUTR_WUT_Pos

#define RTC_WUTR_WUT_Pos (0U)

◆ SPI_CR1_BIDIMODE

#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk

Bidirectional data mode enable

◆ SPI_CR1_BIDIMODE_Msk

#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos)

0x00008000

◆ SPI_CR1_BIDIMODE_Pos

#define SPI_CR1_BIDIMODE_Pos (15U)

◆ SPI_CR1_BIDIOE

#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk

Output enable in bidirectional mode

◆ SPI_CR1_BIDIOE_Msk

#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos)

0x00004000

◆ SPI_CR1_BIDIOE_Pos

#define SPI_CR1_BIDIOE_Pos (14U)

◆ SPI_CR1_BR

#define SPI_CR1_BR SPI_CR1_BR_Msk

BR[2:0] bits (Baud Rate Control)

◆ SPI_CR1_BR_0

#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos)

0x00000008

◆ SPI_CR1_BR_1

#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos)

0x00000010

◆ SPI_CR1_BR_2

#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos)

0x00000020

◆ SPI_CR1_BR_Msk

#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos)

0x00000038

◆ SPI_CR1_BR_Pos

#define SPI_CR1_BR_Pos (3U)

◆ SPI_CR1_CPHA

#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk

Clock Phase

◆ SPI_CR1_CPHA_Msk

#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos)

0x00000001

◆ SPI_CR1_CPHA_Pos

#define SPI_CR1_CPHA_Pos (0U)

◆ SPI_CR1_CPOL

#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk

Clock Polarity

◆ SPI_CR1_CPOL_Msk

#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos)

0x00000002

◆ SPI_CR1_CPOL_Pos

#define SPI_CR1_CPOL_Pos (1U)

◆ SPI_CR1_CRCEN

#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk

Hardware CRC calculation enable

◆ SPI_CR1_CRCEN_Msk

#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos)

0x00002000

◆ SPI_CR1_CRCEN_Pos

#define SPI_CR1_CRCEN_Pos (13U)

◆ SPI_CR1_CRCL

#define SPI_CR1_CRCL SPI_CR1_CRCL_Msk

CRC Length

◆ SPI_CR1_CRCL_Msk

#define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos)

0x00000800

◆ SPI_CR1_CRCL_Pos

#define SPI_CR1_CRCL_Pos (11U)

◆ SPI_CR1_CRCNEXT

#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk

Transmit CRC next

◆ SPI_CR1_CRCNEXT_Msk

#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos)

0x00001000

◆ SPI_CR1_CRCNEXT_Pos

#define SPI_CR1_CRCNEXT_Pos (12U)

◆ SPI_CR1_LSBFIRST

#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk

Frame Format

◆ SPI_CR1_LSBFIRST_Msk

#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos)

0x00000080

◆ SPI_CR1_LSBFIRST_Pos

#define SPI_CR1_LSBFIRST_Pos (7U)

◆ SPI_CR1_MSTR

#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk

Master Selection

◆ SPI_CR1_MSTR_Msk

#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos)

0x00000004

◆ SPI_CR1_MSTR_Pos

#define SPI_CR1_MSTR_Pos (2U)

◆ SPI_CR1_RXONLY

#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk

Receive only

◆ SPI_CR1_RXONLY_Msk

#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos)

0x00000400

◆ SPI_CR1_RXONLY_Pos

#define SPI_CR1_RXONLY_Pos (10U)

◆ SPI_CR1_SPE

#define SPI_CR1_SPE SPI_CR1_SPE_Msk

SPI Enable

◆ SPI_CR1_SPE_Msk

#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos)

0x00000040

◆ SPI_CR1_SPE_Pos

#define SPI_CR1_SPE_Pos (6U)

◆ SPI_CR1_SSI

#define SPI_CR1_SSI SPI_CR1_SSI_Msk

Internal slave select

◆ SPI_CR1_SSI_Msk

#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos)

0x00000100

◆ SPI_CR1_SSI_Pos

#define SPI_CR1_SSI_Pos (8U)

◆ SPI_CR1_SSM

#define SPI_CR1_SSM SPI_CR1_SSM_Msk

Software slave management

◆ SPI_CR1_SSM_Msk

#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos)

0x00000200

◆ SPI_CR1_SSM_Pos

#define SPI_CR1_SSM_Pos (9U)

◆ SPI_CR2_DS

#define SPI_CR2_DS SPI_CR2_DS_Msk

DS[3:0] Data Size

◆ SPI_CR2_DS_0

#define SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos)

0x00000100

◆ SPI_CR2_DS_1

#define SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos)

0x00000200

◆ SPI_CR2_DS_2

#define SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos)

0x00000400

◆ SPI_CR2_DS_3

#define SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos)

0x00000800

◆ SPI_CR2_DS_Msk

#define SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos)

0x00000F00

◆ SPI_CR2_DS_Pos

#define SPI_CR2_DS_Pos (8U)

◆ SPI_CR2_ERRIE

#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk

Error Interrupt Enable

◆ SPI_CR2_ERRIE_Msk

#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos)

0x00000020

◆ SPI_CR2_ERRIE_Pos

#define SPI_CR2_ERRIE_Pos (5U)

◆ SPI_CR2_FRF

#define SPI_CR2_FRF SPI_CR2_FRF_Msk

Frame Format Enable

◆ SPI_CR2_FRF_Msk

#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos)

0x00000010

◆ SPI_CR2_FRF_Pos

#define SPI_CR2_FRF_Pos (4U)

◆ SPI_CR2_FRXTH

#define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk

FIFO reception Threshold

◆ SPI_CR2_FRXTH_Msk

#define SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos)

0x00001000

◆ SPI_CR2_FRXTH_Pos

#define SPI_CR2_FRXTH_Pos (12U)

◆ SPI_CR2_LDMARX

#define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk

Last DMA transfer for reception

◆ SPI_CR2_LDMARX_Msk

#define SPI_CR2_LDMARX_Msk (0x1UL << SPI_CR2_LDMARX_Pos)

0x00002000

◆ SPI_CR2_LDMARX_Pos

#define SPI_CR2_LDMARX_Pos (13U)

◆ SPI_CR2_LDMATX

#define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk

Last DMA transfer for transmission

◆ SPI_CR2_LDMATX_Msk

#define SPI_CR2_LDMATX_Msk (0x1UL << SPI_CR2_LDMATX_Pos)

0x00004000

◆ SPI_CR2_LDMATX_Pos

#define SPI_CR2_LDMATX_Pos (14U)

◆ SPI_CR2_NSSP

#define SPI_CR2_NSSP SPI_CR2_NSSP_Msk

NSS pulse management Enable

◆ SPI_CR2_NSSP_Msk

#define SPI_CR2_NSSP_Msk (0x1UL << SPI_CR2_NSSP_Pos)

0x00000008

◆ SPI_CR2_NSSP_Pos

#define SPI_CR2_NSSP_Pos (3U)

◆ SPI_CR2_RXDMAEN

#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk

Rx Buffer DMA Enable

◆ SPI_CR2_RXDMAEN_Msk

#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos)

0x00000001

◆ SPI_CR2_RXDMAEN_Pos

#define SPI_CR2_RXDMAEN_Pos (0U)

◆ SPI_CR2_RXNEIE

#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk

RX buffer Not Empty Interrupt Enable

◆ SPI_CR2_RXNEIE_Msk

#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos)

0x00000040

◆ SPI_CR2_RXNEIE_Pos

#define SPI_CR2_RXNEIE_Pos (6U)

◆ SPI_CR2_SSOE

#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk

SS Output Enable

◆ SPI_CR2_SSOE_Msk

#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos)

0x00000004

◆ SPI_CR2_SSOE_Pos

#define SPI_CR2_SSOE_Pos (2U)

◆ SPI_CR2_TXDMAEN

#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk

Tx Buffer DMA Enable

◆ SPI_CR2_TXDMAEN_Msk

#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos)

0x00000002

◆ SPI_CR2_TXDMAEN_Pos

#define SPI_CR2_TXDMAEN_Pos (1U)

◆ SPI_CR2_TXEIE

#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk

Tx buffer Empty Interrupt Enable

◆ SPI_CR2_TXEIE_Msk

#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos)

0x00000080

◆ SPI_CR2_TXEIE_Pos

#define SPI_CR2_TXEIE_Pos (7U)

◆ SPI_CRCPR_CRCPOLY

#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk

CRC polynomial register

◆ SPI_CRCPR_CRCPOLY_Msk

#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)

0x0000FFFF

◆ SPI_CRCPR_CRCPOLY_Pos

#define SPI_CRCPR_CRCPOLY_Pos (0U)

◆ SPI_DR_DR

#define SPI_DR_DR SPI_DR_DR_Msk

Data Register

◆ SPI_DR_DR_Msk

#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos)

0x0000FFFF

◆ SPI_DR_DR_Pos

#define SPI_DR_DR_Pos (0U)

◆ SPI_I2S_SUPPORT

#define SPI_I2S_SUPPORT

I2S support

◆ SPI_I2SCFGR_ASTRTEN

#define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk

Asynchronous start enable

◆ SPI_I2SCFGR_ASTRTEN_Msk

#define SPI_I2SCFGR_ASTRTEN_Msk (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos)

0x00001000

◆ SPI_I2SCFGR_ASTRTEN_Pos

#define SPI_I2SCFGR_ASTRTEN_Pos (12U)

◆ SPI_I2SCFGR_CHLEN

#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk

Channel length (number of bits per audio channel)

◆ SPI_I2SCFGR_CHLEN_Msk

#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos)

0x00000001

◆ SPI_I2SCFGR_CHLEN_Pos

#define SPI_I2SCFGR_CHLEN_Pos (0U)

◆ SPI_I2SCFGR_CKPOL

#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk

steady state clock polarity

◆ SPI_I2SCFGR_CKPOL_Msk

#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos)

0x00000008

◆ SPI_I2SCFGR_CKPOL_Pos

#define SPI_I2SCFGR_CKPOL_Pos (3U)

◆ SPI_I2SCFGR_DATLEN

#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk

DATLEN[1:0] bits (Data length to be transferred)

◆ SPI_I2SCFGR_DATLEN_0

#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos)

0x00000002

◆ SPI_I2SCFGR_DATLEN_1

#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos)

0x00000004

◆ SPI_I2SCFGR_DATLEN_Msk

#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos)

0x00000006

◆ SPI_I2SCFGR_DATLEN_Pos

#define SPI_I2SCFGR_DATLEN_Pos (1U)

◆ SPI_I2SCFGR_I2SCFG

#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk

I2SCFG[1:0] bits (I2S configuration mode)

◆ SPI_I2SCFGR_I2SCFG_0

#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)

0x00000100

◆ SPI_I2SCFGR_I2SCFG_1

#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)

0x00000200

◆ SPI_I2SCFGR_I2SCFG_Msk

#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)

0x00000300

◆ SPI_I2SCFGR_I2SCFG_Pos

#define SPI_I2SCFGR_I2SCFG_Pos (8U)

◆ SPI_I2SCFGR_I2SE

#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk

I2S Enable

◆ SPI_I2SCFGR_I2SE_Msk

#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos)

0x00000400

◆ SPI_I2SCFGR_I2SE_Pos

#define SPI_I2SCFGR_I2SE_Pos (10U)

◆ SPI_I2SCFGR_I2SMOD

#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk

I2S mode selection

◆ SPI_I2SCFGR_I2SMOD_Msk

#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)

0x00000800

◆ SPI_I2SCFGR_I2SMOD_Pos

#define SPI_I2SCFGR_I2SMOD_Pos (11U)

◆ SPI_I2SCFGR_I2SSTD

#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk

I2SSTD[1:0] bits (I2S standard selection)

◆ SPI_I2SCFGR_I2SSTD_0

#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)

0x00000010

◆ SPI_I2SCFGR_I2SSTD_1

#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)

0x00000020

◆ SPI_I2SCFGR_I2SSTD_Msk

#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)

0x00000030

◆ SPI_I2SCFGR_I2SSTD_Pos

#define SPI_I2SCFGR_I2SSTD_Pos (4U)

◆ SPI_I2SCFGR_PCMSYNC

#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk

PCM frame synchronization

◆ SPI_I2SCFGR_PCMSYNC_Msk

#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)

0x00000080

◆ SPI_I2SCFGR_PCMSYNC_Pos

#define SPI_I2SCFGR_PCMSYNC_Pos (7U)

◆ SPI_I2SPR_I2SDIV

#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk

I2S Linear prescaler

◆ SPI_I2SPR_I2SDIV_Msk

#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos)

0x000000FF

◆ SPI_I2SPR_I2SDIV_Pos

#define SPI_I2SPR_I2SDIV_Pos (0U)

◆ SPI_I2SPR_MCKOE

#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk

Master Clock Output Enable

◆ SPI_I2SPR_MCKOE_Msk

#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos)

0x00000200

◆ SPI_I2SPR_MCKOE_Pos

#define SPI_I2SPR_MCKOE_Pos (9U)

◆ SPI_I2SPR_ODD

#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk

Odd factor for the prescaler

◆ SPI_I2SPR_ODD_Msk

#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos)

0x00000100

◆ SPI_I2SPR_ODD_Pos

#define SPI_I2SPR_ODD_Pos (8U)

◆ SPI_RXCRCR_RXCRC

#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk

Rx CRC Register

◆ SPI_RXCRCR_RXCRC_Msk

#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)

0x0000FFFF

◆ SPI_RXCRCR_RXCRC_Pos

#define SPI_RXCRCR_RXCRC_Pos (0U)

◆ SPI_SR_BSY

#define SPI_SR_BSY SPI_SR_BSY_Msk

Busy flag

◆ SPI_SR_BSY_Msk

#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos)

0x00000080

◆ SPI_SR_BSY_Pos

#define SPI_SR_BSY_Pos (7U)

◆ SPI_SR_CHSIDE

#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk

Channel side

◆ SPI_SR_CHSIDE_Msk

#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos)

0x00000004

◆ SPI_SR_CHSIDE_Pos

#define SPI_SR_CHSIDE_Pos (2U)

◆ SPI_SR_CRCERR

#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk

CRC Error flag

◆ SPI_SR_CRCERR_Msk

#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos)

0x00000010

◆ SPI_SR_CRCERR_Pos

#define SPI_SR_CRCERR_Pos (4U)

◆ SPI_SR_FRE

#define SPI_SR_FRE SPI_SR_FRE_Msk

TI frame format error

◆ SPI_SR_FRE_Msk

#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos)

0x00000100

◆ SPI_SR_FRE_Pos

#define SPI_SR_FRE_Pos (8U)

◆ SPI_SR_FRLVL

#define SPI_SR_FRLVL SPI_SR_FRLVL_Msk

FIFO Reception Level

◆ SPI_SR_FRLVL_0

#define SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos)

0x00000200

◆ SPI_SR_FRLVL_1

#define SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos)

0x00000400

◆ SPI_SR_FRLVL_Msk

#define SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos)

0x00000600

◆ SPI_SR_FRLVL_Pos

#define SPI_SR_FRLVL_Pos (9U)

◆ SPI_SR_FTLVL

#define SPI_SR_FTLVL SPI_SR_FTLVL_Msk

FIFO Transmission Level

◆ SPI_SR_FTLVL_0

#define SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos)

0x00000800

◆ SPI_SR_FTLVL_1

#define SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos)

0x00001000

◆ SPI_SR_FTLVL_Msk

#define SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos)

0x00001800

◆ SPI_SR_FTLVL_Pos

#define SPI_SR_FTLVL_Pos (11U)

◆ SPI_SR_MODF

#define SPI_SR_MODF SPI_SR_MODF_Msk

Mode fault

◆ SPI_SR_MODF_Msk

#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos)

0x00000020

◆ SPI_SR_MODF_Pos

#define SPI_SR_MODF_Pos (5U)

◆ SPI_SR_OVR

#define SPI_SR_OVR SPI_SR_OVR_Msk

Overrun flag

◆ SPI_SR_OVR_Msk

#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos)

0x00000040

◆ SPI_SR_OVR_Pos

#define SPI_SR_OVR_Pos (6U)

◆ SPI_SR_RXNE

#define SPI_SR_RXNE SPI_SR_RXNE_Msk

Receive buffer Not Empty

◆ SPI_SR_RXNE_Msk

#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos)

0x00000001

◆ SPI_SR_RXNE_Pos

#define SPI_SR_RXNE_Pos (0U)

◆ SPI_SR_TXE

#define SPI_SR_TXE SPI_SR_TXE_Msk

Transmit buffer Empty

◆ SPI_SR_TXE_Msk

#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos)

0x00000002

◆ SPI_SR_TXE_Pos

#define SPI_SR_TXE_Pos (1U)

◆ SPI_SR_UDR

#define SPI_SR_UDR SPI_SR_UDR_Msk

Underrun flag

◆ SPI_SR_UDR_Msk

#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos)

0x00000008

◆ SPI_SR_UDR_Pos

#define SPI_SR_UDR_Pos (3U)

◆ SPI_TXCRCR_TXCRC

#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk

Tx CRC Register

◆ SPI_TXCRCR_TXCRC_Msk

#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)

0x0000FFFF

◆ SPI_TXCRCR_TXCRC_Pos

#define SPI_TXCRCR_TXCRC_Pos (0U)

◆ SYSCFG_CDEN_SUPPORT

#define SYSCFG_CDEN_SUPPORT

◆ SYSCFG_CFGR1_BOOSTEN

#define SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN_Msk

I/O analog switch voltage booster enable

◆ SYSCFG_CFGR1_BOOSTEN_Msk

#define SYSCFG_CFGR1_BOOSTEN_Msk (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos)

0x00000100

◆ SYSCFG_CFGR1_BOOSTEN_Pos

#define SYSCFG_CFGR1_BOOSTEN_Pos (8U)

◆ SYSCFG_CFGR1_I2C1_FMP

#define SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk

Enable Fast Mode Plus on PB10, PB11, PF6 and PF7

◆ SYSCFG_CFGR1_I2C1_FMP_Msk

#define SYSCFG_CFGR1_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos)

0x00100000

◆ SYSCFG_CFGR1_I2C1_FMP_Pos

#define SYSCFG_CFGR1_I2C1_FMP_Pos (20U)

◆ SYSCFG_CFGR1_I2C2_FMP

#define SYSCFG_CFGR1_I2C2_FMP SYSCFG_CFGR1_I2C2_FMP_Msk

Enable I2C2 Fast mode plus

◆ SYSCFG_CFGR1_I2C2_FMP_Msk

#define SYSCFG_CFGR1_I2C2_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C2_FMP_Pos)

0x00200000

◆ SYSCFG_CFGR1_I2C2_FMP_Pos

#define SYSCFG_CFGR1_I2C2_FMP_Pos (21U)

◆ SYSCFG_CFGR1_I2C_PA10_FMP

#define SYSCFG_CFGR1_I2C_PA10_FMP SYSCFG_CFGR1_I2C_PA10_FMP_Msk

Enable Fast Mode Plus on PA10

◆ SYSCFG_CFGR1_I2C_PA10_FMP_Msk

#define SYSCFG_CFGR1_I2C_PA10_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PA10_FMP_Pos)

0x00800000

◆ SYSCFG_CFGR1_I2C_PA10_FMP_Pos

#define SYSCFG_CFGR1_I2C_PA10_FMP_Pos (23U)

◆ SYSCFG_CFGR1_I2C_PA9_FMP

#define SYSCFG_CFGR1_I2C_PA9_FMP SYSCFG_CFGR1_I2C_PA9_FMP_Msk

Enable Fast Mode Plus on PA9

◆ SYSCFG_CFGR1_I2C_PA9_FMP_Msk

#define SYSCFG_CFGR1_I2C_PA9_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PA9_FMP_Pos)

0x00400000

◆ SYSCFG_CFGR1_I2C_PA9_FMP_Pos

#define SYSCFG_CFGR1_I2C_PA9_FMP_Pos (22U)

◆ SYSCFG_CFGR1_I2C_PB6_FMP

#define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk

I2C PB6 Fast mode plus

◆ SYSCFG_CFGR1_I2C_PB6_FMP_Msk

#define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos)

0x00010000

◆ SYSCFG_CFGR1_I2C_PB6_FMP_Pos

#define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U)

◆ SYSCFG_CFGR1_I2C_PB7_FMP

#define SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk

I2C PB7 Fast mode plus

◆ SYSCFG_CFGR1_I2C_PB7_FMP_Msk

#define SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos)

0x00020000

◆ SYSCFG_CFGR1_I2C_PB7_FMP_Pos

#define SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U)

◆ SYSCFG_CFGR1_I2C_PB8_FMP

#define SYSCFG_CFGR1_I2C_PB8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk

I2C PB8 Fast mode plus

◆ SYSCFG_CFGR1_I2C_PB8_FMP_Msk

#define SYSCFG_CFGR1_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos)

0x00040000

◆ SYSCFG_CFGR1_I2C_PB8_FMP_Pos

#define SYSCFG_CFGR1_I2C_PB8_FMP_Pos (18U)

◆ SYSCFG_CFGR1_I2C_PB9_FMP

#define SYSCFG_CFGR1_I2C_PB9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk

I2C PB9 Fast mode plus

◆ SYSCFG_CFGR1_I2C_PB9_FMP_Msk

#define SYSCFG_CFGR1_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos)

0x00080000

◆ SYSCFG_CFGR1_I2C_PB9_FMP_Pos

#define SYSCFG_CFGR1_I2C_PB9_FMP_Pos (19U)

◆ SYSCFG_CFGR1_IR_MOD

#define SYSCFG_CFGR1_IR_MOD SYSCFG_CFGR1_IR_MOD_Msk

IRDA Modulation Envelope signal source selection

◆ SYSCFG_CFGR1_IR_MOD_0

#define SYSCFG_CFGR1_IR_MOD_0 (0x1UL << SYSCFG_CFGR1_IR_MOD_Pos)

0x00000040

◆ SYSCFG_CFGR1_IR_MOD_1

#define SYSCFG_CFGR1_IR_MOD_1 (0x2UL << SYSCFG_CFGR1_IR_MOD_Pos)

0x00000080

◆ SYSCFG_CFGR1_IR_MOD_Msk

#define SYSCFG_CFGR1_IR_MOD_Msk (0x3UL << SYSCFG_CFGR1_IR_MOD_Pos)

0x000000C0

◆ SYSCFG_CFGR1_IR_MOD_Pos

#define SYSCFG_CFGR1_IR_MOD_Pos (6U)

◆ SYSCFG_CFGR1_IR_POL

#define SYSCFG_CFGR1_IR_POL SYSCFG_CFGR1_IR_POL_Msk

IROut Polarity Selection

◆ SYSCFG_CFGR1_IR_POL_Msk

#define SYSCFG_CFGR1_IR_POL_Msk (0x1UL << SYSCFG_CFGR1_IR_POL_Pos)

0x00000020

◆ SYSCFG_CFGR1_IR_POL_Pos

#define SYSCFG_CFGR1_IR_POL_Pos (5U)

◆ SYSCFG_CFGR1_MEM_MODE

#define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk

SYSCFG_Memory Remap Config

◆ SYSCFG_CFGR1_MEM_MODE_0

#define SYSCFG_CFGR1_MEM_MODE_0 (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos)

0x00000001

◆ SYSCFG_CFGR1_MEM_MODE_1

#define SYSCFG_CFGR1_MEM_MODE_1 (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos)

0x00000002

◆ SYSCFG_CFGR1_MEM_MODE_Msk

#define SYSCFG_CFGR1_MEM_MODE_Msk (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos)

0x00000003

◆ SYSCFG_CFGR1_MEM_MODE_Pos

#define SYSCFG_CFGR1_MEM_MODE_Pos (0U)

◆ SYSCFG_CFGR1_PA11_RMP

#define SYSCFG_CFGR1_PA11_RMP SYSCFG_CFGR1_PA11_RMP_Msk

PA11 Remap

◆ SYSCFG_CFGR1_PA11_RMP_Msk

#define SYSCFG_CFGR1_PA11_RMP_Msk (0x1UL << SYSCFG_CFGR1_PA11_RMP_Pos)

0x00000008

◆ SYSCFG_CFGR1_PA11_RMP_Pos

#define SYSCFG_CFGR1_PA11_RMP_Pos (3U)

◆ SYSCFG_CFGR1_PA12_RMP

#define SYSCFG_CFGR1_PA12_RMP SYSCFG_CFGR1_PA12_RMP_Msk

PA12 Remap

◆ SYSCFG_CFGR1_PA12_RMP_Msk

#define SYSCFG_CFGR1_PA12_RMP_Msk (0x1UL << SYSCFG_CFGR1_PA12_RMP_Pos)

0x00000010

◆ SYSCFG_CFGR1_PA12_RMP_Pos

#define SYSCFG_CFGR1_PA12_RMP_Pos (4U)

◆ SYSCFG_CFGR2_CLL

#define SYSCFG_CFGR2_CLL SYSCFG_CFGR2_CLL_Msk

Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1

◆ SYSCFG_CFGR2_CLL_Msk

#define SYSCFG_CFGR2_CLL_Msk (0x1UL << SYSCFG_CFGR2_CLL_Pos)

0x00000001

◆ SYSCFG_CFGR2_CLL_Pos

#define SYSCFG_CFGR2_CLL_Pos (0U)

◆ SYSCFG_CFGR2_ECCL

#define SYSCFG_CFGR2_ECCL SYSCFG_CFGR2_ECCL_Msk

ECCL

◆ SYSCFG_CFGR2_ECCL_Msk

#define SYSCFG_CFGR2_ECCL_Msk (0x1UL << SYSCFG_CFGR2_ECCL_Pos)

0x00000008

◆ SYSCFG_CFGR2_ECCL_Pos

#define SYSCFG_CFGR2_ECCL_Pos (3U)

◆ SYSCFG_CFGR2_PA13_CDEN

#define SYSCFG_CFGR2_PA13_CDEN SYSCFG_CFGR2_PA13_CDEN_Msk

PA[13] Clamping Diode Enable

◆ SYSCFG_CFGR2_PA13_CDEN_Msk

#define SYSCFG_CFGR2_PA13_CDEN_Msk (0x1UL << SYSCFG_CFGR2_PA13_CDEN_Pos) /* 0x00100000 */

◆ SYSCFG_CFGR2_PA13_CDEN_Pos

#define SYSCFG_CFGR2_PA13_CDEN_Pos (20U)

◆ SYSCFG_CFGR2_PA1_CDEN

#define SYSCFG_CFGR2_PA1_CDEN SYSCFG_CFGR2_PA1_CDEN_Msk

PA[1] Clamping Diode Enable

◆ SYSCFG_CFGR2_PA1_CDEN_Msk

#define SYSCFG_CFGR2_PA1_CDEN_Msk (0x1UL << SYSCFG_CFGR2_PA1_CDEN_Pos) /* 0x00010000 */

◆ SYSCFG_CFGR2_PA1_CDEN_Pos

#define SYSCFG_CFGR2_PA1_CDEN_Pos (16U)

◆ SYSCFG_CFGR2_PA3_CDEN

#define SYSCFG_CFGR2_PA3_CDEN SYSCFG_CFGR2_PA3_CDEN_Msk

PA[3] Clamping Diode Enable

◆ SYSCFG_CFGR2_PA3_CDEN_Msk

#define SYSCFG_CFGR2_PA3_CDEN_Msk (0x1UL << SYSCFG_CFGR2_PA3_CDEN_Pos) /* 0x00020000 */

◆ SYSCFG_CFGR2_PA3_CDEN_Pos

#define SYSCFG_CFGR2_PA3_CDEN_Pos (17U)

◆ SYSCFG_CFGR2_PA5_CDEN

#define SYSCFG_CFGR2_PA5_CDEN SYSCFG_CFGR2_PA5_CDEN_Msk

PA[5] Clamping Diode Enable

◆ SYSCFG_CFGR2_PA5_CDEN_Msk

#define SYSCFG_CFGR2_PA5_CDEN_Msk (0x1UL << SYSCFG_CFGR2_PA5_CDEN_Pos) /* 0x00040000 */

◆ SYSCFG_CFGR2_PA5_CDEN_Pos

#define SYSCFG_CFGR2_PA5_CDEN_Pos (18U)

◆ SYSCFG_CFGR2_PA6_CDEN

#define SYSCFG_CFGR2_PA6_CDEN SYSCFG_CFGR2_PA6_CDEN_Msk

PA[6] Clamping Diode Enable

◆ SYSCFG_CFGR2_PA6_CDEN_Msk

#define SYSCFG_CFGR2_PA6_CDEN_Msk (0x1UL << SYSCFG_CFGR2_PA6_CDEN_Pos) /* 0x00080000 */

◆ SYSCFG_CFGR2_PA6_CDEN_Pos

#define SYSCFG_CFGR2_PA6_CDEN_Pos (19U)

◆ SYSCFG_CFGR2_PB0_CDEN

#define SYSCFG_CFGR2_PB0_CDEN SYSCFG_CFGR2_PB0_CDEN_Msk

PB[0] Clamping Diode Enable

◆ SYSCFG_CFGR2_PB0_CDEN_Msk

#define SYSCFG_CFGR2_PB0_CDEN_Msk (0x1UL << SYSCFG_CFGR2_PB0_CDEN_Pos) /* 0x00200000 */

◆ SYSCFG_CFGR2_PB0_CDEN_Pos

#define SYSCFG_CFGR2_PB0_CDEN_Pos (21U)

◆ SYSCFG_CFGR2_PB1_CDEN

#define SYSCFG_CFGR2_PB1_CDEN SYSCFG_CFGR2_PB1_CDEN_Msk

PB[1] Clamping Diode Enable

◆ SYSCFG_CFGR2_PB1_CDEN_Msk

#define SYSCFG_CFGR2_PB1_CDEN_Msk (0x1UL << SYSCFG_CFGR2_PB1_CDEN_Pos) /* 0x00400000 */

◆ SYSCFG_CFGR2_PB1_CDEN_Pos

#define SYSCFG_CFGR2_PB1_CDEN_Pos (22U)

◆ SYSCFG_CFGR2_PB2_CDEN

#define SYSCFG_CFGR2_PB2_CDEN SYSCFG_CFGR2_PB2_CDEN_Msk

PB[2] Clamping Diode Enable

◆ SYSCFG_CFGR2_PB2_CDEN_Msk

#define SYSCFG_CFGR2_PB2_CDEN_Msk (0x1UL << SYSCFG_CFGR2_PB2_CDEN_Pos) /* 0x00800000 */

◆ SYSCFG_CFGR2_PB2_CDEN_Pos

#define SYSCFG_CFGR2_PB2_CDEN_Pos (23U)

◆ SYSCFG_CFGR2_SPF

#define SYSCFG_CFGR2_SPF SYSCFG_CFGR2_SPF_Msk

SRAM Parity error flag

◆ SYSCFG_CFGR2_SPF_Msk

#define SYSCFG_CFGR2_SPF_Msk (0x1UL << SYSCFG_CFGR2_SPF_Pos)

0x00000100

◆ SYSCFG_CFGR2_SPF_Pos

#define SYSCFG_CFGR2_SPF_Pos (8U)

◆ SYSCFG_CFGR2_SPL

#define SYSCFG_CFGR2_SPL SYSCFG_CFGR2_SPL_Msk

Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1

◆ SYSCFG_CFGR2_SPL_Msk

#define SYSCFG_CFGR2_SPL_Msk (0x1UL << SYSCFG_CFGR2_SPL_Pos)

0x00000002

◆ SYSCFG_CFGR2_SPL_Pos

#define SYSCFG_CFGR2_SPL_Pos (1U)

◆ SYSCFG_CFGR2_SRAM_PE

#define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SPF

SRAM Parity error flag (define maintained for legacy purpose)

◆ SYSCFG_ITLINE0_SR_EWDG

#define SYSCFG_ITLINE0_SR_EWDG SYSCFG_ITLINE0_SR_EWDG_Msk

EWDG interrupt

◆ SYSCFG_ITLINE0_SR_EWDG_Msk

#define SYSCFG_ITLINE0_SR_EWDG_Msk (0x1UL << SYSCFG_ITLINE0_SR_EWDG_Pos)

0x00000001

◆ SYSCFG_ITLINE0_SR_EWDG_Pos

#define SYSCFG_ITLINE0_SR_EWDG_Pos (0U)

◆ SYSCFG_ITLINE10_SR_DMA1_CH2

#define SYSCFG_ITLINE10_SR_DMA1_CH2 SYSCFG_ITLINE10_SR_DMA1_CH2_Msk

DMA1 Channel 2 Interrupt

◆ SYSCFG_ITLINE10_SR_DMA1_CH2_Msk

#define SYSCFG_ITLINE10_SR_DMA1_CH2_Msk (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH2_Pos)

0x00000001

◆ SYSCFG_ITLINE10_SR_DMA1_CH2_Pos

#define SYSCFG_ITLINE10_SR_DMA1_CH2_Pos (0U)

◆ SYSCFG_ITLINE10_SR_DMA1_CH3

#define SYSCFG_ITLINE10_SR_DMA1_CH3 SYSCFG_ITLINE10_SR_DMA1_CH3_Msk

DMA2 Channel 3 Interrupt

◆ SYSCFG_ITLINE10_SR_DMA1_CH3_Msk

#define SYSCFG_ITLINE10_SR_DMA1_CH3_Msk (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH3_Pos)

0x00000002

◆ SYSCFG_ITLINE10_SR_DMA1_CH3_Pos

#define SYSCFG_ITLINE10_SR_DMA1_CH3_Pos (1U)

◆ SYSCFG_ITLINE11_SR_DMA1_CH4

#define SYSCFG_ITLINE11_SR_DMA1_CH4 SYSCFG_ITLINE11_SR_DMA1_CH4_Msk

DMA1 Channel 4 Interrupt

◆ SYSCFG_ITLINE11_SR_DMA1_CH4_Msk

#define SYSCFG_ITLINE11_SR_DMA1_CH4_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH4_Pos)

0x00000002

◆ SYSCFG_ITLINE11_SR_DMA1_CH4_Pos

#define SYSCFG_ITLINE11_SR_DMA1_CH4_Pos (1U)

◆ SYSCFG_ITLINE11_SR_DMA1_CH5

#define SYSCFG_ITLINE11_SR_DMA1_CH5 SYSCFG_ITLINE11_SR_DMA1_CH5_Msk

DMA1 Channel 5 Interrupt

◆ SYSCFG_ITLINE11_SR_DMA1_CH5_Msk

#define SYSCFG_ITLINE11_SR_DMA1_CH5_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH5_Pos)

0x00000004

◆ SYSCFG_ITLINE11_SR_DMA1_CH5_Pos

#define SYSCFG_ITLINE11_SR_DMA1_CH5_Pos (2U)

◆ SYSCFG_ITLINE11_SR_DMAMUX1

#define SYSCFG_ITLINE11_SR_DMAMUX1 SYSCFG_ITLINE11_SR_DMAMUX1_Msk

DMAMUX Interrupt

◆ SYSCFG_ITLINE11_SR_DMAMUX1_Msk

#define SYSCFG_ITLINE11_SR_DMAMUX1_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMAMUX1_Pos)

0x00000001

◆ SYSCFG_ITLINE11_SR_DMAMUX1_Pos

#define SYSCFG_ITLINE11_SR_DMAMUX1_Pos (0U)

◆ SYSCFG_ITLINE12_SR_ADC

#define SYSCFG_ITLINE12_SR_ADC SYSCFG_ITLINE12_SR_ADC_Msk

ADC Interrupt

◆ SYSCFG_ITLINE12_SR_ADC_Msk

#define SYSCFG_ITLINE12_SR_ADC_Msk (0x1UL << SYSCFG_ITLINE12_SR_ADC_Pos)

0x00000001

◆ SYSCFG_ITLINE12_SR_ADC_Pos

#define SYSCFG_ITLINE12_SR_ADC_Pos (0U)

◆ SYSCFG_ITLINE13_SR_TIM1_BRK

#define SYSCFG_ITLINE13_SR_TIM1_BRK SYSCFG_ITLINE13_SR_TIM1_BRK_Msk

TIM1 BRK Interrupt

◆ SYSCFG_ITLINE13_SR_TIM1_BRK_Msk

#define SYSCFG_ITLINE13_SR_TIM1_BRK_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_BRK_Pos)

0x00000008

◆ SYSCFG_ITLINE13_SR_TIM1_BRK_Pos

#define SYSCFG_ITLINE13_SR_TIM1_BRK_Pos (3U)

◆ SYSCFG_ITLINE13_SR_TIM1_CCU

#define SYSCFG_ITLINE13_SR_TIM1_CCU SYSCFG_ITLINE13_SR_TIM1_CCU_Msk

TIM1 CCU Interrupt

◆ SYSCFG_ITLINE13_SR_TIM1_CCU_Msk

#define SYSCFG_ITLINE13_SR_TIM1_CCU_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_CCU_Pos)

0x00000001

◆ SYSCFG_ITLINE13_SR_TIM1_CCU_Pos

#define SYSCFG_ITLINE13_SR_TIM1_CCU_Pos (0U)

◆ SYSCFG_ITLINE13_SR_TIM1_TRG

#define SYSCFG_ITLINE13_SR_TIM1_TRG SYSCFG_ITLINE13_SR_TIM1_TRG_Msk

TIM1 TRG Interrupt

◆ SYSCFG_ITLINE13_SR_TIM1_TRG_Msk

#define SYSCFG_ITLINE13_SR_TIM1_TRG_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_TRG_Pos)

0x00000002

◆ SYSCFG_ITLINE13_SR_TIM1_TRG_Pos

#define SYSCFG_ITLINE13_SR_TIM1_TRG_Pos (1U)

◆ SYSCFG_ITLINE13_SR_TIM1_UPD

#define SYSCFG_ITLINE13_SR_TIM1_UPD SYSCFG_ITLINE13_SR_TIM1_UPD_Msk

TIM1 UPD Interrupt

◆ SYSCFG_ITLINE13_SR_TIM1_UPD_Msk

#define SYSCFG_ITLINE13_SR_TIM1_UPD_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_UPD_Pos)

0x00000004

◆ SYSCFG_ITLINE13_SR_TIM1_UPD_Pos

#define SYSCFG_ITLINE13_SR_TIM1_UPD_Pos (2U)

◆ SYSCFG_ITLINE14_SR_TIM1_CC

#define SYSCFG_ITLINE14_SR_TIM1_CC SYSCFG_ITLINE14_SR_TIM1_CC_Msk

TIM1 CC Interrupt

◆ SYSCFG_ITLINE14_SR_TIM1_CC_Msk

#define SYSCFG_ITLINE14_SR_TIM1_CC_Msk (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC_Pos)

0x00000001

◆ SYSCFG_ITLINE14_SR_TIM1_CC_Pos

#define SYSCFG_ITLINE14_SR_TIM1_CC_Pos (0U)

◆ SYSCFG_ITLINE16_SR_TIM3_GLB

#define SYSCFG_ITLINE16_SR_TIM3_GLB SYSCFG_ITLINE16_SR_TIM3_GLB_Msk

TIM3 GLB Interrupt

◆ SYSCFG_ITLINE16_SR_TIM3_GLB_Msk

#define SYSCFG_ITLINE16_SR_TIM3_GLB_Msk (0x1UL << SYSCFG_ITLINE16_SR_TIM3_GLB_Pos)

0x00000001

◆ SYSCFG_ITLINE16_SR_TIM3_GLB_Pos

#define SYSCFG_ITLINE16_SR_TIM3_GLB_Pos (0U)

◆ SYSCFG_ITLINE19_SR_TIM14_GLB

#define SYSCFG_ITLINE19_SR_TIM14_GLB SYSCFG_ITLINE19_SR_TIM14_GLB_Msk

TIM14 GLB Interrupt

◆ SYSCFG_ITLINE19_SR_TIM14_GLB_Msk

#define SYSCFG_ITLINE19_SR_TIM14_GLB_Msk (0x1UL << SYSCFG_ITLINE19_SR_TIM14_GLB_Pos)

0x00000001

◆ SYSCFG_ITLINE19_SR_TIM14_GLB_Pos

#define SYSCFG_ITLINE19_SR_TIM14_GLB_Pos (0U)

◆ SYSCFG_ITLINE21_SR_TIM16_GLB

#define SYSCFG_ITLINE21_SR_TIM16_GLB SYSCFG_ITLINE21_SR_TIM16_GLB_Msk

TIM16 GLB Interrupt

◆ SYSCFG_ITLINE21_SR_TIM16_GLB_Msk

#define SYSCFG_ITLINE21_SR_TIM16_GLB_Msk (0x1UL << SYSCFG_ITLINE21_SR_TIM16_GLB_Pos)

0x00000001

◆ SYSCFG_ITLINE21_SR_TIM16_GLB_Pos

#define SYSCFG_ITLINE21_SR_TIM16_GLB_Pos (0U)

◆ SYSCFG_ITLINE22_SR_TIM17_GLB

#define SYSCFG_ITLINE22_SR_TIM17_GLB SYSCFG_ITLINE22_SR_TIM17_GLB_Msk

TIM17 GLB Interrupt

◆ SYSCFG_ITLINE22_SR_TIM17_GLB_Msk

#define SYSCFG_ITLINE22_SR_TIM17_GLB_Msk (0x1UL << SYSCFG_ITLINE22_SR_TIM17_GLB_Pos)

0x00000001

◆ SYSCFG_ITLINE22_SR_TIM17_GLB_Pos

#define SYSCFG_ITLINE22_SR_TIM17_GLB_Pos (0U)

◆ SYSCFG_ITLINE23_SR_I2C1_GLB

#define SYSCFG_ITLINE23_SR_I2C1_GLB SYSCFG_ITLINE23_SR_I2C1_GLB_Msk

I2C1 GLB Interrupt -> exti[23]

◆ SYSCFG_ITLINE23_SR_I2C1_GLB_Msk

#define SYSCFG_ITLINE23_SR_I2C1_GLB_Msk (0x1UL << SYSCFG_ITLINE23_SR_I2C1_GLB_Pos)

0x00000001

◆ SYSCFG_ITLINE23_SR_I2C1_GLB_Pos

#define SYSCFG_ITLINE23_SR_I2C1_GLB_Pos (0U)

◆ SYSCFG_ITLINE24_SR_I2C2_GLB

#define SYSCFG_ITLINE24_SR_I2C2_GLB SYSCFG_ITLINE24_SR_I2C2_GLB_Msk

I2C2 GLB Interrupt -> exti[22]

◆ SYSCFG_ITLINE24_SR_I2C2_GLB_Msk

#define SYSCFG_ITLINE24_SR_I2C2_GLB_Msk (0x1UL << SYSCFG_ITLINE24_SR_I2C2_GLB_Pos)

0x00000001

◆ SYSCFG_ITLINE24_SR_I2C2_GLB_Pos

#define SYSCFG_ITLINE24_SR_I2C2_GLB_Pos (0U)

◆ SYSCFG_ITLINE25_SR_SPI1

#define SYSCFG_ITLINE25_SR_SPI1 SYSCFG_ITLINE25_SR_SPI1_Msk

SPI1 Interrupt

◆ SYSCFG_ITLINE25_SR_SPI1_Msk

#define SYSCFG_ITLINE25_SR_SPI1_Msk (0x1UL << SYSCFG_ITLINE25_SR_SPI1_Pos)

0x00000001

◆ SYSCFG_ITLINE25_SR_SPI1_Pos

#define SYSCFG_ITLINE25_SR_SPI1_Pos (0U)

◆ SYSCFG_ITLINE26_SR_SPI2

#define SYSCFG_ITLINE26_SR_SPI2 SYSCFG_ITLINE26_SR_SPI2_Msk

SPI2 Interrupt

◆ SYSCFG_ITLINE26_SR_SPI2_Msk

#define SYSCFG_ITLINE26_SR_SPI2_Msk (0x1UL << SYSCFG_ITLINE26_SR_SPI2_Pos)

0x00000001

◆ SYSCFG_ITLINE26_SR_SPI2_Pos

#define SYSCFG_ITLINE26_SR_SPI2_Pos (0U)

◆ SYSCFG_ITLINE27_SR_USART1_GLB

#define SYSCFG_ITLINE27_SR_USART1_GLB SYSCFG_ITLINE27_SR_USART1_GLB_Msk

USART1 GLB Interrupt -> exti[25]

◆ SYSCFG_ITLINE27_SR_USART1_GLB_Msk

#define SYSCFG_ITLINE27_SR_USART1_GLB_Msk (0x1UL << SYSCFG_ITLINE27_SR_USART1_GLB_Pos)

0x00000001

◆ SYSCFG_ITLINE27_SR_USART1_GLB_Pos

#define SYSCFG_ITLINE27_SR_USART1_GLB_Pos (0U)

◆ SYSCFG_ITLINE28_SR_USART2_GLB

#define SYSCFG_ITLINE28_SR_USART2_GLB SYSCFG_ITLINE28_SR_USART2_GLB_Msk

USART2 GLB Interrupt -> exti[26]

◆ SYSCFG_ITLINE28_SR_USART2_GLB_Msk

#define SYSCFG_ITLINE28_SR_USART2_GLB_Msk (0x1UL << SYSCFG_ITLINE28_SR_USART2_GLB_Pos)

0x00000001

◆ SYSCFG_ITLINE28_SR_USART2_GLB_Pos

#define SYSCFG_ITLINE28_SR_USART2_GLB_Pos (0U)

◆ SYSCFG_ITLINE2_SR_RTC

#define SYSCFG_ITLINE2_SR_RTC SYSCFG_ITLINE2_SR_RTC_Msk

RTC -> exti[19] interrupt ....

◆ SYSCFG_ITLINE2_SR_RTC_Msk

#define SYSCFG_ITLINE2_SR_RTC_Msk (0x1UL << SYSCFG_ITLINE2_SR_RTC_Pos)

0x00000002

◆ SYSCFG_ITLINE2_SR_RTC_Pos

#define SYSCFG_ITLINE2_SR_RTC_Pos (1U)

◆ SYSCFG_ITLINE2_SR_TAMPER

#define SYSCFG_ITLINE2_SR_TAMPER SYSCFG_ITLINE2_SR_TAMPER_Msk

TAMPER -> exti[21] interrupt

◆ SYSCFG_ITLINE2_SR_TAMPER_Msk

#define SYSCFG_ITLINE2_SR_TAMPER_Msk (0x1UL << SYSCFG_ITLINE2_SR_TAMPER_Pos)

0x00000001

◆ SYSCFG_ITLINE2_SR_TAMPER_Pos

#define SYSCFG_ITLINE2_SR_TAMPER_Pos (0U)

◆ SYSCFG_ITLINE3_SR_FLASH_ECC

#define SYSCFG_ITLINE3_SR_FLASH_ECC SYSCFG_ITLINE3_SR_FLASH_ECC_Msk

Flash ITF ECC interrupt

◆ SYSCFG_ITLINE3_SR_FLASH_ECC_Msk

#define SYSCFG_ITLINE3_SR_FLASH_ECC_Msk (0x1UL << SYSCFG_ITLINE3_SR_FLASH_ECC_Pos)

0x00000001

◆ SYSCFG_ITLINE3_SR_FLASH_ECC_Pos

#define SYSCFG_ITLINE3_SR_FLASH_ECC_Pos (0U)

◆ SYSCFG_ITLINE3_SR_FLASH_ITF

#define SYSCFG_ITLINE3_SR_FLASH_ITF SYSCFG_ITLINE3_SR_FLASH_ITF_Msk

FLASH ITF interrupt

◆ SYSCFG_ITLINE3_SR_FLASH_ITF_Msk

#define SYSCFG_ITLINE3_SR_FLASH_ITF_Msk (0x1UL << SYSCFG_ITLINE3_SR_FLASH_ITF_Pos)

0x00000002

◆ SYSCFG_ITLINE3_SR_FLASH_ITF_Pos

#define SYSCFG_ITLINE3_SR_FLASH_ITF_Pos (1U)

◆ SYSCFG_ITLINE4_SR_CLK_CTRL

#define SYSCFG_ITLINE4_SR_CLK_CTRL SYSCFG_ITLINE4_SR_CLK_CTRL_Msk

RCC interrupt

◆ SYSCFG_ITLINE4_SR_CLK_CTRL_Msk

#define SYSCFG_ITLINE4_SR_CLK_CTRL_Msk (0x1UL << SYSCFG_ITLINE4_SR_CLK_CTRL_Pos)

0x00000001

◆ SYSCFG_ITLINE4_SR_CLK_CTRL_Pos

#define SYSCFG_ITLINE4_SR_CLK_CTRL_Pos (0U)

◆ SYSCFG_ITLINE5_SR_EXTI0

#define SYSCFG_ITLINE5_SR_EXTI0 SYSCFG_ITLINE5_SR_EXTI0_Msk

External Interrupt 0

◆ SYSCFG_ITLINE5_SR_EXTI0_Msk

#define SYSCFG_ITLINE5_SR_EXTI0_Msk (0x1UL << SYSCFG_ITLINE5_SR_EXTI0_Pos)

0x00000001

◆ SYSCFG_ITLINE5_SR_EXTI0_Pos

#define SYSCFG_ITLINE5_SR_EXTI0_Pos (0U)

◆ SYSCFG_ITLINE5_SR_EXTI1

#define SYSCFG_ITLINE5_SR_EXTI1 SYSCFG_ITLINE5_SR_EXTI1_Msk

External Interrupt 1

◆ SYSCFG_ITLINE5_SR_EXTI1_Msk

#define SYSCFG_ITLINE5_SR_EXTI1_Msk (0x1UL << SYSCFG_ITLINE5_SR_EXTI1_Pos)

0x00000002

◆ SYSCFG_ITLINE5_SR_EXTI1_Pos

#define SYSCFG_ITLINE5_SR_EXTI1_Pos (1U)

◆ SYSCFG_ITLINE6_SR_EXTI2

#define SYSCFG_ITLINE6_SR_EXTI2 SYSCFG_ITLINE6_SR_EXTI2_Msk

External Interrupt 2

◆ SYSCFG_ITLINE6_SR_EXTI2_Msk

#define SYSCFG_ITLINE6_SR_EXTI2_Msk (0x1UL << SYSCFG_ITLINE6_SR_EXTI2_Pos)

0x00000001

◆ SYSCFG_ITLINE6_SR_EXTI2_Pos

#define SYSCFG_ITLINE6_SR_EXTI2_Pos (0U)

◆ SYSCFG_ITLINE6_SR_EXTI3

#define SYSCFG_ITLINE6_SR_EXTI3 SYSCFG_ITLINE6_SR_EXTI3_Msk

External Interrupt 3

◆ SYSCFG_ITLINE6_SR_EXTI3_Msk

#define SYSCFG_ITLINE6_SR_EXTI3_Msk (0x1UL << SYSCFG_ITLINE6_SR_EXTI3_Pos)

0x00000002

◆ SYSCFG_ITLINE6_SR_EXTI3_Pos

#define SYSCFG_ITLINE6_SR_EXTI3_Pos (1U)

◆ SYSCFG_ITLINE7_SR_EXTI10

#define SYSCFG_ITLINE7_SR_EXTI10 SYSCFG_ITLINE7_SR_EXTI10_Msk

External Interrupt 10

◆ SYSCFG_ITLINE7_SR_EXTI10_Msk

#define SYSCFG_ITLINE7_SR_EXTI10_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI10_Pos)

0x00000040

◆ SYSCFG_ITLINE7_SR_EXTI10_Pos

#define SYSCFG_ITLINE7_SR_EXTI10_Pos (6U)

◆ SYSCFG_ITLINE7_SR_EXTI11

#define SYSCFG_ITLINE7_SR_EXTI11 SYSCFG_ITLINE7_SR_EXTI11_Msk

External Interrupt 11

◆ SYSCFG_ITLINE7_SR_EXTI11_Msk

#define SYSCFG_ITLINE7_SR_EXTI11_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI11_Pos)

0x00000080

◆ SYSCFG_ITLINE7_SR_EXTI11_Pos

#define SYSCFG_ITLINE7_SR_EXTI11_Pos (7U)

◆ SYSCFG_ITLINE7_SR_EXTI12

#define SYSCFG_ITLINE7_SR_EXTI12 SYSCFG_ITLINE7_SR_EXTI12_Msk

External Interrupt 12

◆ SYSCFG_ITLINE7_SR_EXTI12_Msk

#define SYSCFG_ITLINE7_SR_EXTI12_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI12_Pos)

0x00000100

◆ SYSCFG_ITLINE7_SR_EXTI12_Pos

#define SYSCFG_ITLINE7_SR_EXTI12_Pos (8U)

◆ SYSCFG_ITLINE7_SR_EXTI13

#define SYSCFG_ITLINE7_SR_EXTI13 SYSCFG_ITLINE7_SR_EXTI13_Msk

External Interrupt 13

◆ SYSCFG_ITLINE7_SR_EXTI13_Msk

#define SYSCFG_ITLINE7_SR_EXTI13_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI13_Pos)

0x00000200

◆ SYSCFG_ITLINE7_SR_EXTI13_Pos

#define SYSCFG_ITLINE7_SR_EXTI13_Pos (9U)

◆ SYSCFG_ITLINE7_SR_EXTI14

#define SYSCFG_ITLINE7_SR_EXTI14 SYSCFG_ITLINE7_SR_EXTI14_Msk

External Interrupt 14

◆ SYSCFG_ITLINE7_SR_EXTI14_Msk

#define SYSCFG_ITLINE7_SR_EXTI14_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI14_Pos)

0x00000400

◆ SYSCFG_ITLINE7_SR_EXTI14_Pos

#define SYSCFG_ITLINE7_SR_EXTI14_Pos (10U)

◆ SYSCFG_ITLINE7_SR_EXTI15

#define SYSCFG_ITLINE7_SR_EXTI15 SYSCFG_ITLINE7_SR_EXTI15_Msk

External Interrupt 15

◆ SYSCFG_ITLINE7_SR_EXTI15_Msk

#define SYSCFG_ITLINE7_SR_EXTI15_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI15_Pos)

0x00000800

◆ SYSCFG_ITLINE7_SR_EXTI15_Pos

#define SYSCFG_ITLINE7_SR_EXTI15_Pos (11U)

◆ SYSCFG_ITLINE7_SR_EXTI4

#define SYSCFG_ITLINE7_SR_EXTI4 SYSCFG_ITLINE7_SR_EXTI4_Msk

External Interrupt 4

◆ SYSCFG_ITLINE7_SR_EXTI4_Msk

#define SYSCFG_ITLINE7_SR_EXTI4_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI4_Pos)

0x00000001

◆ SYSCFG_ITLINE7_SR_EXTI4_Pos

#define SYSCFG_ITLINE7_SR_EXTI4_Pos (0U)

◆ SYSCFG_ITLINE7_SR_EXTI5

#define SYSCFG_ITLINE7_SR_EXTI5 SYSCFG_ITLINE7_SR_EXTI5_Msk

External Interrupt 5

◆ SYSCFG_ITLINE7_SR_EXTI5_Msk

#define SYSCFG_ITLINE7_SR_EXTI5_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI5_Pos)

0x00000002

◆ SYSCFG_ITLINE7_SR_EXTI5_Pos

#define SYSCFG_ITLINE7_SR_EXTI5_Pos (1U)

◆ SYSCFG_ITLINE7_SR_EXTI6

#define SYSCFG_ITLINE7_SR_EXTI6 SYSCFG_ITLINE7_SR_EXTI6_Msk

External Interrupt 6

◆ SYSCFG_ITLINE7_SR_EXTI6_Msk

#define SYSCFG_ITLINE7_SR_EXTI6_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI6_Pos)

0x00000004

◆ SYSCFG_ITLINE7_SR_EXTI6_Pos

#define SYSCFG_ITLINE7_SR_EXTI6_Pos (2U)

◆ SYSCFG_ITLINE7_SR_EXTI7

#define SYSCFG_ITLINE7_SR_EXTI7 SYSCFG_ITLINE7_SR_EXTI7_Msk

External Interrupt 7

◆ SYSCFG_ITLINE7_SR_EXTI7_Msk

#define SYSCFG_ITLINE7_SR_EXTI7_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI7_Pos)

0x00000008

◆ SYSCFG_ITLINE7_SR_EXTI7_Pos

#define SYSCFG_ITLINE7_SR_EXTI7_Pos (3U)

◆ SYSCFG_ITLINE7_SR_EXTI8

#define SYSCFG_ITLINE7_SR_EXTI8 SYSCFG_ITLINE7_SR_EXTI8_Msk

External Interrupt 8

◆ SYSCFG_ITLINE7_SR_EXTI8_Msk

#define SYSCFG_ITLINE7_SR_EXTI8_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI8_Pos)

0x00000010

◆ SYSCFG_ITLINE7_SR_EXTI8_Pos

#define SYSCFG_ITLINE7_SR_EXTI8_Pos (4U)

◆ SYSCFG_ITLINE7_SR_EXTI9

#define SYSCFG_ITLINE7_SR_EXTI9 SYSCFG_ITLINE7_SR_EXTI9_Msk

External Interrupt 9

◆ SYSCFG_ITLINE7_SR_EXTI9_Msk

#define SYSCFG_ITLINE7_SR_EXTI9_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI9_Pos)

0x00000020

◆ SYSCFG_ITLINE7_SR_EXTI9_Pos

#define SYSCFG_ITLINE7_SR_EXTI9_Pos (5U)

◆ SYSCFG_ITLINE9_SR_DMA1_CH1

#define SYSCFG_ITLINE9_SR_DMA1_CH1 SYSCFG_ITLINE9_SR_DMA1_CH1_Msk

DMA1 Channel 1 Interrupt

◆ SYSCFG_ITLINE9_SR_DMA1_CH1_Msk

#define SYSCFG_ITLINE9_SR_DMA1_CH1_Msk (0x1UL << SYSCFG_ITLINE9_SR_DMA1_CH1_Pos)

0x00000001

◆ SYSCFG_ITLINE9_SR_DMA1_CH1_Pos

#define SYSCFG_ITLINE9_SR_DMA1_CH1_Pos (0U)

◆ TAMP_BKP0R

#define TAMP_BKP0R TAMP_BKP0R_Msk

◆ TAMP_BKP0R_Msk

#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos)

0xFFFFFFFF

◆ TAMP_BKP0R_Pos

#define TAMP_BKP0R_Pos (0U)

◆ TAMP_BKP1R

#define TAMP_BKP1R TAMP_BKP1R_Msk

◆ TAMP_BKP1R_Msk

#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos)

0xFFFFFFFF

◆ TAMP_BKP1R_Pos

#define TAMP_BKP1R_Pos (0U)

◆ TAMP_BKP2R

#define TAMP_BKP2R TAMP_BKP2R_Msk

◆ TAMP_BKP2R_Msk

#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos)

0xFFFFFFFF

◆ TAMP_BKP2R_Pos

#define TAMP_BKP2R_Pos (0U)

◆ TAMP_BKP3R

#define TAMP_BKP3R TAMP_BKP3R_Msk

◆ TAMP_BKP3R_Msk

#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos)

0xFFFFFFFF

◆ TAMP_BKP3R_Pos

#define TAMP_BKP3R_Pos (0U)

◆ TAMP_BKP4R

#define TAMP_BKP4R TAMP_BKP4R_Msk

◆ TAMP_BKP4R_Msk

#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos)

0xFFFFFFFF

◆ TAMP_BKP4R_Pos

#define TAMP_BKP4R_Pos (0U)

◆ TAMP_CR1_ITAMP3E

#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk

◆ TAMP_CR1_ITAMP3E_Msk

#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos)

0x00040000

◆ TAMP_CR1_ITAMP3E_Pos

#define TAMP_CR1_ITAMP3E_Pos (18U)

◆ TAMP_CR1_ITAMP4E

#define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk

◆ TAMP_CR1_ITAMP4E_Msk

#define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos)

0x00080000

◆ TAMP_CR1_ITAMP4E_Pos

#define TAMP_CR1_ITAMP4E_Pos (19U)

◆ TAMP_CR1_ITAMP5E

#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk

◆ TAMP_CR1_ITAMP5E_Msk

#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos)

0x00100000

◆ TAMP_CR1_ITAMP5E_Pos

#define TAMP_CR1_ITAMP5E_Pos (20U)

◆ TAMP_CR1_ITAMP6E

#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk

◆ TAMP_CR1_ITAMP6E_Msk

#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos)

0x00200000

◆ TAMP_CR1_ITAMP6E_Pos

#define TAMP_CR1_ITAMP6E_Pos (21U)

◆ TAMP_CR1_TAMP1E

#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk

◆ TAMP_CR1_TAMP1E_Msk

#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos)

0x00000001

◆ TAMP_CR1_TAMP1E_Pos

#define TAMP_CR1_TAMP1E_Pos (0U)

◆ TAMP_CR1_TAMP2E

#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk

◆ TAMP_CR1_TAMP2E_Msk

#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos)

0x00000002

◆ TAMP_CR1_TAMP2E_Pos

#define TAMP_CR1_TAMP2E_Pos (1U)

◆ TAMP_CR2_TAMP1MSK

#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk

◆ TAMP_CR2_TAMP1MSK_Msk

#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos)

0x00010000

◆ TAMP_CR2_TAMP1MSK_Pos

#define TAMP_CR2_TAMP1MSK_Pos (16U)

◆ TAMP_CR2_TAMP1NOERASE

#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk

◆ TAMP_CR2_TAMP1NOERASE_Msk

#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos)

0x00000001

◆ TAMP_CR2_TAMP1NOERASE_Pos

#define TAMP_CR2_TAMP1NOERASE_Pos (0U)

◆ TAMP_CR2_TAMP1TRG

#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk

◆ TAMP_CR2_TAMP1TRG_Msk

#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos)

0x01000000

◆ TAMP_CR2_TAMP1TRG_Pos

#define TAMP_CR2_TAMP1TRG_Pos (24U)

◆ TAMP_CR2_TAMP2MSK

#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk

◆ TAMP_CR2_TAMP2MSK_Msk

#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos)

0x00020000

◆ TAMP_CR2_TAMP2MSK_Pos

#define TAMP_CR2_TAMP2MSK_Pos (17U)

◆ TAMP_CR2_TAMP2NOERASE

#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk

◆ TAMP_CR2_TAMP2NOERASE_Msk

#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos)

0x00000002

◆ TAMP_CR2_TAMP2NOERASE_Pos

#define TAMP_CR2_TAMP2NOERASE_Pos (1U)

◆ TAMP_CR2_TAMP2TRG

#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk

◆ TAMP_CR2_TAMP2TRG_Msk

#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos)

0x02000000

◆ TAMP_CR2_TAMP2TRG_Pos

#define TAMP_CR2_TAMP2TRG_Pos (25U)

◆ TAMP_FLTCR_TAMPFLT

#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk

◆ TAMP_FLTCR_TAMPFLT_0

#define TAMP_FLTCR_TAMPFLT_0 0x00000008U

◆ TAMP_FLTCR_TAMPFLT_1

#define TAMP_FLTCR_TAMPFLT_1 0x00000010U

◆ TAMP_FLTCR_TAMPFLT_Msk

#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos)

0x00000018

◆ TAMP_FLTCR_TAMPFLT_Pos

#define TAMP_FLTCR_TAMPFLT_Pos (3U)

◆ TAMP_FLTCR_TAMPFREQ

#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk

◆ TAMP_FLTCR_TAMPFREQ_0

#define TAMP_FLTCR_TAMPFREQ_0 0x00000001U

◆ TAMP_FLTCR_TAMPFREQ_1

#define TAMP_FLTCR_TAMPFREQ_1 0x00000002U

◆ TAMP_FLTCR_TAMPFREQ_2

#define TAMP_FLTCR_TAMPFREQ_2 0x00000004U

◆ TAMP_FLTCR_TAMPFREQ_Msk

#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos)

0x00000007

◆ TAMP_FLTCR_TAMPFREQ_Pos

#define TAMP_FLTCR_TAMPFREQ_Pos (0U)

◆ TAMP_FLTCR_TAMPPRCH

#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk

◆ TAMP_FLTCR_TAMPPRCH_0

#define TAMP_FLTCR_TAMPPRCH_0 0x00000020U

◆ TAMP_FLTCR_TAMPPRCH_1

#define TAMP_FLTCR_TAMPPRCH_1 0x00000040U

◆ TAMP_FLTCR_TAMPPRCH_Msk

#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos)

0x00000060

◆ TAMP_FLTCR_TAMPPRCH_Pos

#define TAMP_FLTCR_TAMPPRCH_Pos (5U)

◆ TAMP_FLTCR_TAMPPUDIS

#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk

◆ TAMP_FLTCR_TAMPPUDIS_Msk

#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos)

0x00000080

◆ TAMP_FLTCR_TAMPPUDIS_Pos

#define TAMP_FLTCR_TAMPPUDIS_Pos (7U)

◆ TAMP_IER_ITAMP3IE

#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk

◆ TAMP_IER_ITAMP3IE_Msk

#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos)

0x00040000

◆ TAMP_IER_ITAMP3IE_Pos

#define TAMP_IER_ITAMP3IE_Pos (18U)

◆ TAMP_IER_ITAMP4IE

#define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk

◆ TAMP_IER_ITAMP4IE_Msk

#define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos)

0x00080000

◆ TAMP_IER_ITAMP4IE_Pos

#define TAMP_IER_ITAMP4IE_Pos (19U)

◆ TAMP_IER_ITAMP5IE

#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk

◆ TAMP_IER_ITAMP5IE_Msk

#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos)

0x00100000

◆ TAMP_IER_ITAMP5IE_Pos

#define TAMP_IER_ITAMP5IE_Pos (20U)

◆ TAMP_IER_ITAMP6IE

#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk

◆ TAMP_IER_ITAMP6IE_Msk

#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos)

0x00200000

◆ TAMP_IER_ITAMP6IE_Pos

#define TAMP_IER_ITAMP6IE_Pos (21U)

◆ TAMP_IER_TAMP1IE

#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk

◆ TAMP_IER_TAMP1IE_Msk

#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos)

0x00000001

◆ TAMP_IER_TAMP1IE_Pos

#define TAMP_IER_TAMP1IE_Pos (0U)

◆ TAMP_IER_TAMP2IE

#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk

◆ TAMP_IER_TAMP2IE_Msk

#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos)

0x00000002

◆ TAMP_IER_TAMP2IE_Pos

#define TAMP_IER_TAMP2IE_Pos (1U)

◆ TAMP_MISR_ITAMP3MF

#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk

◆ TAMP_MISR_ITAMP3MF_Msk

#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos)

0x00040000

◆ TAMP_MISR_ITAMP3MF_Pos

#define TAMP_MISR_ITAMP3MF_Pos (18U)

◆ TAMP_MISR_ITAMP4MF

#define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk

◆ TAMP_MISR_ITAMP4MF_Msk

#define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos)

0x00080000

◆ TAMP_MISR_ITAMP4MF_Pos

#define TAMP_MISR_ITAMP4MF_Pos (19U)

◆ TAMP_MISR_ITAMP5MF

#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk

◆ TAMP_MISR_ITAMP5MF_Msk

#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos)

0x00100000

◆ TAMP_MISR_ITAMP5MF_Pos

#define TAMP_MISR_ITAMP5MF_Pos (20U)

◆ TAMP_MISR_ITAMP6MF

#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk

◆ TAMP_MISR_ITAMP6MF_Msk

#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos)

0x00200000

◆ TAMP_MISR_ITAMP6MF_Pos

#define TAMP_MISR_ITAMP6MF_Pos (21U)

◆ TAMP_MISR_TAMP1MF

#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk

◆ TAMP_MISR_TAMP1MF_Msk

#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos)

0x00000001

◆ TAMP_MISR_TAMP1MF_Pos

#define TAMP_MISR_TAMP1MF_Pos (0U)

◆ TAMP_MISR_TAMP2MF

#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk

◆ TAMP_MISR_TAMP2MF_Msk

#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos)

0x00000002

◆ TAMP_MISR_TAMP2MF_Pos

#define TAMP_MISR_TAMP2MF_Pos (1U)

◆ TAMP_SCR_CITAMP3F

#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk

◆ TAMP_SCR_CITAMP3F_Msk

#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos)

0x00040000

◆ TAMP_SCR_CITAMP3F_Pos

#define TAMP_SCR_CITAMP3F_Pos (18U)

◆ TAMP_SCR_CITAMP4F

#define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk

◆ TAMP_SCR_CITAMP4F_Msk

#define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos)

0x00080000

◆ TAMP_SCR_CITAMP4F_Pos

#define TAMP_SCR_CITAMP4F_Pos (19U)

◆ TAMP_SCR_CITAMP5F

#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk

◆ TAMP_SCR_CITAMP5F_Msk

#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos)

0x00100000

◆ TAMP_SCR_CITAMP5F_Pos

#define TAMP_SCR_CITAMP5F_Pos (20U)

◆ TAMP_SCR_CITAMP6F

#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk

◆ TAMP_SCR_CITAMP6F_Msk

#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos)

0x00200000

◆ TAMP_SCR_CITAMP6F_Pos

#define TAMP_SCR_CITAMP6F_Pos (21U)

◆ TAMP_SCR_CTAMP1F

#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk

◆ TAMP_SCR_CTAMP1F_Msk

#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos)

0x00000001

◆ TAMP_SCR_CTAMP1F_Pos

#define TAMP_SCR_CTAMP1F_Pos (0U)

◆ TAMP_SCR_CTAMP2F

#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk

◆ TAMP_SCR_CTAMP2F_Msk

#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos)

0x00000002

◆ TAMP_SCR_CTAMP2F_Pos

#define TAMP_SCR_CTAMP2F_Pos (1U)

◆ TAMP_SR_ITAMP3F

#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk

◆ TAMP_SR_ITAMP3F_Msk

#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos)

0x00040000

◆ TAMP_SR_ITAMP3F_Pos

#define TAMP_SR_ITAMP3F_Pos (18U)

◆ TAMP_SR_ITAMP4F

#define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk

◆ TAMP_SR_ITAMP4F_Msk

#define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos)

0x00080000

◆ TAMP_SR_ITAMP4F_Pos

#define TAMP_SR_ITAMP4F_Pos (19U)

◆ TAMP_SR_ITAMP5F

#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk

◆ TAMP_SR_ITAMP5F_Msk

#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos)

0x00100000

◆ TAMP_SR_ITAMP5F_Pos

#define TAMP_SR_ITAMP5F_Pos (20U)

◆ TAMP_SR_ITAMP6F

#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk

◆ TAMP_SR_ITAMP6F_Msk

#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos)

0x00200000

◆ TAMP_SR_ITAMP6F_Pos

#define TAMP_SR_ITAMP6F_Pos (21U)

◆ TAMP_SR_TAMP1F

#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk

◆ TAMP_SR_TAMP1F_Msk

#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos)

0x00000001

◆ TAMP_SR_TAMP1F_Pos

#define TAMP_SR_TAMP1F_Pos (0U)

◆ TAMP_SR_TAMP2F

#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk

◆ TAMP_SR_TAMP2F_Msk

#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos)

0x00000002

◆ TAMP_SR_TAMP2F_Pos

#define TAMP_SR_TAMP2F_Pos (1U)

◆ TIM14_AF1_ETRSEL

#define TIM14_AF1_ETRSEL TIM14_AF1_ETRSEL_Msk

ETRSEL[3:0] bits (TIM14 ETR source selection)

◆ TIM14_AF1_ETRSEL_0

#define TIM14_AF1_ETRSEL_0 (0x1UL << TIM14_AF1_ETRSEL_Pos)

0x00004000

◆ TIM14_AF1_ETRSEL_1

#define TIM14_AF1_ETRSEL_1 (0x2UL << TIM14_AF1_ETRSEL_Pos)

0x00008000

◆ TIM14_AF1_ETRSEL_2

#define TIM14_AF1_ETRSEL_2 (0x4UL << TIM14_AF1_ETRSEL_Pos)

0x00010000

◆ TIM14_AF1_ETRSEL_3

#define TIM14_AF1_ETRSEL_3 (0x8UL << TIM14_AF1_ETRSEL_Pos)

0x00020000

◆ TIM14_AF1_ETRSEL_Msk

#define TIM14_AF1_ETRSEL_Msk (0xFUL << TIM14_AF1_ETRSEL_Pos)

0x0003C000

◆ TIM14_AF1_ETRSEL_Pos

#define TIM14_AF1_ETRSEL_Pos (14U)

◆ TIM16_AF1_BKCMP1E

#define TIM16_AF1_BKCMP1E TIM16_AF1_BKCMP1E_Msk

BRK COMP1 enable

◆ TIM16_AF1_BKCMP1E_Msk

#define TIM16_AF1_BKCMP1E_Msk (0x1UL << TIM16_AF1_BKCMP1E_Pos)

0x00000002

◆ TIM16_AF1_BKCMP1E_Pos

#define TIM16_AF1_BKCMP1E_Pos (1U)

◆ TIM16_AF1_BKCMP1P

#define TIM16_AF1_BKCMP1P TIM16_AF1_BKCMP1P_Msk

BRK COMP1 input polarity

◆ TIM16_AF1_BKCMP1P_Msk

#define TIM16_AF1_BKCMP1P_Msk (0x1UL << TIM16_AF1_BKCMP1P_Pos)

0x00000400

◆ TIM16_AF1_BKCMP1P_Pos

#define TIM16_AF1_BKCMP1P_Pos (10U)

◆ TIM16_AF1_BKCMP2E

#define TIM16_AF1_BKCMP2E TIM16_AF1_BKCMP2E_Msk

BRK COMP2 enable

◆ TIM16_AF1_BKCMP2E_Msk

#define TIM16_AF1_BKCMP2E_Msk (0x1UL << TIM16_AF1_BKCMP2E_Pos)

0x00000004

◆ TIM16_AF1_BKCMP2E_Pos

#define TIM16_AF1_BKCMP2E_Pos (2U)

◆ TIM16_AF1_BKCMP2P

#define TIM16_AF1_BKCMP2P TIM16_AF1_BKCMP2P_Msk

BRK COMP2 input polarity

◆ TIM16_AF1_BKCMP2P_Msk

#define TIM16_AF1_BKCMP2P_Msk (0x1UL << TIM16_AF1_BKCMP2P_Pos)

0x00000800

◆ TIM16_AF1_BKCMP2P_Pos

#define TIM16_AF1_BKCMP2P_Pos (11U)

◆ TIM16_AF1_BKINE

#define TIM16_AF1_BKINE TIM16_AF1_BKINE_Msk

BRK BKIN input enable

◆ TIM16_AF1_BKINE_Msk

#define TIM16_AF1_BKINE_Msk (0x1UL << TIM16_AF1_BKINE_Pos)

0x00000001

◆ TIM16_AF1_BKINE_Pos

#define TIM16_AF1_BKINE_Pos (0U)

◆ TIM16_AF1_BKINP

#define TIM16_AF1_BKINP TIM16_AF1_BKINP_Msk

BRK BKIN input polarity

◆ TIM16_AF1_BKINP_Msk

#define TIM16_AF1_BKINP_Msk (0x1UL << TIM16_AF1_BKINP_Pos)

0x00000200

◆ TIM16_AF1_BKINP_Pos

#define TIM16_AF1_BKINP_Pos (9U)

◆ TIM17_AF1_BKCMP1E

#define TIM17_AF1_BKCMP1E TIM17_AF1_BKCMP1E_Msk

BRK COMP1 enable

◆ TIM17_AF1_BKCMP1E_Msk

#define TIM17_AF1_BKCMP1E_Msk (0x1UL << TIM17_AF1_BKCMP1E_Pos)

0x00000002

◆ TIM17_AF1_BKCMP1E_Pos

#define TIM17_AF1_BKCMP1E_Pos (1U)

◆ TIM17_AF1_BKCMP1P

#define TIM17_AF1_BKCMP1P TIM17_AF1_BKCMP1P_Msk

BRK COMP1 input polarity

◆ TIM17_AF1_BKCMP1P_Msk

#define TIM17_AF1_BKCMP1P_Msk (0x1UL << TIM17_AF1_BKCMP1P_Pos)

0x00000400

◆ TIM17_AF1_BKCMP1P_Pos

#define TIM17_AF1_BKCMP1P_Pos (10U)

◆ TIM17_AF1_BKCMP2E

#define TIM17_AF1_BKCMP2E TIM17_AF1_BKCMP2E_Msk

BRK COMP2 enable

◆ TIM17_AF1_BKCMP2E_Msk

#define TIM17_AF1_BKCMP2E_Msk (0x1UL << TIM17_AF1_BKCMP2E_Pos)

0x00000004

◆ TIM17_AF1_BKCMP2E_Pos

#define TIM17_AF1_BKCMP2E_Pos (2U)

◆ TIM17_AF1_BKCMP2P

#define TIM17_AF1_BKCMP2P TIM17_AF1_BKCMP2P_Msk

BRK COMP2 input polarity

◆ TIM17_AF1_BKCMP2P_Msk

#define TIM17_AF1_BKCMP2P_Msk (0x1UL << TIM17_AF1_BKCMP2P_Pos)

0x00000800

◆ TIM17_AF1_BKCMP2P_Pos

#define TIM17_AF1_BKCMP2P_Pos (11U)

◆ TIM17_AF1_BKINE

#define TIM17_AF1_BKINE TIM17_AF1_BKINE_Msk

BRK BKIN input enable

◆ TIM17_AF1_BKINE_Msk

#define TIM17_AF1_BKINE_Msk (0x1UL << TIM17_AF1_BKINE_Pos)

0x00000001

◆ TIM17_AF1_BKINE_Pos

#define TIM17_AF1_BKINE_Pos (0U)

◆ TIM17_AF1_BKINP

#define TIM17_AF1_BKINP TIM17_AF1_BKINP_Msk

BRK BKIN input polarity

◆ TIM17_AF1_BKINP_Msk

#define TIM17_AF1_BKINP_Msk (0x1UL << TIM17_AF1_BKINP_Pos)

0x00000200

◆ TIM17_AF1_BKINP_Pos

#define TIM17_AF1_BKINP_Pos (9U)

◆ TIM1_AF1_BKCMP1E

#define TIM1_AF1_BKCMP1E TIM1_AF1_BKCMP1E_Msk

BRK COMP1 enable

◆ TIM1_AF1_BKCMP1E_Msk

#define TIM1_AF1_BKCMP1E_Msk (0x1UL << TIM1_AF1_BKCMP1E_Pos)

0x00000002

◆ TIM1_AF1_BKCMP1E_Pos

#define TIM1_AF1_BKCMP1E_Pos (1U)

◆ TIM1_AF1_BKCMP1P

#define TIM1_AF1_BKCMP1P TIM1_AF1_BKCMP1P_Msk

BRK COMP1 input polarity

◆ TIM1_AF1_BKCMP1P_Msk

#define TIM1_AF1_BKCMP1P_Msk (0x1UL << TIM1_AF1_BKCMP1P_Pos)

0x00000400

◆ TIM1_AF1_BKCMP1P_Pos

#define TIM1_AF1_BKCMP1P_Pos (10U)

◆ TIM1_AF1_BKCMP2E

#define TIM1_AF1_BKCMP2E TIM1_AF1_BKCMP2E_Msk

BRK COMP2 enable

◆ TIM1_AF1_BKCMP2E_Msk

#define TIM1_AF1_BKCMP2E_Msk (0x1UL << TIM1_AF1_BKCMP2E_Pos)

0x00000004

◆ TIM1_AF1_BKCMP2E_Pos

#define TIM1_AF1_BKCMP2E_Pos (2U)

◆ TIM1_AF1_BKCMP2P

#define TIM1_AF1_BKCMP2P TIM1_AF1_BKCMP2P_Msk

BRK COMP2 input polarity

◆ TIM1_AF1_BKCMP2P_Msk

#define TIM1_AF1_BKCMP2P_Msk (0x1UL << TIM1_AF1_BKCMP2P_Pos)

0x00000800

◆ TIM1_AF1_BKCMP2P_Pos

#define TIM1_AF1_BKCMP2P_Pos (11U)

◆ TIM1_AF1_BKINE

#define TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk

BRK BKIN input enable

◆ TIM1_AF1_BKINE_Msk

#define TIM1_AF1_BKINE_Msk (0x1UL << TIM1_AF1_BKINE_Pos)

0x00000001

◆ TIM1_AF1_BKINE_Pos

#define TIM1_AF1_BKINE_Pos (0U)

◆ TIM1_AF1_BKINP

#define TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk

BRK BKIN input polarity

◆ TIM1_AF1_BKINP_Msk

#define TIM1_AF1_BKINP_Msk (0x1UL << TIM1_AF1_BKINP_Pos)

0x00000200

◆ TIM1_AF1_BKINP_Pos

#define TIM1_AF1_BKINP_Pos (9U)

◆ TIM1_AF1_ETRSEL

#define TIM1_AF1_ETRSEL TIM1_AF1_ETRSEL_Msk

ETRSEL[3:0] bits (TIM1 ETR source selection)

◆ TIM1_AF1_ETRSEL_0

#define TIM1_AF1_ETRSEL_0 (0x1UL << TIM1_AF1_ETRSEL_Pos)

0x00004000

◆ TIM1_AF1_ETRSEL_1

#define TIM1_AF1_ETRSEL_1 (0x2UL << TIM1_AF1_ETRSEL_Pos)

0x00008000

◆ TIM1_AF1_ETRSEL_2

#define TIM1_AF1_ETRSEL_2 (0x4UL << TIM1_AF1_ETRSEL_Pos)

0x00010000

◆ TIM1_AF1_ETRSEL_3

#define TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos)

0x00020000

◆ TIM1_AF1_ETRSEL_Msk

#define TIM1_AF1_ETRSEL_Msk (0xFUL << TIM1_AF1_ETRSEL_Pos)

0x0003C000

◆ TIM1_AF1_ETRSEL_Pos

#define TIM1_AF1_ETRSEL_Pos (14U)

◆ TIM1_AF2_BK2CMP1E

#define TIM1_AF2_BK2CMP1E TIM1_AF2_BK2CMP1E_Msk

BRK2 COMP1 enable

◆ TIM1_AF2_BK2CMP1E_Msk

#define TIM1_AF2_BK2CMP1E_Msk (0x1UL << TIM1_AF2_BK2CMP1E_Pos)

0x00000002

◆ TIM1_AF2_BK2CMP1E_Pos

#define TIM1_AF2_BK2CMP1E_Pos (1U)

◆ TIM1_AF2_BK2CMP1P

#define TIM1_AF2_BK2CMP1P TIM1_AF2_BK2CMP1P_Msk

BRK2 COMP1 input polarity

◆ TIM1_AF2_BK2CMP1P_Msk

#define TIM1_AF2_BK2CMP1P_Msk (0x1UL << TIM1_AF2_BK2CMP1P_Pos)

0x00000400

◆ TIM1_AF2_BK2CMP1P_Pos

#define TIM1_AF2_BK2CMP1P_Pos (10U)

◆ TIM1_AF2_BK2CMP2E

#define TIM1_AF2_BK2CMP2E TIM1_AF2_BK2CMP2E_Msk

BRK2 COMP2 enable

◆ TIM1_AF2_BK2CMP2E_Msk

#define TIM1_AF2_BK2CMP2E_Msk (0x1UL << TIM1_AF2_BK2CMP2E_Pos)

0x00000004

◆ TIM1_AF2_BK2CMP2E_Pos

#define TIM1_AF2_BK2CMP2E_Pos (2U)

◆ TIM1_AF2_BK2CMP2P

#define TIM1_AF2_BK2CMP2P TIM1_AF2_BK2CMP2P_Msk

BRK2 COMP2 input polarity

◆ TIM1_AF2_BK2CMP2P_Msk

#define TIM1_AF2_BK2CMP2P_Msk (0x1UL << TIM1_AF2_BK2CMP2P_Pos)

0x00000800

◆ TIM1_AF2_BK2CMP2P_Pos

#define TIM1_AF2_BK2CMP2P_Pos (11U)

◆ TIM1_AF2_BK2INE

#define TIM1_AF2_BK2INE TIM1_AF2_BK2INE_Msk

BRK2 BKIN2 input enable

◆ TIM1_AF2_BK2INE_Msk

#define TIM1_AF2_BK2INE_Msk (0x1UL << TIM1_AF2_BK2INE_Pos)

0x00000001

◆ TIM1_AF2_BK2INE_Pos

#define TIM1_AF2_BK2INE_Pos (0U)

◆ TIM1_AF2_BK2INP

#define TIM1_AF2_BK2INP TIM1_AF2_BK2INP_Msk

BRK2 BKIN2 input polarity

◆ TIM1_AF2_BK2INP_Msk

#define TIM1_AF2_BK2INP_Msk (0x1UL << TIM1_AF2_BK2INP_Pos)

0x00000200

◆ TIM1_AF2_BK2INP_Pos

#define TIM1_AF2_BK2INP_Pos (9U)

◆ TIM1_OR1_OCREF_CLR

#define TIM1_OR1_OCREF_CLR TIM1_OR1_OCREF_CLR_Msk

OCREF clear input selection

◆ TIM1_OR1_OCREF_CLR_Msk

#define TIM1_OR1_OCREF_CLR_Msk (0x1UL << TIM1_OR1_OCREF_CLR_Pos)

0x00000001

◆ TIM1_OR1_OCREF_CLR_Pos

#define TIM1_OR1_OCREF_CLR_Pos (0U)

◆ TIM3_AF1_ETRSEL

#define TIM3_AF1_ETRSEL TIM3_AF1_ETRSEL_Msk

ETRSEL[3:0] bits (TIM3 ETR source selection)

◆ TIM3_AF1_ETRSEL_0

#define TIM3_AF1_ETRSEL_0 (0x1UL << TIM3_AF1_ETRSEL_Pos)

0x00004000

◆ TIM3_AF1_ETRSEL_1

#define TIM3_AF1_ETRSEL_1 (0x2UL << TIM3_AF1_ETRSEL_Pos)

0x00008000

◆ TIM3_AF1_ETRSEL_2

#define TIM3_AF1_ETRSEL_2 (0x4UL << TIM3_AF1_ETRSEL_Pos)

0x00010000

◆ TIM3_AF1_ETRSEL_3

#define TIM3_AF1_ETRSEL_3 (0x8UL << TIM3_AF1_ETRSEL_Pos)

0x00020000

◆ TIM3_AF1_ETRSEL_Msk

#define TIM3_AF1_ETRSEL_Msk (0xFUL << TIM3_AF1_ETRSEL_Pos)

0x0003C000

◆ TIM3_AF1_ETRSEL_Pos

#define TIM3_AF1_ETRSEL_Pos (14U)

◆ TIM3_OR1_OCREF_CLR

#define TIM3_OR1_OCREF_CLR TIM3_OR1_OCREF_CLR_Msk

OCREF clear input selection

◆ TIM3_OR1_OCREF_CLR_Msk

#define TIM3_OR1_OCREF_CLR_Msk (0x1UL << TIM3_OR1_OCREF_CLR_Pos)

0x00000001

◆ TIM3_OR1_OCREF_CLR_Pos

#define TIM3_OR1_OCREF_CLR_Pos (0U)

◆ TIM_ARR_ARR

#define TIM_ARR_ARR TIM_ARR_ARR_Msk

Actual auto-reload Value

◆ TIM_ARR_ARR_Msk

#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)

0xFFFFFFFF

◆ TIM_ARR_ARR_Pos

#define TIM_ARR_ARR_Pos (0U)

◆ TIM_BDTR_AOE

#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk

Automatic Output enable

◆ TIM_BDTR_AOE_Msk

#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos)

0x00004000

◆ TIM_BDTR_AOE_Pos

#define TIM_BDTR_AOE_Pos (14U)

◆ TIM_BDTR_BK2BID

#define TIM_BDTR_BK2BID TIM_BDTR_BK2BID_Msk

Break2 BIDirectional

◆ TIM_BDTR_BK2BID_Msk

#define TIM_BDTR_BK2BID_Msk (0x1UL << TIM_BDTR_BK2BID_Pos)

0x20000000

◆ TIM_BDTR_BK2BID_Pos

#define TIM_BDTR_BK2BID_Pos (29U)

◆ TIM_BDTR_BK2DSRM

#define TIM_BDTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk

Break2 disarming/re-arming

◆ TIM_BDTR_BK2DSRM_Msk

#define TIM_BDTR_BK2DSRM_Msk (0x1UL << TIM_BDTR_BK2DSRM_Pos)

0x08000000

◆ TIM_BDTR_BK2DSRM_Pos

#define TIM_BDTR_BK2DSRM_Pos (27U)

◆ TIM_BDTR_BK2E

#define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk

Break enable for Break 2

◆ TIM_BDTR_BK2E_Msk

#define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos)

0x01000000

◆ TIM_BDTR_BK2E_Pos

#define TIM_BDTR_BK2E_Pos (24U)

◆ TIM_BDTR_BK2F

#define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk

Break Filter for Break 2

◆ TIM_BDTR_BK2F_Msk

#define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos)

0x00F00000

◆ TIM_BDTR_BK2F_Pos

#define TIM_BDTR_BK2F_Pos (20U)

◆ TIM_BDTR_BK2P

#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk

Break Polarity for Break 2

◆ TIM_BDTR_BK2P_Msk

#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos)

0x02000000

◆ TIM_BDTR_BK2P_Pos

#define TIM_BDTR_BK2P_Pos (25U)

◆ TIM_BDTR_BKBID

#define TIM_BDTR_BKBID TIM_BDTR_BKBID_Msk

Break BIDirectional

◆ TIM_BDTR_BKBID_Msk

#define TIM_BDTR_BKBID_Msk (0x1UL << TIM_BDTR_BKBID_Pos)

0x10000000

◆ TIM_BDTR_BKBID_Pos

#define TIM_BDTR_BKBID_Pos (28U)

◆ TIM_BDTR_BKDSRM

#define TIM_BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk

Break disarming/re-arming

◆ TIM_BDTR_BKDSRM_Msk

#define TIM_BDTR_BKDSRM_Msk (0x1UL << TIM_BDTR_BKDSRM_Pos)

0x04000000

◆ TIM_BDTR_BKDSRM_Pos

#define TIM_BDTR_BKDSRM_Pos (26U)

◆ TIM_BDTR_BKE

#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk

Break enable for Break 1

◆ TIM_BDTR_BKE_Msk

#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos)

0x00001000

◆ TIM_BDTR_BKE_Pos

#define TIM_BDTR_BKE_Pos (12U)

◆ TIM_BDTR_BKF

#define TIM_BDTR_BKF TIM_BDTR_BKF_Msk

Break Filter for Break 1

◆ TIM_BDTR_BKF_Msk

#define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos)

0x000F0000

◆ TIM_BDTR_BKF_Pos

#define TIM_BDTR_BKF_Pos (16U)

◆ TIM_BDTR_BKP

#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk

Break Polarity for Break 1

◆ TIM_BDTR_BKP_Msk

#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos)

0x00002000

◆ TIM_BDTR_BKP_Pos

#define TIM_BDTR_BKP_Pos (13U)

◆ TIM_BDTR_DTG

#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk

DTG[0:7] bits (Dead-Time Generator set-up)

◆ TIM_BDTR_DTG_0

#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos)

0x00000001

◆ TIM_BDTR_DTG_1

#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos)

0x00000002

◆ TIM_BDTR_DTG_2

#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos)

0x00000004

◆ TIM_BDTR_DTG_3

#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos)

0x00000008

◆ TIM_BDTR_DTG_4

#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos)

0x00000010

◆ TIM_BDTR_DTG_5

#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos)

0x00000020

◆ TIM_BDTR_DTG_6

#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos)

0x00000040

◆ TIM_BDTR_DTG_7

#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos)

0x00000080

◆ TIM_BDTR_DTG_Msk

#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos)

0x000000FF

◆ TIM_BDTR_DTG_Pos

#define TIM_BDTR_DTG_Pos (0U)

◆ TIM_BDTR_LOCK

#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk

LOCK[1:0] bits (Lock Configuration)

◆ TIM_BDTR_LOCK_0

#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos)

0x00000100

◆ TIM_BDTR_LOCK_1

#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos)

0x00000200

◆ TIM_BDTR_LOCK_Msk

#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos)

0x00000300

◆ TIM_BDTR_LOCK_Pos

#define TIM_BDTR_LOCK_Pos (8U)

◆ TIM_BDTR_MOE

#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk

Main Output enable

◆ TIM_BDTR_MOE_Msk

#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos)

0x00008000

◆ TIM_BDTR_MOE_Pos

#define TIM_BDTR_MOE_Pos (15U)

◆ TIM_BDTR_OSSI

#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk

Off-State Selection for Idle mode

◆ TIM_BDTR_OSSI_Msk

#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos)

0x00000400

◆ TIM_BDTR_OSSI_Pos

#define TIM_BDTR_OSSI_Pos (10U)

◆ TIM_BDTR_OSSR

#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk

Off-State Selection for Run mode

◆ TIM_BDTR_OSSR_Msk

#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos)

0x00000800

◆ TIM_BDTR_OSSR_Pos

#define TIM_BDTR_OSSR_Pos (11U)

◆ TIM_CCER_CC1E

#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk

Capture/Compare 1 output enable

◆ TIM_CCER_CC1E_Msk

#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos)

0x00000001

◆ TIM_CCER_CC1E_Pos

#define TIM_CCER_CC1E_Pos (0U)

◆ TIM_CCER_CC1NE

#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk

Capture/Compare 1 Complementary output enable

◆ TIM_CCER_CC1NE_Msk

#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos)

0x00000004

◆ TIM_CCER_CC1NE_Pos

#define TIM_CCER_CC1NE_Pos (2U)

◆ TIM_CCER_CC1NP

#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk

Capture/Compare 1 Complementary output Polarity

◆ TIM_CCER_CC1NP_Msk

#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos)

0x00000008

◆ TIM_CCER_CC1NP_Pos

#define TIM_CCER_CC1NP_Pos (3U)

◆ TIM_CCER_CC1P

#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk

Capture/Compare 1 output Polarity

◆ TIM_CCER_CC1P_Msk

#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos)

0x00000002

◆ TIM_CCER_CC1P_Pos

#define TIM_CCER_CC1P_Pos (1U)

◆ TIM_CCER_CC2E

#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk

Capture/Compare 2 output enable

◆ TIM_CCER_CC2E_Msk

#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos)

0x00000010

◆ TIM_CCER_CC2E_Pos

#define TIM_CCER_CC2E_Pos (4U)

◆ TIM_CCER_CC2NE

#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk

Capture/Compare 2 Complementary output enable

◆ TIM_CCER_CC2NE_Msk

#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos)

0x00000040

◆ TIM_CCER_CC2NE_Pos

#define TIM_CCER_CC2NE_Pos (6U)

◆ TIM_CCER_CC2NP

#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk

Capture/Compare 2 Complementary output Polarity

◆ TIM_CCER_CC2NP_Msk

#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos)

0x00000080

◆ TIM_CCER_CC2NP_Pos

#define TIM_CCER_CC2NP_Pos (7U)

◆ TIM_CCER_CC2P

#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk

Capture/Compare 2 output Polarity

◆ TIM_CCER_CC2P_Msk

#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos)

0x00000020

◆ TIM_CCER_CC2P_Pos

#define TIM_CCER_CC2P_Pos (5U)

◆ TIM_CCER_CC3E

#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk

Capture/Compare 3 output enable

◆ TIM_CCER_CC3E_Msk

#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos)

0x00000100

◆ TIM_CCER_CC3E_Pos

#define TIM_CCER_CC3E_Pos (8U)

◆ TIM_CCER_CC3NE

#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk

Capture/Compare 3 Complementary output enable

◆ TIM_CCER_CC3NE_Msk

#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos)

0x00000400

◆ TIM_CCER_CC3NE_Pos

#define TIM_CCER_CC3NE_Pos (10U)

◆ TIM_CCER_CC3NP

#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk

Capture/Compare 3 Complementary output Polarity

◆ TIM_CCER_CC3NP_Msk

#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos)

0x00000800

◆ TIM_CCER_CC3NP_Pos

#define TIM_CCER_CC3NP_Pos (11U)

◆ TIM_CCER_CC3P

#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk

Capture/Compare 3 output Polarity

◆ TIM_CCER_CC3P_Msk

#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos)

0x00000200

◆ TIM_CCER_CC3P_Pos

#define TIM_CCER_CC3P_Pos (9U)

◆ TIM_CCER_CC4E

#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk

Capture/Compare 4 output enable

◆ TIM_CCER_CC4E_Msk

#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos)

0x00001000

◆ TIM_CCER_CC4E_Pos

#define TIM_CCER_CC4E_Pos (12U)

◆ TIM_CCER_CC4NP

#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk

Capture/Compare 4 Complementary output Polarity

◆ TIM_CCER_CC4NP_Msk

#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos)

0x00008000

◆ TIM_CCER_CC4NP_Pos

#define TIM_CCER_CC4NP_Pos (15U)

◆ TIM_CCER_CC4P

#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk

Capture/Compare 4 output Polarity

◆ TIM_CCER_CC4P_Msk

#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos)

0x00002000

◆ TIM_CCER_CC4P_Pos

#define TIM_CCER_CC4P_Pos (13U)

◆ TIM_CCER_CC5E

#define TIM_CCER_CC5E TIM_CCER_CC5E_Msk

Capture/Compare 5 output enable

◆ TIM_CCER_CC5E_Msk

#define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos)

0x00010000

◆ TIM_CCER_CC5E_Pos

#define TIM_CCER_CC5E_Pos (16U)

◆ TIM_CCER_CC5P

#define TIM_CCER_CC5P TIM_CCER_CC5P_Msk

Capture/Compare 5 output Polarity

◆ TIM_CCER_CC5P_Msk

#define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos)

0x00020000

◆ TIM_CCER_CC5P_Pos

#define TIM_CCER_CC5P_Pos (17U)

◆ TIM_CCER_CC6E

#define TIM_CCER_CC6E TIM_CCER_CC6E_Msk

Capture/Compare 6 output enable

◆ TIM_CCER_CC6E_Msk

#define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos)

0x00100000

◆ TIM_CCER_CC6E_Pos

#define TIM_CCER_CC6E_Pos (20U)

◆ TIM_CCER_CC6P

#define TIM_CCER_CC6P TIM_CCER_CC6P_Msk

Capture/Compare 6 output Polarity

◆ TIM_CCER_CC6P_Msk

#define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos)

0x00200000

◆ TIM_CCER_CC6P_Pos

#define TIM_CCER_CC6P_Pos (21U)

◆ TIM_CCMR1_CC1S

#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk

CC1S[1:0] bits (Capture/Compare 1 Selection)

◆ TIM_CCMR1_CC1S_0

#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos)

0x00000001

◆ TIM_CCMR1_CC1S_1

#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos)

0x00000002

◆ TIM_CCMR1_CC1S_Msk

#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos)

0x00000003

◆ TIM_CCMR1_CC1S_Pos

#define TIM_CCMR1_CC1S_Pos (0U)

◆ TIM_CCMR1_CC2S

#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk

CC2S[1:0] bits (Capture/Compare 2 Selection)

◆ TIM_CCMR1_CC2S_0

#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos)

0x00000100

◆ TIM_CCMR1_CC2S_1

#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos)

0x00000200

◆ TIM_CCMR1_CC2S_Msk

#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos)

0x00000300

◆ TIM_CCMR1_CC2S_Pos

#define TIM_CCMR1_CC2S_Pos (8U)

◆ TIM_CCMR1_IC1F

#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk

IC1F[3:0] bits (Input Capture 1 Filter)

◆ TIM_CCMR1_IC1F_0

#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos)

0x00000010

◆ TIM_CCMR1_IC1F_1

#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos)

0x00000020

◆ TIM_CCMR1_IC1F_2

#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos)

0x00000040

◆ TIM_CCMR1_IC1F_3

#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos)

0x00000080

◆ TIM_CCMR1_IC1F_Msk

#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos)

0x000000F0

◆ TIM_CCMR1_IC1F_Pos

#define TIM_CCMR1_IC1F_Pos (4U)

◆ TIM_CCMR1_IC1PSC

#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk

IC1PSC[1:0] bits (Input Capture 1 Prescaler)

◆ TIM_CCMR1_IC1PSC_0

#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos)

0x00000004

◆ TIM_CCMR1_IC1PSC_1

#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos)

0x00000008

◆ TIM_CCMR1_IC1PSC_Msk

#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos)

0x0000000C

◆ TIM_CCMR1_IC1PSC_Pos

#define TIM_CCMR1_IC1PSC_Pos (2U)

◆ TIM_CCMR1_IC2F

#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk

IC2F[3:0] bits (Input Capture 2 Filter)

◆ TIM_CCMR1_IC2F_0

#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos)

0x00001000

◆ TIM_CCMR1_IC2F_1

#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos)

0x00002000

◆ TIM_CCMR1_IC2F_2

#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos)

0x00004000

◆ TIM_CCMR1_IC2F_3

#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos)

0x00008000

◆ TIM_CCMR1_IC2F_Msk

#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos)

0x0000F000

◆ TIM_CCMR1_IC2F_Pos

#define TIM_CCMR1_IC2F_Pos (12U)

◆ TIM_CCMR1_IC2PSC

#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk

IC2PSC[1:0] bits (Input Capture 2 Prescaler)

◆ TIM_CCMR1_IC2PSC_0

#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos)

0x00000400

◆ TIM_CCMR1_IC2PSC_1

#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos)

0x00000800

◆ TIM_CCMR1_IC2PSC_Msk

#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos)

0x00000C00

◆ TIM_CCMR1_IC2PSC_Pos

#define TIM_CCMR1_IC2PSC_Pos (10U)

◆ TIM_CCMR1_OC1CE

#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk

Output Compare 1 Clear Enable

◆ TIM_CCMR1_OC1CE_Msk

#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos)

0x00000080

◆ TIM_CCMR1_OC1CE_Pos

#define TIM_CCMR1_OC1CE_Pos (7U)

◆ TIM_CCMR1_OC1FE

#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk

Output Compare 1 Fast enable

◆ TIM_CCMR1_OC1FE_Msk

#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos)

0x00000004

◆ TIM_CCMR1_OC1FE_Pos

#define TIM_CCMR1_OC1FE_Pos (2U)

◆ TIM_CCMR1_OC1M

#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk

OC1M[2:0] bits (Output Compare 1 Mode)

◆ TIM_CCMR1_OC1M_0

#define TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos)

0x00000010

◆ TIM_CCMR1_OC1M_1

#define TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos)

0x00000020

◆ TIM_CCMR1_OC1M_2

#define TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos)

0x00000040

◆ TIM_CCMR1_OC1M_3

#define TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos)

0x00010000

◆ TIM_CCMR1_OC1M_Msk

#define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos)

0x00010070

◆ TIM_CCMR1_OC1M_Pos

#define TIM_CCMR1_OC1M_Pos (4U)

◆ TIM_CCMR1_OC1PE

#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk

Output Compare 1 Preload enable

◆ TIM_CCMR1_OC1PE_Msk

#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos)

0x00000008

◆ TIM_CCMR1_OC1PE_Pos

#define TIM_CCMR1_OC1PE_Pos (3U)

◆ TIM_CCMR1_OC2CE

#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk

Output Compare 2 Clear Enable

◆ TIM_CCMR1_OC2CE_Msk

#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos)

0x00008000

◆ TIM_CCMR1_OC2CE_Pos

#define TIM_CCMR1_OC2CE_Pos (15U)

◆ TIM_CCMR1_OC2FE

#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk

Output Compare 2 Fast enable

◆ TIM_CCMR1_OC2FE_Msk

#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos)

0x00000400

◆ TIM_CCMR1_OC2FE_Pos

#define TIM_CCMR1_OC2FE_Pos (10U)

◆ TIM_CCMR1_OC2M

#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk

OC2M[2:0] bits (Output Compare 2 Mode)

◆ TIM_CCMR1_OC2M_0

#define TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos)

0x00001000

◆ TIM_CCMR1_OC2M_1

#define TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos)

0x00002000

◆ TIM_CCMR1_OC2M_2

#define TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos)

0x00004000

◆ TIM_CCMR1_OC2M_3

#define TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos)

0x01000000

◆ TIM_CCMR1_OC2M_Msk

#define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos)

0x01007000

◆ TIM_CCMR1_OC2M_Pos

#define TIM_CCMR1_OC2M_Pos (12U)

◆ TIM_CCMR1_OC2PE

#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk

Output Compare 2 Preload enable

◆ TIM_CCMR1_OC2PE_Msk

#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos)

0x00000800

◆ TIM_CCMR1_OC2PE_Pos

#define TIM_CCMR1_OC2PE_Pos (11U)

◆ TIM_CCMR2_CC3S

#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk

CC3S[1:0] bits (Capture/Compare 3 Selection)

◆ TIM_CCMR2_CC3S_0

#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos)

0x00000001

◆ TIM_CCMR2_CC3S_1

#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos)

0x00000002

◆ TIM_CCMR2_CC3S_Msk

#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos)

0x00000003

◆ TIM_CCMR2_CC3S_Pos

#define TIM_CCMR2_CC3S_Pos (0U)

◆ TIM_CCMR2_CC4S

#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk

CC4S[1:0] bits (Capture/Compare 4 Selection)

◆ TIM_CCMR2_CC4S_0

#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos)

0x00000100

◆ TIM_CCMR2_CC4S_1

#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos)

0x00000200

◆ TIM_CCMR2_CC4S_Msk

#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos)

0x00000300

◆ TIM_CCMR2_CC4S_Pos

#define TIM_CCMR2_CC4S_Pos (8U)

◆ TIM_CCMR2_IC3F

#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk

IC3F[3:0] bits (Input Capture 3 Filter)

◆ TIM_CCMR2_IC3F_0

#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos)

0x00000010

◆ TIM_CCMR2_IC3F_1

#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos)

0x00000020

◆ TIM_CCMR2_IC3F_2

#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos)

0x00000040

◆ TIM_CCMR2_IC3F_3

#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos)

0x00000080

◆ TIM_CCMR2_IC3F_Msk

#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos)

0x000000F0

◆ TIM_CCMR2_IC3F_Pos

#define TIM_CCMR2_IC3F_Pos (4U)

◆ TIM_CCMR2_IC3PSC

#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk

IC3PSC[1:0] bits (Input Capture 3 Prescaler)

◆ TIM_CCMR2_IC3PSC_0

#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos)

0x00000004

◆ TIM_CCMR2_IC3PSC_1

#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos)

0x00000008

◆ TIM_CCMR2_IC3PSC_Msk

#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos)

0x0000000C

◆ TIM_CCMR2_IC3PSC_Pos

#define TIM_CCMR2_IC3PSC_Pos (2U)

◆ TIM_CCMR2_IC4F

#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk

IC4F[3:0] bits (Input Capture 4 Filter)

◆ TIM_CCMR2_IC4F_0

#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos)

0x00001000

◆ TIM_CCMR2_IC4F_1

#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos)

0x00002000

◆ TIM_CCMR2_IC4F_2

#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos)

0x00004000

◆ TIM_CCMR2_IC4F_3

#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos)

0x00008000

◆ TIM_CCMR2_IC4F_Msk

#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos)

0x0000F000

◆ TIM_CCMR2_IC4F_Pos

#define TIM_CCMR2_IC4F_Pos (12U)

◆ TIM_CCMR2_IC4PSC

#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk

IC4PSC[1:0] bits (Input Capture 4 Prescaler)

◆ TIM_CCMR2_IC4PSC_0

#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos)

0x00000400

◆ TIM_CCMR2_IC4PSC_1

#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos)

0x00000800

◆ TIM_CCMR2_IC4PSC_Msk

#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos)

0x00000C00

◆ TIM_CCMR2_IC4PSC_Pos

#define TIM_CCMR2_IC4PSC_Pos (10U)

◆ TIM_CCMR2_OC3CE

#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk

Output Compare 3 Clear Enable

◆ TIM_CCMR2_OC3CE_Msk

#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos)

0x00000080

◆ TIM_CCMR2_OC3CE_Pos

#define TIM_CCMR2_OC3CE_Pos (7U)

◆ TIM_CCMR2_OC3FE

#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk

Output Compare 3 Fast enable

◆ TIM_CCMR2_OC3FE_Msk

#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos)

0x00000004

◆ TIM_CCMR2_OC3FE_Pos

#define TIM_CCMR2_OC3FE_Pos (2U)

◆ TIM_CCMR2_OC3M

#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk

OC3M[2:0] bits (Output Compare 3 Mode)

◆ TIM_CCMR2_OC3M_0

#define TIM_CCMR2_OC3M_0 (0x0001UL << TIM_CCMR2_OC3M_Pos)

0x00000010

◆ TIM_CCMR2_OC3M_1

#define TIM_CCMR2_OC3M_1 (0x0002UL << TIM_CCMR2_OC3M_Pos)

0x00000020

◆ TIM_CCMR2_OC3M_2

#define TIM_CCMR2_OC3M_2 (0x0004UL << TIM_CCMR2_OC3M_Pos)

0x00000040

◆ TIM_CCMR2_OC3M_3

#define TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos)

0x00010000

◆ TIM_CCMR2_OC3M_Msk

#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos)

0x00010070

◆ TIM_CCMR2_OC3M_Pos

#define TIM_CCMR2_OC3M_Pos (4U)

◆ TIM_CCMR2_OC3PE

#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk

Output Compare 3 Preload enable

◆ TIM_CCMR2_OC3PE_Msk

#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos)

0x00000008

◆ TIM_CCMR2_OC3PE_Pos

#define TIM_CCMR2_OC3PE_Pos (3U)

◆ TIM_CCMR2_OC4CE

#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk

Output Compare 4 Clear Enable

◆ TIM_CCMR2_OC4CE_Msk

#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos)

0x00008000

◆ TIM_CCMR2_OC4CE_Pos

#define TIM_CCMR2_OC4CE_Pos (15U)

◆ TIM_CCMR2_OC4FE

#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk

Output Compare 4 Fast enable

◆ TIM_CCMR2_OC4FE_Msk

#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos)

0x00000400

◆ TIM_CCMR2_OC4FE_Pos

#define TIM_CCMR2_OC4FE_Pos (10U)

◆ TIM_CCMR2_OC4M

#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk

OC4M[2:0] bits (Output Compare 4 Mode)

◆ TIM_CCMR2_OC4M_0

#define TIM_CCMR2_OC4M_0 (0x0001UL << TIM_CCMR2_OC4M_Pos)

0x00001000

◆ TIM_CCMR2_OC4M_1

#define TIM_CCMR2_OC4M_1 (0x0002UL << TIM_CCMR2_OC4M_Pos)

0x00002000

◆ TIM_CCMR2_OC4M_2

#define TIM_CCMR2_OC4M_2 (0x0004UL << TIM_CCMR2_OC4M_Pos)

0x00004000

◆ TIM_CCMR2_OC4M_3

#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos)

0x01000000

◆ TIM_CCMR2_OC4M_Msk

#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos)

0x01007000

◆ TIM_CCMR2_OC4M_Pos

#define TIM_CCMR2_OC4M_Pos (12U)

◆ TIM_CCMR2_OC4PE

#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk

Output Compare 4 Preload enable

◆ TIM_CCMR2_OC4PE_Msk

#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos)

0x00000800

◆ TIM_CCMR2_OC4PE_Pos

#define TIM_CCMR2_OC4PE_Pos (11U)

◆ TIM_CCMR3_OC5CE

#define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk

Output Compare 5 Clear Enable

◆ TIM_CCMR3_OC5CE_Msk

#define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos)

0x00000080

◆ TIM_CCMR3_OC5CE_Pos

#define TIM_CCMR3_OC5CE_Pos (7U)

◆ TIM_CCMR3_OC5FE

#define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk

Output Compare 5 Fast enable

◆ TIM_CCMR3_OC5FE_Msk

#define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos)

0x00000004

◆ TIM_CCMR3_OC5FE_Pos

#define TIM_CCMR3_OC5FE_Pos (2U)

◆ TIM_CCMR3_OC5M

#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk

OC5M[3:0] bits (Output Compare 5 Mode)

◆ TIM_CCMR3_OC5M_0

#define TIM_CCMR3_OC5M_0 (0x0001UL << TIM_CCMR3_OC5M_Pos)

0x00000010

◆ TIM_CCMR3_OC5M_1

#define TIM_CCMR3_OC5M_1 (0x0002UL << TIM_CCMR3_OC5M_Pos)

0x00000020

◆ TIM_CCMR3_OC5M_2

#define TIM_CCMR3_OC5M_2 (0x0004UL << TIM_CCMR3_OC5M_Pos)

0x00000040

◆ TIM_CCMR3_OC5M_3

#define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos)

0x00010000

◆ TIM_CCMR3_OC5M_Msk

#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos)

0x00010070

◆ TIM_CCMR3_OC5M_Pos

#define TIM_CCMR3_OC5M_Pos (4U)

◆ TIM_CCMR3_OC5PE

#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk

Output Compare 5 Preload enable

◆ TIM_CCMR3_OC5PE_Msk

#define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos)

0x00000008

◆ TIM_CCMR3_OC5PE_Pos

#define TIM_CCMR3_OC5PE_Pos (3U)

◆ TIM_CCMR3_OC6CE

#define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk

Output Compare 6 Clear Enable

◆ TIM_CCMR3_OC6CE_Msk

#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos)

0x00008000

◆ TIM_CCMR3_OC6CE_Pos

#define TIM_CCMR3_OC6CE_Pos (15U)

◆ TIM_CCMR3_OC6FE

#define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk

Output Compare 6 Fast enable

◆ TIM_CCMR3_OC6FE_Msk

#define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos)

0x00000400

◆ TIM_CCMR3_OC6FE_Pos

#define TIM_CCMR3_OC6FE_Pos (10U)

◆ TIM_CCMR3_OC6M

#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk

OC6M[3:0] bits (Output Compare 6 Mode)

◆ TIM_CCMR3_OC6M_0

#define TIM_CCMR3_OC6M_0 (0x0001UL << TIM_CCMR3_OC6M_Pos)

0x00001000

◆ TIM_CCMR3_OC6M_1

#define TIM_CCMR3_OC6M_1 (0x0002UL << TIM_CCMR3_OC6M_Pos)

0x00002000

◆ TIM_CCMR3_OC6M_2

#define TIM_CCMR3_OC6M_2 (0x0004UL << TIM_CCMR3_OC6M_Pos)

0x00004000

◆ TIM_CCMR3_OC6M_3

#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos)

0x01000000

◆ TIM_CCMR3_OC6M_Msk

#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos)

0x01007000

◆ TIM_CCMR3_OC6M_Pos

#define TIM_CCMR3_OC6M_Pos (12U)

◆ TIM_CCMR3_OC6PE

#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk

Output Compare 6 Preload enable

◆ TIM_CCMR3_OC6PE_Msk

#define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos)

0x00000800

◆ TIM_CCMR3_OC6PE_Pos

#define TIM_CCMR3_OC6PE_Pos (11U)

◆ TIM_CCR1_CCR1

#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk

Capture/Compare 1 Value

◆ TIM_CCR1_CCR1_Msk

#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos)

0x0000FFFF

◆ TIM_CCR1_CCR1_Pos

#define TIM_CCR1_CCR1_Pos (0U)

◆ TIM_CCR2_CCR2

#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk

Capture/Compare 2 Value

◆ TIM_CCR2_CCR2_Msk

#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos)

0x0000FFFF

◆ TIM_CCR2_CCR2_Pos

#define TIM_CCR2_CCR2_Pos (0U)

◆ TIM_CCR3_CCR3

#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk

Capture/Compare 3 Value

◆ TIM_CCR3_CCR3_Msk

#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos)

0x0000FFFF

◆ TIM_CCR3_CCR3_Pos

#define TIM_CCR3_CCR3_Pos (0U)

◆ TIM_CCR4_CCR4

#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk

Capture/Compare 4 Value

◆ TIM_CCR4_CCR4_Msk

#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos)

0x0000FFFF

◆ TIM_CCR4_CCR4_Pos

#define TIM_CCR4_CCR4_Pos (0U)

◆ TIM_CCR5_CCR5

#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk

Capture/Compare 5 Value

◆ TIM_CCR5_CCR5_Msk

#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)

0xFFFFFFFF

◆ TIM_CCR5_CCR5_Pos

#define TIM_CCR5_CCR5_Pos (0U)

◆ TIM_CCR5_GC5C1

#define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk

Group Channel 5 and Channel 1

◆ TIM_CCR5_GC5C1_Msk

#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos)

0x20000000

◆ TIM_CCR5_GC5C1_Pos

#define TIM_CCR5_GC5C1_Pos (29U)

◆ TIM_CCR5_GC5C2

#define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk

Group Channel 5 and Channel 2

◆ TIM_CCR5_GC5C2_Msk

#define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos)

0x40000000

◆ TIM_CCR5_GC5C2_Pos

#define TIM_CCR5_GC5C2_Pos (30U)

◆ TIM_CCR5_GC5C3

#define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk

Group Channel 5 and Channel 3

◆ TIM_CCR5_GC5C3_Msk

#define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos)

0x80000000

◆ TIM_CCR5_GC5C3_Pos

#define TIM_CCR5_GC5C3_Pos (31U)

◆ TIM_CCR6_CCR6

#define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk

Capture/Compare 6 Value

◆ TIM_CCR6_CCR6_Msk

#define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos)

0x0000FFFF

◆ TIM_CCR6_CCR6_Pos

#define TIM_CCR6_CCR6_Pos (0U)

◆ TIM_CNT_CNT

#define TIM_CNT_CNT TIM_CNT_CNT_Msk

Counter Value

◆ TIM_CNT_CNT_Msk

#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)

0xFFFFFFFF

◆ TIM_CNT_CNT_Pos

#define TIM_CNT_CNT_Pos (0U)

◆ TIM_CNT_UIFCPY

#define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk

Update interrupt flag copy (if UIFREMAP=1)

◆ TIM_CNT_UIFCPY_Msk

#define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos)

0x80000000

◆ TIM_CNT_UIFCPY_Pos

#define TIM_CNT_UIFCPY_Pos (31U)

◆ TIM_CR1_ARPE

#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk

Auto-reload preload enable

◆ TIM_CR1_ARPE_Msk

#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos)

0x00000080

◆ TIM_CR1_ARPE_Pos

#define TIM_CR1_ARPE_Pos (7U)

◆ TIM_CR1_CEN

#define TIM_CR1_CEN TIM_CR1_CEN_Msk

Counter enable

◆ TIM_CR1_CEN_Msk

#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos)

0x00000001

◆ TIM_CR1_CEN_Pos

#define TIM_CR1_CEN_Pos (0U)

◆ TIM_CR1_CKD

#define TIM_CR1_CKD TIM_CR1_CKD_Msk

CKD[1:0] bits (clock division)

◆ TIM_CR1_CKD_0

#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos)

0x00000100

◆ TIM_CR1_CKD_1

#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos)

0x00000200

◆ TIM_CR1_CKD_Msk

#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos)

0x00000300

◆ TIM_CR1_CKD_Pos

#define TIM_CR1_CKD_Pos (8U)

◆ TIM_CR1_CMS

#define TIM_CR1_CMS TIM_CR1_CMS_Msk

CMS[1:0] bits (Center-aligned mode selection)

◆ TIM_CR1_CMS_0

#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos)

0x00000020

◆ TIM_CR1_CMS_1

#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos)

0x00000040

◆ TIM_CR1_CMS_Msk

#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos)

0x00000060

◆ TIM_CR1_CMS_Pos

#define TIM_CR1_CMS_Pos (5U)

◆ TIM_CR1_DIR

#define TIM_CR1_DIR TIM_CR1_DIR_Msk

Direction

◆ TIM_CR1_DIR_Msk

#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos)

0x00000010

◆ TIM_CR1_DIR_Pos

#define TIM_CR1_DIR_Pos (4U)

◆ TIM_CR1_OPM

#define TIM_CR1_OPM TIM_CR1_OPM_Msk

One pulse mode

◆ TIM_CR1_OPM_Msk

#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos)

0x00000008

◆ TIM_CR1_OPM_Pos

#define TIM_CR1_OPM_Pos (3U)

◆ TIM_CR1_UDIS

#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk

Update disable

◆ TIM_CR1_UDIS_Msk

#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos)

0x00000002

◆ TIM_CR1_UDIS_Pos

#define TIM_CR1_UDIS_Pos (1U)

◆ TIM_CR1_UIFREMAP

#define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk

Update interrupt flag remap

◆ TIM_CR1_UIFREMAP_Msk

#define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos)

0x00000800

◆ TIM_CR1_UIFREMAP_Pos

#define TIM_CR1_UIFREMAP_Pos (11U)

◆ TIM_CR1_URS

#define TIM_CR1_URS TIM_CR1_URS_Msk

Update request source

◆ TIM_CR1_URS_Msk

#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos)

0x00000004

◆ TIM_CR1_URS_Pos

#define TIM_CR1_URS_Pos (2U)

◆ TIM_CR2_CCDS

#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk

Capture/Compare DMA Selection

◆ TIM_CR2_CCDS_Msk

#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos)

0x00000008

◆ TIM_CR2_CCDS_Pos

#define TIM_CR2_CCDS_Pos (3U)

◆ TIM_CR2_CCPC

#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk

Capture/Compare Preloaded Control

◆ TIM_CR2_CCPC_Msk

#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos)

0x00000001

◆ TIM_CR2_CCPC_Pos

#define TIM_CR2_CCPC_Pos (0U)

◆ TIM_CR2_CCUS

#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk

Capture/Compare Control Update Selection

◆ TIM_CR2_CCUS_Msk

#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos)

0x00000004

◆ TIM_CR2_CCUS_Pos

#define TIM_CR2_CCUS_Pos (2U)

◆ TIM_CR2_MMS

#define TIM_CR2_MMS TIM_CR2_MMS_Msk

MMS[2:0] bits (Master Mode Selection)

◆ TIM_CR2_MMS2

#define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk

MMS[2:0] bits (Master Mode Selection)

◆ TIM_CR2_MMS2_0

#define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos)

0x00100000

◆ TIM_CR2_MMS2_1

#define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos)

0x00200000

◆ TIM_CR2_MMS2_2

#define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos)

0x00400000

◆ TIM_CR2_MMS2_3

#define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos)

0x00800000

◆ TIM_CR2_MMS2_Msk

#define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos)

0x00F00000

◆ TIM_CR2_MMS2_Pos

#define TIM_CR2_MMS2_Pos (20U)

◆ TIM_CR2_MMS_0

#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos)

0x00000010

◆ TIM_CR2_MMS_1

#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos)

0x00000020

◆ TIM_CR2_MMS_2

#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos)

0x00000040

◆ TIM_CR2_MMS_Msk

#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos)

0x00000070

◆ TIM_CR2_MMS_Pos

#define TIM_CR2_MMS_Pos (4U)

◆ TIM_CR2_OIS1

#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk

Output Idle state 1 (OC1 output)

◆ TIM_CR2_OIS1_Msk

#define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos)

0x00000100

◆ TIM_CR2_OIS1_Pos

#define TIM_CR2_OIS1_Pos (8U)

◆ TIM_CR2_OIS1N

#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk

Output Idle state 1 (OC1N output)

◆ TIM_CR2_OIS1N_Msk

#define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos)

0x00000200

◆ TIM_CR2_OIS1N_Pos

#define TIM_CR2_OIS1N_Pos (9U)

◆ TIM_CR2_OIS2

#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk

Output Idle state 2 (OC2 output)

◆ TIM_CR2_OIS2_Msk

#define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos)

0x00000400

◆ TIM_CR2_OIS2_Pos

#define TIM_CR2_OIS2_Pos (10U)

◆ TIM_CR2_OIS2N

#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk

Output Idle state 2 (OC2N output)

◆ TIM_CR2_OIS2N_Msk

#define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos)

0x00000800

◆ TIM_CR2_OIS2N_Pos

#define TIM_CR2_OIS2N_Pos (11U)

◆ TIM_CR2_OIS3

#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk

Output Idle state 3 (OC3 output)

◆ TIM_CR2_OIS3_Msk

#define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos)

0x00001000

◆ TIM_CR2_OIS3_Pos

#define TIM_CR2_OIS3_Pos (12U)

◆ TIM_CR2_OIS3N

#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk

Output Idle state 3 (OC3N output)

◆ TIM_CR2_OIS3N_Msk

#define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos)

0x00002000

◆ TIM_CR2_OIS3N_Pos

#define TIM_CR2_OIS3N_Pos (13U)

◆ TIM_CR2_OIS4

#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk

Output Idle state 4 (OC4 output)

◆ TIM_CR2_OIS4_Msk

#define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos)

0x00004000

◆ TIM_CR2_OIS4_Pos

#define TIM_CR2_OIS4_Pos (14U)

◆ TIM_CR2_OIS5

#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk

Output Idle state 5 (OC5 output)

◆ TIM_CR2_OIS5_Msk

#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos)

0x00010000

◆ TIM_CR2_OIS5_Pos

#define TIM_CR2_OIS5_Pos (16U)

◆ TIM_CR2_OIS6

#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk

Output Idle state 6 (OC6 output)

◆ TIM_CR2_OIS6_Msk

#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos)

0x00040000

◆ TIM_CR2_OIS6_Pos

#define TIM_CR2_OIS6_Pos (18U)

◆ TIM_CR2_TI1S

#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk

TI1 Selection

◆ TIM_CR2_TI1S_Msk

#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos)

0x00000080

◆ TIM_CR2_TI1S_Pos

#define TIM_CR2_TI1S_Pos (7U)

◆ TIM_DCR_DBA

#define TIM_DCR_DBA TIM_DCR_DBA_Msk

DBA[4:0] bits (DMA Base Address)

◆ TIM_DCR_DBA_0

#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos)

0x00000001

◆ TIM_DCR_DBA_1

#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos)

0x00000002

◆ TIM_DCR_DBA_2

#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos)

0x00000004

◆ TIM_DCR_DBA_3

#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos)

0x00000008

◆ TIM_DCR_DBA_4

#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos)

0x00000010

◆ TIM_DCR_DBA_Msk

#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos)

0x0000001F

◆ TIM_DCR_DBA_Pos

#define TIM_DCR_DBA_Pos (0U)

◆ TIM_DCR_DBL

#define TIM_DCR_DBL TIM_DCR_DBL_Msk

DBL[4:0] bits (DMA Burst Length)

◆ TIM_DCR_DBL_0

#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos)

0x00000100

◆ TIM_DCR_DBL_1

#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos)

0x00000200

◆ TIM_DCR_DBL_2

#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos)

0x00000400

◆ TIM_DCR_DBL_3

#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos)

0x00000800

◆ TIM_DCR_DBL_4

#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos)

0x00001000

◆ TIM_DCR_DBL_Msk

#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos)

0x00001F00

◆ TIM_DCR_DBL_Pos

#define TIM_DCR_DBL_Pos (8U)

◆ TIM_DIER_BIE

#define TIM_DIER_BIE TIM_DIER_BIE_Msk

Break interrupt enable

◆ TIM_DIER_BIE_Msk

#define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos)

0x00000080

◆ TIM_DIER_BIE_Pos

#define TIM_DIER_BIE_Pos (7U)

◆ TIM_DIER_CC1DE

#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk

Capture/Compare 1 DMA request enable

◆ TIM_DIER_CC1DE_Msk

#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos)

0x00000200

◆ TIM_DIER_CC1DE_Pos

#define TIM_DIER_CC1DE_Pos (9U)

◆ TIM_DIER_CC1IE

#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk

Capture/Compare 1 interrupt enable

◆ TIM_DIER_CC1IE_Msk

#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos)

0x00000002

◆ TIM_DIER_CC1IE_Pos

#define TIM_DIER_CC1IE_Pos (1U)

◆ TIM_DIER_CC2DE

#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk

Capture/Compare 2 DMA request enable

◆ TIM_DIER_CC2DE_Msk

#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos)

0x00000400

◆ TIM_DIER_CC2DE_Pos

#define TIM_DIER_CC2DE_Pos (10U)

◆ TIM_DIER_CC2IE

#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk

Capture/Compare 2 interrupt enable

◆ TIM_DIER_CC2IE_Msk

#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos)

0x00000004

◆ TIM_DIER_CC2IE_Pos

#define TIM_DIER_CC2IE_Pos (2U)

◆ TIM_DIER_CC3DE

#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk

Capture/Compare 3 DMA request enable

◆ TIM_DIER_CC3DE_Msk

#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos)

0x00000800

◆ TIM_DIER_CC3DE_Pos

#define TIM_DIER_CC3DE_Pos (11U)

◆ TIM_DIER_CC3IE

#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk

Capture/Compare 3 interrupt enable

◆ TIM_DIER_CC3IE_Msk

#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos)

0x00000008

◆ TIM_DIER_CC3IE_Pos

#define TIM_DIER_CC3IE_Pos (3U)

◆ TIM_DIER_CC4DE

#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk

Capture/Compare 4 DMA request enable

◆ TIM_DIER_CC4DE_Msk

#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos)

0x00001000

◆ TIM_DIER_CC4DE_Pos

#define TIM_DIER_CC4DE_Pos (12U)

◆ TIM_DIER_CC4IE

#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk

Capture/Compare 4 interrupt enable

◆ TIM_DIER_CC4IE_Msk

#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos)

0x00000010

◆ TIM_DIER_CC4IE_Pos

#define TIM_DIER_CC4IE_Pos (4U)

◆ TIM_DIER_COMDE

#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk

COM DMA request enable

◆ TIM_DIER_COMDE_Msk

#define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos)

0x00002000

◆ TIM_DIER_COMDE_Pos

#define TIM_DIER_COMDE_Pos (13U)

◆ TIM_DIER_COMIE

#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk

COM interrupt enable

◆ TIM_DIER_COMIE_Msk

#define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos)

0x00000020

◆ TIM_DIER_COMIE_Pos

#define TIM_DIER_COMIE_Pos (5U)

◆ TIM_DIER_TDE

#define TIM_DIER_TDE TIM_DIER_TDE_Msk

Trigger DMA request enable

◆ TIM_DIER_TDE_Msk

#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos)

0x00004000

◆ TIM_DIER_TDE_Pos

#define TIM_DIER_TDE_Pos (14U)

◆ TIM_DIER_TIE

#define TIM_DIER_TIE TIM_DIER_TIE_Msk

Trigger interrupt enable

◆ TIM_DIER_TIE_Msk

#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos)

0x00000040

◆ TIM_DIER_TIE_Pos

#define TIM_DIER_TIE_Pos (6U)

◆ TIM_DIER_UDE

#define TIM_DIER_UDE TIM_DIER_UDE_Msk

Update DMA request enable

◆ TIM_DIER_UDE_Msk

#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos)

0x00000100

◆ TIM_DIER_UDE_Pos

#define TIM_DIER_UDE_Pos (8U)

◆ TIM_DIER_UIE

#define TIM_DIER_UIE TIM_DIER_UIE_Msk

Update interrupt enable

◆ TIM_DIER_UIE_Msk

#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos)

0x00000001

◆ TIM_DIER_UIE_Pos

#define TIM_DIER_UIE_Pos (0U)

◆ TIM_DMAR_DMAB

#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk

DMA register for burst accesses

◆ TIM_DMAR_DMAB_Msk

#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos)

0x0000FFFF

◆ TIM_DMAR_DMAB_Pos

#define TIM_DMAR_DMAB_Pos (0U)

◆ TIM_EGR_B2G

#define TIM_EGR_B2G TIM_EGR_B2G_Msk

Break 2 Generation

◆ TIM_EGR_B2G_Msk

#define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos)

0x00000100

◆ TIM_EGR_B2G_Pos

#define TIM_EGR_B2G_Pos (8U)

◆ TIM_EGR_BG

#define TIM_EGR_BG TIM_EGR_BG_Msk

Break Generation

◆ TIM_EGR_BG_Msk

#define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos)

0x00000080

◆ TIM_EGR_BG_Pos

#define TIM_EGR_BG_Pos (7U)

◆ TIM_EGR_CC1G

#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk

Capture/Compare 1 Generation

◆ TIM_EGR_CC1G_Msk

#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos)

0x00000002

◆ TIM_EGR_CC1G_Pos

#define TIM_EGR_CC1G_Pos (1U)

◆ TIM_EGR_CC2G

#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk

Capture/Compare 2 Generation

◆ TIM_EGR_CC2G_Msk

#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos)

0x00000004

◆ TIM_EGR_CC2G_Pos

#define TIM_EGR_CC2G_Pos (2U)

◆ TIM_EGR_CC3G

#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk

Capture/Compare 3 Generation

◆ TIM_EGR_CC3G_Msk

#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos)

0x00000008

◆ TIM_EGR_CC3G_Pos

#define TIM_EGR_CC3G_Pos (3U)

◆ TIM_EGR_CC4G

#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk

Capture/Compare 4 Generation

◆ TIM_EGR_CC4G_Msk

#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos)

0x00000010

◆ TIM_EGR_CC4G_Pos

#define TIM_EGR_CC4G_Pos (4U)

◆ TIM_EGR_COMG

#define TIM_EGR_COMG TIM_EGR_COMG_Msk

Capture/Compare Control Update Generation

◆ TIM_EGR_COMG_Msk

#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos)

0x00000020

◆ TIM_EGR_COMG_Pos

#define TIM_EGR_COMG_Pos (5U)

◆ TIM_EGR_TG

#define TIM_EGR_TG TIM_EGR_TG_Msk

Trigger Generation

◆ TIM_EGR_TG_Msk

#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos)

0x00000040

◆ TIM_EGR_TG_Pos

#define TIM_EGR_TG_Pos (6U)

◆ TIM_EGR_UG

#define TIM_EGR_UG TIM_EGR_UG_Msk

Update Generation

◆ TIM_EGR_UG_Msk

#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos)

0x00000001

◆ TIM_EGR_UG_Pos

#define TIM_EGR_UG_Pos (0U)

◆ TIM_PSC_PSC

#define TIM_PSC_PSC TIM_PSC_PSC_Msk

Prescaler Value

◆ TIM_PSC_PSC_Msk

#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos)

0x0000FFFF

◆ TIM_PSC_PSC_Pos

#define TIM_PSC_PSC_Pos (0U)

◆ TIM_RCR_REP

#define TIM_RCR_REP TIM_RCR_REP_Msk

Repetition Counter Value

◆ TIM_RCR_REP_Msk

#define TIM_RCR_REP_Msk (0xFFFFUL << TIM_RCR_REP_Pos)

0x0000FFFF

◆ TIM_RCR_REP_Pos

#define TIM_RCR_REP_Pos (0U)

◆ TIM_SMCR_ECE

#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk

External clock enable

◆ TIM_SMCR_ECE_Msk

#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos)

0x00004000

◆ TIM_SMCR_ECE_Pos

#define TIM_SMCR_ECE_Pos (14U)

◆ TIM_SMCR_ETF

#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk

ETF[3:0] bits (External trigger filter)

◆ TIM_SMCR_ETF_0

#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos)

0x00000100

◆ TIM_SMCR_ETF_1

#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos)

0x00000200

◆ TIM_SMCR_ETF_2

#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos)

0x00000400

◆ TIM_SMCR_ETF_3

#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos)

0x00000800

◆ TIM_SMCR_ETF_Msk

#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos)

0x00000F00

◆ TIM_SMCR_ETF_Pos

#define TIM_SMCR_ETF_Pos (8U)

◆ TIM_SMCR_ETP

#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk

External trigger polarity

◆ TIM_SMCR_ETP_Msk

#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos)

0x00008000

◆ TIM_SMCR_ETP_Pos

#define TIM_SMCR_ETP_Pos (15U)

◆ TIM_SMCR_ETPS

#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk

ETPS[1:0] bits (External trigger prescaler)

◆ TIM_SMCR_ETPS_0

#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos)

0x00001000

◆ TIM_SMCR_ETPS_1

#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos)

0x00002000

◆ TIM_SMCR_ETPS_Msk

#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos)

0x00003000

◆ TIM_SMCR_ETPS_Pos

#define TIM_SMCR_ETPS_Pos (12U)

◆ TIM_SMCR_MSM

#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk

Master/slave mode

◆ TIM_SMCR_MSM_Msk

#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos)

0x00000080

◆ TIM_SMCR_MSM_Pos

#define TIM_SMCR_MSM_Pos (7U)

◆ TIM_SMCR_OCCS

#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk

OCREF clear selection

◆ TIM_SMCR_OCCS_Msk

#define TIM_SMCR_OCCS_Msk (0x1UL << TIM_SMCR_OCCS_Pos)

0x00000008

◆ TIM_SMCR_OCCS_Pos

#define TIM_SMCR_OCCS_Pos (3U)

◆ TIM_SMCR_SMS

#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk

SMS[2:0] bits (Slave mode selection)

◆ TIM_SMCR_SMS_0

#define TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos)

0x00000001

◆ TIM_SMCR_SMS_1

#define TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos)

0x00000002

◆ TIM_SMCR_SMS_2

#define TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos)

0x00000004

◆ TIM_SMCR_SMS_3

#define TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos)

0x00010000

◆ TIM_SMCR_SMS_Msk

#define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos)

0x00010007

◆ TIM_SMCR_SMS_Pos

#define TIM_SMCR_SMS_Pos (0U)

◆ TIM_SMCR_TS

#define TIM_SMCR_TS TIM_SMCR_TS_Msk

TS[2:0] bits (Trigger selection)

◆ TIM_SMCR_TS_0

#define TIM_SMCR_TS_0 (0x00001UL << TIM_SMCR_TS_Pos)

0x00000010

◆ TIM_SMCR_TS_1

#define TIM_SMCR_TS_1 (0x00002UL << TIM_SMCR_TS_Pos)

0x00000020

◆ TIM_SMCR_TS_2

#define TIM_SMCR_TS_2 (0x00004UL << TIM_SMCR_TS_Pos)

0x00000040

◆ TIM_SMCR_TS_3

#define TIM_SMCR_TS_3 (0x10000UL << TIM_SMCR_TS_Pos)

0x00100000

◆ TIM_SMCR_TS_4

#define TIM_SMCR_TS_4 (0x20000UL << TIM_SMCR_TS_Pos)

0x00200000

◆ TIM_SMCR_TS_Msk

#define TIM_SMCR_TS_Msk (0x30007UL << TIM_SMCR_TS_Pos)

0x00300070

◆ TIM_SMCR_TS_Pos

#define TIM_SMCR_TS_Pos (4U)

◆ TIM_SR_B2IF

#define TIM_SR_B2IF TIM_SR_B2IF_Msk

Break 2 interrupt Flag

◆ TIM_SR_B2IF_Msk

#define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos)

0x00000100

◆ TIM_SR_B2IF_Pos

#define TIM_SR_B2IF_Pos (8U)

◆ TIM_SR_BIF

#define TIM_SR_BIF TIM_SR_BIF_Msk

Break interrupt Flag

◆ TIM_SR_BIF_Msk

#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos)

0x00000080

◆ TIM_SR_BIF_Pos

#define TIM_SR_BIF_Pos (7U)

◆ TIM_SR_CC1IF

#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk

Capture/Compare 1 interrupt Flag

◆ TIM_SR_CC1IF_Msk

#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos)

0x00000002

◆ TIM_SR_CC1IF_Pos

#define TIM_SR_CC1IF_Pos (1U)

◆ TIM_SR_CC1OF

#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk

Capture/Compare 1 Overcapture Flag

◆ TIM_SR_CC1OF_Msk

#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos)

0x00000200

◆ TIM_SR_CC1OF_Pos

#define TIM_SR_CC1OF_Pos (9U)

◆ TIM_SR_CC2IF

#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk

Capture/Compare 2 interrupt Flag

◆ TIM_SR_CC2IF_Msk

#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos)

0x00000004

◆ TIM_SR_CC2IF_Pos

#define TIM_SR_CC2IF_Pos (2U)

◆ TIM_SR_CC2OF

#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk

Capture/Compare 2 Overcapture Flag

◆ TIM_SR_CC2OF_Msk

#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos)

0x00000400

◆ TIM_SR_CC2OF_Pos

#define TIM_SR_CC2OF_Pos (10U)

◆ TIM_SR_CC3IF

#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk

Capture/Compare 3 interrupt Flag

◆ TIM_SR_CC3IF_Msk

#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos)

0x00000008

◆ TIM_SR_CC3IF_Pos

#define TIM_SR_CC3IF_Pos (3U)

◆ TIM_SR_CC3OF

#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk

Capture/Compare 3 Overcapture Flag

◆ TIM_SR_CC3OF_Msk

#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos)

0x00000800

◆ TIM_SR_CC3OF_Pos

#define TIM_SR_CC3OF_Pos (11U)

◆ TIM_SR_CC4IF

#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk

Capture/Compare 4 interrupt Flag

◆ TIM_SR_CC4IF_Msk

#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos)

0x00000010

◆ TIM_SR_CC4IF_Pos

#define TIM_SR_CC4IF_Pos (4U)

◆ TIM_SR_CC4OF

#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk

Capture/Compare 4 Overcapture Flag

◆ TIM_SR_CC4OF_Msk

#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos)

0x00001000

◆ TIM_SR_CC4OF_Pos

#define TIM_SR_CC4OF_Pos (12U)

◆ TIM_SR_CC5IF

#define TIM_SR_CC5IF TIM_SR_CC5IF_Msk

Capture/Compare 5 interrupt Flag

◆ TIM_SR_CC5IF_Msk

#define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos)

0x00010000

◆ TIM_SR_CC5IF_Pos

#define TIM_SR_CC5IF_Pos (16U)

◆ TIM_SR_CC6IF

#define TIM_SR_CC6IF TIM_SR_CC6IF_Msk

Capture/Compare 6 interrupt Flag

◆ TIM_SR_CC6IF_Msk

#define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos)

0x00020000

◆ TIM_SR_CC6IF_Pos

#define TIM_SR_CC6IF_Pos (17U)

◆ TIM_SR_COMIF

#define TIM_SR_COMIF TIM_SR_COMIF_Msk

COM interrupt Flag

◆ TIM_SR_COMIF_Msk

#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos)

0x00000020

◆ TIM_SR_COMIF_Pos

#define TIM_SR_COMIF_Pos (5U)

◆ TIM_SR_SBIF

#define TIM_SR_SBIF TIM_SR_SBIF_Msk

System Break interrupt Flag

◆ TIM_SR_SBIF_Msk

#define TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos)

0x00002000

◆ TIM_SR_SBIF_Pos

#define TIM_SR_SBIF_Pos (13U)

◆ TIM_SR_TIF

#define TIM_SR_TIF TIM_SR_TIF_Msk

Trigger interrupt Flag

◆ TIM_SR_TIF_Msk

#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos)

0x00000040

◆ TIM_SR_TIF_Pos

#define TIM_SR_TIF_Pos (6U)

◆ TIM_SR_UIF

#define TIM_SR_UIF TIM_SR_UIF_Msk

Update interrupt Flag

◆ TIM_SR_UIF_Msk

#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos)

0x00000001

◆ TIM_SR_UIF_Pos

#define TIM_SR_UIF_Pos (0U)

◆ TIM_TISEL_TI1SEL

#define TIM_TISEL_TI1SEL TIM_TISEL_TI1SEL_Msk

TI1SEL[3:0] bits (TIM TI1 SEL)

◆ TIM_TISEL_TI1SEL_0

#define TIM_TISEL_TI1SEL_0 (0x1UL << TIM_TISEL_TI1SEL_Pos)

0x00000001

◆ TIM_TISEL_TI1SEL_1

#define TIM_TISEL_TI1SEL_1 (0x2UL << TIM_TISEL_TI1SEL_Pos)

0x00000002

◆ TIM_TISEL_TI1SEL_2

#define TIM_TISEL_TI1SEL_2 (0x4UL << TIM_TISEL_TI1SEL_Pos)

0x00000004

◆ TIM_TISEL_TI1SEL_3

#define TIM_TISEL_TI1SEL_3 (0x8UL << TIM_TISEL_TI1SEL_Pos)

0x00000008

◆ TIM_TISEL_TI1SEL_Msk

#define TIM_TISEL_TI1SEL_Msk (0xFUL << TIM_TISEL_TI1SEL_Pos)

0x0000000F

◆ TIM_TISEL_TI1SEL_Pos

#define TIM_TISEL_TI1SEL_Pos (0U)

◆ TIM_TISEL_TI2SEL

#define TIM_TISEL_TI2SEL TIM_TISEL_TI2SEL_Msk

TI2SEL[3:0] bits (TIM TI2 SEL)

◆ TIM_TISEL_TI2SEL_0

#define TIM_TISEL_TI2SEL_0 (0x1UL << TIM_TISEL_TI2SEL_Pos)

0x00000100

◆ TIM_TISEL_TI2SEL_1

#define TIM_TISEL_TI2SEL_1 (0x2UL << TIM_TISEL_TI2SEL_Pos)

0x00000200

◆ TIM_TISEL_TI2SEL_2

#define TIM_TISEL_TI2SEL_2 (0x4UL << TIM_TISEL_TI2SEL_Pos)

0x00000400

◆ TIM_TISEL_TI2SEL_3

#define TIM_TISEL_TI2SEL_3 (0x8UL << TIM_TISEL_TI2SEL_Pos)

0x00000800

◆ TIM_TISEL_TI2SEL_Msk

#define TIM_TISEL_TI2SEL_Msk (0xFUL << TIM_TISEL_TI2SEL_Pos)

0x00000F00

◆ TIM_TISEL_TI2SEL_Pos

#define TIM_TISEL_TI2SEL_Pos (8U)

◆ TIM_TISEL_TI3SEL

#define TIM_TISEL_TI3SEL TIM_TISEL_TI3SEL_Msk

TI3SEL[3:0] bits (TIM TI3 SEL)

◆ TIM_TISEL_TI3SEL_0

#define TIM_TISEL_TI3SEL_0 (0x1UL << TIM_TISEL_TI3SEL_Pos)

0x00010000

◆ TIM_TISEL_TI3SEL_1

#define TIM_TISEL_TI3SEL_1 (0x2UL << TIM_TISEL_TI3SEL_Pos)

0x00020000

◆ TIM_TISEL_TI3SEL_2

#define TIM_TISEL_TI3SEL_2 (0x4UL << TIM_TISEL_TI3SEL_Pos)

0x00040000

◆ TIM_TISEL_TI3SEL_3

#define TIM_TISEL_TI3SEL_3 (0x8UL << TIM_TISEL_TI3SEL_Pos)

0x00080000

◆ TIM_TISEL_TI3SEL_Msk

#define TIM_TISEL_TI3SEL_Msk (0xFUL << TIM_TISEL_TI3SEL_Pos)

0x000F0000

◆ TIM_TISEL_TI3SEL_Pos

#define TIM_TISEL_TI3SEL_Pos (16U)

◆ TIM_TISEL_TI4SEL

#define TIM_TISEL_TI4SEL TIM_TISEL_TI4SEL_Msk

TI4SEL[3:0] bits (TIM TI4 SEL)

◆ TIM_TISEL_TI4SEL_0

#define TIM_TISEL_TI4SEL_0 (0x1UL << TIM_TISEL_TI4SEL_Pos)

0x01000000

◆ TIM_TISEL_TI4SEL_1

#define TIM_TISEL_TI4SEL_1 (0x2UL << TIM_TISEL_TI4SEL_Pos)

0x02000000

◆ TIM_TISEL_TI4SEL_2

#define TIM_TISEL_TI4SEL_2 (0x4UL << TIM_TISEL_TI4SEL_Pos)

0x04000000

◆ TIM_TISEL_TI4SEL_3

#define TIM_TISEL_TI4SEL_3 (0x8UL << TIM_TISEL_TI4SEL_Pos)

0x08000000

◆ TIM_TISEL_TI4SEL_Msk

#define TIM_TISEL_TI4SEL_Msk (0xFUL << TIM_TISEL_TI4SEL_Pos)

0x0F000000

◆ TIM_TISEL_TI4SEL_Pos

#define TIM_TISEL_TI4SEL_Pos (24U)

◆ USART_BRR_BRR

#define USART_BRR_BRR ((uint16_t)0xFFFF)

USART Baud rate register [15:0]

◆ USART_CR1_CMIE

#define USART_CR1_CMIE USART_CR1_CMIE_Msk

Character match interrupt enable

◆ USART_CR1_CMIE_Msk

#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos)

0x00004000

◆ USART_CR1_CMIE_Pos

#define USART_CR1_CMIE_Pos (14U)

◆ USART_CR1_DEAT

#define USART_CR1_DEAT USART_CR1_DEAT_Msk

DEAT[4:0] bits (Driver Enable Assertion Time)

◆ USART_CR1_DEAT_0

#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos)

0x00200000

◆ USART_CR1_DEAT_1

#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos)

0x00400000

◆ USART_CR1_DEAT_2

#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos)

0x00800000

◆ USART_CR1_DEAT_3

#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos)

0x01000000

◆ USART_CR1_DEAT_4

#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos)

0x02000000

◆ USART_CR1_DEAT_Msk

#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos)

0x03E00000

◆ USART_CR1_DEAT_Pos

#define USART_CR1_DEAT_Pos (21U)

◆ USART_CR1_DEDT

#define USART_CR1_DEDT USART_CR1_DEDT_Msk

DEDT[4:0] bits (Driver Enable Deassertion Time)

◆ USART_CR1_DEDT_0

#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos)

0x00010000

◆ USART_CR1_DEDT_1

#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos)

0x00020000

◆ USART_CR1_DEDT_2

#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos)

0x00040000

◆ USART_CR1_DEDT_3

#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos)

0x00080000

◆ USART_CR1_DEDT_4

#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos)

0x00100000

◆ USART_CR1_DEDT_Msk

#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos)

0x001F0000

◆ USART_CR1_DEDT_Pos

#define USART_CR1_DEDT_Pos (16U)

◆ USART_CR1_EOBIE

#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk

End of Block interrupt enable

◆ USART_CR1_EOBIE_Msk

#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos)

0x08000000

◆ USART_CR1_EOBIE_Pos

#define USART_CR1_EOBIE_Pos (27U)

◆ USART_CR1_FIFOEN

#define USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk

FIFO mode enable

◆ USART_CR1_FIFOEN_Msk

#define USART_CR1_FIFOEN_Msk (0x1UL << USART_CR1_FIFOEN_Pos)

0x20000000

◆ USART_CR1_FIFOEN_Pos

#define USART_CR1_FIFOEN_Pos (29U)

◆ USART_CR1_IDLEIE

#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk

IDLE Interrupt Enable

◆ USART_CR1_IDLEIE_Msk

#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos)

0x00000010

◆ USART_CR1_IDLEIE_Pos

#define USART_CR1_IDLEIE_Pos (4U)

◆ USART_CR1_M

#define USART_CR1_M USART_CR1_M_Msk

Word length

◆ USART_CR1_M0

#define USART_CR1_M0 USART_CR1_M0_Msk

Word length - Bit 0

◆ USART_CR1_M0_Msk

#define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos)

0x00001000

◆ USART_CR1_M0_Pos

#define USART_CR1_M0_Pos (12U)

◆ USART_CR1_M1

#define USART_CR1_M1 USART_CR1_M1_Msk

Word length - Bit 1

◆ USART_CR1_M1_Msk

#define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos)

0x10000000

◆ USART_CR1_M1_Pos

#define USART_CR1_M1_Pos (28U)

◆ USART_CR1_M_Msk

#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos)

0x10001000

◆ USART_CR1_M_Pos

#define USART_CR1_M_Pos (12U)

◆ USART_CR1_MME

#define USART_CR1_MME USART_CR1_MME_Msk

Mute Mode Enable

◆ USART_CR1_MME_Msk

#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos)

0x00002000

◆ USART_CR1_MME_Pos

#define USART_CR1_MME_Pos (13U)

◆ USART_CR1_OVER8

#define USART_CR1_OVER8 USART_CR1_OVER8_Msk

Oversampling by 8-bit or 16-bit mode

◆ USART_CR1_OVER8_Msk

#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos)

0x00008000

◆ USART_CR1_OVER8_Pos

#define USART_CR1_OVER8_Pos (15U)

◆ USART_CR1_PCE

#define USART_CR1_PCE USART_CR1_PCE_Msk

Parity Control Enable

◆ USART_CR1_PCE_Msk

#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos)

0x00000400

◆ USART_CR1_PCE_Pos

#define USART_CR1_PCE_Pos (10U)

◆ USART_CR1_PEIE

#define USART_CR1_PEIE USART_CR1_PEIE_Msk

PE Interrupt Enable

◆ USART_CR1_PEIE_Msk

#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos)

0x00000100

◆ USART_CR1_PEIE_Pos

#define USART_CR1_PEIE_Pos (8U)

◆ USART_CR1_PS

#define USART_CR1_PS USART_CR1_PS_Msk

Parity Selection

◆ USART_CR1_PS_Msk

#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos)

0x00000200

◆ USART_CR1_PS_Pos

#define USART_CR1_PS_Pos (9U)

◆ USART_CR1_RE

#define USART_CR1_RE USART_CR1_RE_Msk

Receiver Enable

◆ USART_CR1_RE_Msk

#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos)

0x00000004

◆ USART_CR1_RE_Pos

#define USART_CR1_RE_Pos (2U)

◆ USART_CR1_RTOIE

#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk

Receive Time Out interrupt enable

◆ USART_CR1_RTOIE_Msk

#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos)

0x04000000

◆ USART_CR1_RTOIE_Pos

#define USART_CR1_RTOIE_Pos (26U)

◆ USART_CR1_RXFFIE

#define USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk

RXFIFO Full interrupt enable

◆ USART_CR1_RXFFIE_Msk

#define USART_CR1_RXFFIE_Msk (0x1UL << USART_CR1_RXFFIE_Pos)

0x80000000

◆ USART_CR1_RXFFIE_Pos

#define USART_CR1_RXFFIE_Pos (31U)

◆ USART_CR1_RXNEIE_RXFNEIE

#define USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE_Msk

RXNE/RXFIFO not empty Interrupt Enable

◆ USART_CR1_RXNEIE_RXFNEIE_Msk

#define USART_CR1_RXNEIE_RXFNEIE_Msk (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos)

0x00000020

◆ USART_CR1_RXNEIE_RXFNEIE_Pos

#define USART_CR1_RXNEIE_RXFNEIE_Pos (5U)

◆ USART_CR1_TCIE

#define USART_CR1_TCIE USART_CR1_TCIE_Msk

Transmission Complete Interrupt Enable

◆ USART_CR1_TCIE_Msk

#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos)

0x00000040

◆ USART_CR1_TCIE_Pos

#define USART_CR1_TCIE_Pos (6U)

◆ USART_CR1_TE

#define USART_CR1_TE USART_CR1_TE_Msk

Transmitter Enable

◆ USART_CR1_TE_Msk

#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos)

0x00000008

◆ USART_CR1_TE_Pos

#define USART_CR1_TE_Pos (3U)

◆ USART_CR1_TXEIE_TXFNFIE

#define USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE_Msk

TXE/TXFIFO not full Interrupt Enable

◆ USART_CR1_TXEIE_TXFNFIE_Msk

#define USART_CR1_TXEIE_TXFNFIE_Msk (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos)

0x00000080

◆ USART_CR1_TXEIE_TXFNFIE_Pos

#define USART_CR1_TXEIE_TXFNFIE_Pos (7U)

◆ USART_CR1_TXFEIE

#define USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk

TXFIFO empty interrupt enable

◆ USART_CR1_TXFEIE_Msk

#define USART_CR1_TXFEIE_Msk (0x1UL << USART_CR1_TXFEIE_Pos)

0x40000000

◆ USART_CR1_TXFEIE_Pos

#define USART_CR1_TXFEIE_Pos (30U)

◆ USART_CR1_UE

#define USART_CR1_UE USART_CR1_UE_Msk

USART Enable

◆ USART_CR1_UE_Msk

#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos)

0x00000001

◆ USART_CR1_UE_Pos

#define USART_CR1_UE_Pos (0U)

◆ USART_CR1_UESM

#define USART_CR1_UESM USART_CR1_UESM_Msk

USART Enable in STOP Mode

◆ USART_CR1_UESM_Msk

#define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos)

0x00000002

◆ USART_CR1_UESM_Pos

#define USART_CR1_UESM_Pos (1U)

◆ USART_CR1_WAKE

#define USART_CR1_WAKE USART_CR1_WAKE_Msk

Receiver Wakeup method

◆ USART_CR1_WAKE_Msk

#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos)

0x00000800

◆ USART_CR1_WAKE_Pos

#define USART_CR1_WAKE_Pos (11U)

◆ USART_CR2_ABREN

#define USART_CR2_ABREN USART_CR2_ABREN_Msk

Auto Baud-Rate Enable

◆ USART_CR2_ABREN_Msk

#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos)

0x00100000

◆ USART_CR2_ABREN_Pos

#define USART_CR2_ABREN_Pos (20U)

◆ USART_CR2_ABRMODE

#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk

ABRMOD[1:0] bits (Auto Baud-Rate Mode)

◆ USART_CR2_ABRMODE_0

#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos)

0x00200000

◆ USART_CR2_ABRMODE_1

#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos)

0x00400000

◆ USART_CR2_ABRMODE_Msk

#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos)

0x00600000

◆ USART_CR2_ABRMODE_Pos

#define USART_CR2_ABRMODE_Pos (21U)

◆ USART_CR2_ADD

#define USART_CR2_ADD USART_CR2_ADD_Msk

Address of the USART node

◆ USART_CR2_ADD_Msk

#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos)

0xFF000000

◆ USART_CR2_ADD_Pos

#define USART_CR2_ADD_Pos (24U)

◆ USART_CR2_ADDM7

#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk

7-bit or 4-bit Address Detection

◆ USART_CR2_ADDM7_Msk

#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos)

0x00000010

◆ USART_CR2_ADDM7_Pos

#define USART_CR2_ADDM7_Pos (4U)

◆ USART_CR2_CLKEN

#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk

Clock Enable

◆ USART_CR2_CLKEN_Msk

#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos)

0x00000800

◆ USART_CR2_CLKEN_Pos

#define USART_CR2_CLKEN_Pos (11U)

◆ USART_CR2_CPHA

#define USART_CR2_CPHA USART_CR2_CPHA_Msk

Clock Phase

◆ USART_CR2_CPHA_Msk

#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos)

0x00000200

◆ USART_CR2_CPHA_Pos

#define USART_CR2_CPHA_Pos (9U)

◆ USART_CR2_CPOL

#define USART_CR2_CPOL USART_CR2_CPOL_Msk

Clock Polarity

◆ USART_CR2_CPOL_Msk

#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos)

0x00000400

◆ USART_CR2_CPOL_Pos

#define USART_CR2_CPOL_Pos (10U)

◆ USART_CR2_DATAINV

#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk

Binary data inversion

◆ USART_CR2_DATAINV_Msk

#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos)

0x00040000

◆ USART_CR2_DATAINV_Pos

#define USART_CR2_DATAINV_Pos (18U)

◆ USART_CR2_DIS_NSS

#define USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk

NSS input pin disable for SPI slave selection

◆ USART_CR2_DIS_NSS_Msk

#define USART_CR2_DIS_NSS_Msk (0x1UL << USART_CR2_DIS_NSS_Pos)

0x00000008

◆ USART_CR2_DIS_NSS_Pos

#define USART_CR2_DIS_NSS_Pos (3U)

◆ USART_CR2_LBCL

#define USART_CR2_LBCL USART_CR2_LBCL_Msk

Last Bit Clock pulse

◆ USART_CR2_LBCL_Msk

#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos)

0x00000100

◆ USART_CR2_LBCL_Pos

#define USART_CR2_LBCL_Pos (8U)

◆ USART_CR2_LBDIE

#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk

LIN Break Detection Interrupt Enable

◆ USART_CR2_LBDIE_Msk

#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos)

0x00000040

◆ USART_CR2_LBDIE_Pos

#define USART_CR2_LBDIE_Pos (6U)

◆ USART_CR2_LBDL

#define USART_CR2_LBDL USART_CR2_LBDL_Msk

LIN Break Detection Length

◆ USART_CR2_LBDL_Msk

#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos)

0x00000020

◆ USART_CR2_LBDL_Pos

#define USART_CR2_LBDL_Pos (5U)

◆ USART_CR2_LINEN

#define USART_CR2_LINEN USART_CR2_LINEN_Msk

LIN mode enable

◆ USART_CR2_LINEN_Msk

#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos)

0x00004000

◆ USART_CR2_LINEN_Pos

#define USART_CR2_LINEN_Pos (14U)

◆ USART_CR2_MSBFIRST

#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk

Most Significant Bit First

◆ USART_CR2_MSBFIRST_Msk

#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos)

0x00080000

◆ USART_CR2_MSBFIRST_Pos

#define USART_CR2_MSBFIRST_Pos (19U)

◆ USART_CR2_RTOEN

#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk

Receiver Time-Out enable

◆ USART_CR2_RTOEN_Msk

#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos)

0x00800000

◆ USART_CR2_RTOEN_Pos

#define USART_CR2_RTOEN_Pos (23U)

◆ USART_CR2_RXINV

#define USART_CR2_RXINV USART_CR2_RXINV_Msk

RX pin active level inversion

◆ USART_CR2_RXINV_Msk

#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos)

0x00010000

◆ USART_CR2_RXINV_Pos

#define USART_CR2_RXINV_Pos (16U)

◆ USART_CR2_SLVEN

#define USART_CR2_SLVEN USART_CR2_SLVEN_Msk

Synchronous Slave mode enable

◆ USART_CR2_SLVEN_Msk

#define USART_CR2_SLVEN_Msk (0x1UL << USART_CR2_SLVEN_Pos)

0x00000001

◆ USART_CR2_SLVEN_Pos

#define USART_CR2_SLVEN_Pos (0U)

◆ USART_CR2_STOP

#define USART_CR2_STOP USART_CR2_STOP_Msk

STOP[1:0] bits (STOP bits)

◆ USART_CR2_STOP_0

#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos)

0x00001000

◆ USART_CR2_STOP_1

#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos)

0x00002000

◆ USART_CR2_STOP_Msk

#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos)

0x00003000

◆ USART_CR2_STOP_Pos

#define USART_CR2_STOP_Pos (12U)

◆ USART_CR2_SWAP

#define USART_CR2_SWAP USART_CR2_SWAP_Msk

SWAP TX/RX pins

◆ USART_CR2_SWAP_Msk

#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos)

0x00008000

◆ USART_CR2_SWAP_Pos

#define USART_CR2_SWAP_Pos (15U)

◆ USART_CR2_TXINV

#define USART_CR2_TXINV USART_CR2_TXINV_Msk

TX pin active level inversion

◆ USART_CR2_TXINV_Msk

#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos)

0x00020000

◆ USART_CR2_TXINV_Pos

#define USART_CR2_TXINV_Pos (17U)

◆ USART_CR3_CTSE

#define USART_CR3_CTSE USART_CR3_CTSE_Msk

CTS Enable

◆ USART_CR3_CTSE_Msk

#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos)

0x00000200

◆ USART_CR3_CTSE_Pos

#define USART_CR3_CTSE_Pos (9U)

◆ USART_CR3_CTSIE

#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk

CTS Interrupt Enable

◆ USART_CR3_CTSIE_Msk

#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos)

0x00000400

◆ USART_CR3_CTSIE_Pos

#define USART_CR3_CTSIE_Pos (10U)

◆ USART_CR3_DDRE

#define USART_CR3_DDRE USART_CR3_DDRE_Msk

DMA Disable on Reception Error

◆ USART_CR3_DDRE_Msk

#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos)

0x00002000

◆ USART_CR3_DDRE_Pos

#define USART_CR3_DDRE_Pos (13U)

◆ USART_CR3_DEM

#define USART_CR3_DEM USART_CR3_DEM_Msk

Driver Enable Mode

◆ USART_CR3_DEM_Msk

#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos)

0x00004000

◆ USART_CR3_DEM_Pos

#define USART_CR3_DEM_Pos (14U)

◆ USART_CR3_DEP

#define USART_CR3_DEP USART_CR3_DEP_Msk

Driver Enable Polarity Selection

◆ USART_CR3_DEP_Msk

#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos)

0x00008000

◆ USART_CR3_DEP_Pos

#define USART_CR3_DEP_Pos (15U)

◆ USART_CR3_DMAR

#define USART_CR3_DMAR USART_CR3_DMAR_Msk

DMA Enable Receiver

◆ USART_CR3_DMAR_Msk

#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos)

0x00000040

◆ USART_CR3_DMAR_Pos

#define USART_CR3_DMAR_Pos (6U)

◆ USART_CR3_DMAT

#define USART_CR3_DMAT USART_CR3_DMAT_Msk

DMA Enable Transmitter

◆ USART_CR3_DMAT_Msk

#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos)

0x00000080

◆ USART_CR3_DMAT_Pos

#define USART_CR3_DMAT_Pos (7U)

◆ USART_CR3_EIE

#define USART_CR3_EIE USART_CR3_EIE_Msk

Error Interrupt Enable

◆ USART_CR3_EIE_Msk

#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos)

0x00000001

◆ USART_CR3_EIE_Pos

#define USART_CR3_EIE_Pos (0U)

◆ USART_CR3_HDSEL

#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk

Half-Duplex Selection

◆ USART_CR3_HDSEL_Msk

#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos)

0x00000008

◆ USART_CR3_HDSEL_Pos

#define USART_CR3_HDSEL_Pos (3U)

◆ USART_CR3_IREN

#define USART_CR3_IREN USART_CR3_IREN_Msk

IrDA mode Enable

◆ USART_CR3_IREN_Msk

#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos)

0x00000002

◆ USART_CR3_IREN_Pos

#define USART_CR3_IREN_Pos (1U)

◆ USART_CR3_IRLP

#define USART_CR3_IRLP USART_CR3_IRLP_Msk

IrDA Low-Power

◆ USART_CR3_IRLP_Msk

#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos)

0x00000004

◆ USART_CR3_IRLP_Pos

#define USART_CR3_IRLP_Pos (2U)

◆ USART_CR3_NACK

#define USART_CR3_NACK USART_CR3_NACK_Msk

SmartCard NACK enable

◆ USART_CR3_NACK_Msk

#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos)

0x00000010

◆ USART_CR3_NACK_Pos

#define USART_CR3_NACK_Pos (4U)

◆ USART_CR3_ONEBIT

#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk

One sample bit method enable

◆ USART_CR3_ONEBIT_Msk

#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos)

0x00000800

◆ USART_CR3_ONEBIT_Pos

#define USART_CR3_ONEBIT_Pos (11U)

◆ USART_CR3_OVRDIS

#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk

Overrun Disable

◆ USART_CR3_OVRDIS_Msk

#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos)

0x00001000

◆ USART_CR3_OVRDIS_Pos

#define USART_CR3_OVRDIS_Pos (12U)

◆ USART_CR3_RTSE

#define USART_CR3_RTSE USART_CR3_RTSE_Msk

RTS Enable

◆ USART_CR3_RTSE_Msk

#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos)

0x00000100

◆ USART_CR3_RTSE_Pos

#define USART_CR3_RTSE_Pos (8U)

◆ USART_CR3_RXFTCFG

#define USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk

RXFIFO FIFO threshold configuration

◆ USART_CR3_RXFTCFG_0

#define USART_CR3_RXFTCFG_0 (0x1UL << USART_CR3_RXFTCFG_Pos)

0x02000000

◆ USART_CR3_RXFTCFG_1

#define USART_CR3_RXFTCFG_1 (0x2UL << USART_CR3_RXFTCFG_Pos)

0x04000000

◆ USART_CR3_RXFTCFG_2

#define USART_CR3_RXFTCFG_2 (0x4UL << USART_CR3_RXFTCFG_Pos)

0x08000000

◆ USART_CR3_RXFTCFG_Msk

#define USART_CR3_RXFTCFG_Msk (0x7UL << USART_CR3_RXFTCFG_Pos)

0x0E000000

◆ USART_CR3_RXFTCFG_Pos

#define USART_CR3_RXFTCFG_Pos (25U)

◆ USART_CR3_RXFTIE

#define USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk

RXFIFO threshold interrupt enable

◆ USART_CR3_RXFTIE_Msk

#define USART_CR3_RXFTIE_Msk (0x1UL << USART_CR3_RXFTIE_Pos)

0x10000000

◆ USART_CR3_RXFTIE_Pos

#define USART_CR3_RXFTIE_Pos (28U)

◆ USART_CR3_SCARCNT

#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk

SCARCNT[2:0] bits (SmartCard Auto-Retry Count)

◆ USART_CR3_SCARCNT_0

#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos)

0x00020000

◆ USART_CR3_SCARCNT_1

#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos)

0x00040000

◆ USART_CR3_SCARCNT_2

#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos)

0x00080000

◆ USART_CR3_SCARCNT_Msk

#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos)

0x000E0000

◆ USART_CR3_SCARCNT_Pos

#define USART_CR3_SCARCNT_Pos (17U)

◆ USART_CR3_SCEN

#define USART_CR3_SCEN USART_CR3_SCEN_Msk

SmartCard mode enable

◆ USART_CR3_SCEN_Msk

#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos)

0x00000020

◆ USART_CR3_SCEN_Pos

#define USART_CR3_SCEN_Pos (5U)

◆ USART_CR3_TCBGTIE

#define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk

Transmission Complete Before Guard Time Interrupt Enable

◆ USART_CR3_TCBGTIE_Msk

#define USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos)

0x01000000

◆ USART_CR3_TCBGTIE_Pos

#define USART_CR3_TCBGTIE_Pos (24U)

◆ USART_CR3_TXFTCFG

#define USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk

TXFIFO threshold configuration

◆ USART_CR3_TXFTCFG_0

#define USART_CR3_TXFTCFG_0 (0x1UL << USART_CR3_TXFTCFG_Pos)

0x20000000

◆ USART_CR3_TXFTCFG_1

#define USART_CR3_TXFTCFG_1 (0x2UL << USART_CR3_TXFTCFG_Pos)

0x40000000

◆ USART_CR3_TXFTCFG_2

#define USART_CR3_TXFTCFG_2 (0x4UL << USART_CR3_TXFTCFG_Pos)

0x80000000

◆ USART_CR3_TXFTCFG_Msk

#define USART_CR3_TXFTCFG_Msk (0x7UL << USART_CR3_TXFTCFG_Pos)

0xE0000000

◆ USART_CR3_TXFTCFG_Pos

#define USART_CR3_TXFTCFG_Pos (29U)

◆ USART_CR3_TXFTIE

#define USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk

TXFIFO threshold interrupt enable

◆ USART_CR3_TXFTIE_Msk

#define USART_CR3_TXFTIE_Msk (0x1UL << USART_CR3_TXFTIE_Pos)

0x00800000

◆ USART_CR3_TXFTIE_Pos

#define USART_CR3_TXFTIE_Pos (23U)

◆ USART_CR3_WUFIE

#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk

Wake Up Interrupt Enable

◆ USART_CR3_WUFIE_Msk

#define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos)

0x00400000

◆ USART_CR3_WUFIE_Pos

#define USART_CR3_WUFIE_Pos (22U)

◆ USART_CR3_WUS

#define USART_CR3_WUS USART_CR3_WUS_Msk

WUS[1:0] bits (Wake UP Interrupt Flag Selection)

◆ USART_CR3_WUS_0

#define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos)

0x00100000

◆ USART_CR3_WUS_1

#define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos)

0x00200000

◆ USART_CR3_WUS_Msk

#define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos)

0x00300000

◆ USART_CR3_WUS_Pos

#define USART_CR3_WUS_Pos (20U)

◆ USART_GTPR_GT

#define USART_GTPR_GT USART_GTPR_GT_Msk

GT[7:0] bits (Guard time value)

◆ USART_GTPR_GT_Msk

#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos)

0x0000FF00

◆ USART_GTPR_GT_Pos

#define USART_GTPR_GT_Pos (8U)

◆ USART_GTPR_PSC

#define USART_GTPR_PSC USART_GTPR_PSC_Msk

PSC[7:0] bits (Prescaler value)

◆ USART_GTPR_PSC_Msk

#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos)

0x000000FF

◆ USART_GTPR_PSC_Pos

#define USART_GTPR_PSC_Pos (0U)

◆ USART_ICR_CMCF

#define USART_ICR_CMCF USART_ICR_CMCF_Msk

Character Match Clear Flag

◆ USART_ICR_CMCF_Msk

#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos)

0x00020000

◆ USART_ICR_CMCF_Pos

#define USART_ICR_CMCF_Pos (17U)

◆ USART_ICR_CTSCF

#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk

CTS Interrupt Clear Flag

◆ USART_ICR_CTSCF_Msk

#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos)

0x00000200

◆ USART_ICR_CTSCF_Pos

#define USART_ICR_CTSCF_Pos (9U)

◆ USART_ICR_EOBCF

#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk

End Of Block Clear Flag

◆ USART_ICR_EOBCF_Msk

#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos)

0x00001000

◆ USART_ICR_EOBCF_Pos

#define USART_ICR_EOBCF_Pos (12U)

◆ USART_ICR_FECF

#define USART_ICR_FECF USART_ICR_FECF_Msk

Framing Error Clear Flag

◆ USART_ICR_FECF_Msk

#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos)

0x00000002

◆ USART_ICR_FECF_Pos

#define USART_ICR_FECF_Pos (1U)

◆ USART_ICR_IDLECF

#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk

IDLE line detected Clear Flag

◆ USART_ICR_IDLECF_Msk

#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos)

0x00000010

◆ USART_ICR_IDLECF_Pos

#define USART_ICR_IDLECF_Pos (4U)

◆ USART_ICR_LBDCF

#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk

LIN Break Detection Clear Flag

◆ USART_ICR_LBDCF_Msk

#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos)

0x00000100

◆ USART_ICR_LBDCF_Pos

#define USART_ICR_LBDCF_Pos (8U)

◆ USART_ICR_NECF

#define USART_ICR_NECF USART_ICR_NECF_Msk

Noise Error detected Clear Flag

◆ USART_ICR_NECF_Msk

#define USART_ICR_NECF_Msk (0x1UL << USART_ICR_NECF_Pos)

0x00000004

◆ USART_ICR_NECF_Pos

#define USART_ICR_NECF_Pos (2U)

◆ USART_ICR_ORECF

#define USART_ICR_ORECF USART_ICR_ORECF_Msk

OverRun Error Clear Flag

◆ USART_ICR_ORECF_Msk

#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos)

0x00000008

◆ USART_ICR_ORECF_Pos

#define USART_ICR_ORECF_Pos (3U)

◆ USART_ICR_PECF

#define USART_ICR_PECF USART_ICR_PECF_Msk

Parity Error Clear Flag

◆ USART_ICR_PECF_Msk

#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos)

0x00000001

◆ USART_ICR_PECF_Pos

#define USART_ICR_PECF_Pos (0U)

◆ USART_ICR_RTOCF

#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk

Receiver Time Out Clear Flag

◆ USART_ICR_RTOCF_Msk

#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos)

0x00000800

◆ USART_ICR_RTOCF_Pos

#define USART_ICR_RTOCF_Pos (11U)

◆ USART_ICR_TCBGTCF

#define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk

Transmission Complete Before Guard Time Clear Flag

◆ USART_ICR_TCBGTCF_Msk

#define USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos)

0x00000080

◆ USART_ICR_TCBGTCF_Pos

#define USART_ICR_TCBGTCF_Pos (7U)

◆ USART_ICR_TCCF

#define USART_ICR_TCCF USART_ICR_TCCF_Msk

Transmission Complete Clear Flag

◆ USART_ICR_TCCF_Msk

#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos)

0x00000040

◆ USART_ICR_TCCF_Pos

#define USART_ICR_TCCF_Pos (6U)

◆ USART_ICR_TXFECF

#define USART_ICR_TXFECF USART_ICR_TXFECF_Msk

TXFIFO Empty Clear Flag

◆ USART_ICR_TXFECF_Msk

#define USART_ICR_TXFECF_Msk (0x1UL << USART_ICR_TXFECF_Pos)

0x00000020

◆ USART_ICR_TXFECF_Pos

#define USART_ICR_TXFECF_Pos (5U)

◆ USART_ICR_UDRCF

#define USART_ICR_UDRCF USART_ICR_UDRCF_Msk

SPI Slave Underrun Clear Flag

◆ USART_ICR_UDRCF_Msk

#define USART_ICR_UDRCF_Msk (0x1UL << USART_ICR_UDRCF_Pos)

0x00002000

◆ USART_ICR_UDRCF_Pos

#define USART_ICR_UDRCF_Pos (13U)

◆ USART_ICR_WUCF

#define USART_ICR_WUCF USART_ICR_WUCF_Msk

Wake Up from stop mode Clear Flag

◆ USART_ICR_WUCF_Msk

#define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos)

0x00100000

◆ USART_ICR_WUCF_Pos

#define USART_ICR_WUCF_Pos (20U)

◆ USART_ISR_ABRE

#define USART_ISR_ABRE USART_ISR_ABRE_Msk

Auto-Baud Rate Error

◆ USART_ISR_ABRE_Msk

#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos)

0x00004000

◆ USART_ISR_ABRE_Pos

#define USART_ISR_ABRE_Pos (14U)

◆ USART_ISR_ABRF

#define USART_ISR_ABRF USART_ISR_ABRF_Msk

Auto-Baud Rate Flag

◆ USART_ISR_ABRF_Msk

#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos)

0x00008000

◆ USART_ISR_ABRF_Pos

#define USART_ISR_ABRF_Pos (15U)

◆ USART_ISR_BUSY

#define USART_ISR_BUSY USART_ISR_BUSY_Msk

Busy Flag

◆ USART_ISR_BUSY_Msk

#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos)

0x00010000

◆ USART_ISR_BUSY_Pos

#define USART_ISR_BUSY_Pos (16U)

◆ USART_ISR_CMF

#define USART_ISR_CMF USART_ISR_CMF_Msk

Character Match Flag

◆ USART_ISR_CMF_Msk

#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos)

0x00020000

◆ USART_ISR_CMF_Pos

#define USART_ISR_CMF_Pos (17U)

◆ USART_ISR_CTS

#define USART_ISR_CTS USART_ISR_CTS_Msk

CTS flag

◆ USART_ISR_CTS_Msk

#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos)

0x00000400

◆ USART_ISR_CTS_Pos

#define USART_ISR_CTS_Pos (10U)

◆ USART_ISR_CTSIF

#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk

CTS interrupt flag

◆ USART_ISR_CTSIF_Msk

#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos)

0x00000200

◆ USART_ISR_CTSIF_Pos

#define USART_ISR_CTSIF_Pos (9U)

◆ USART_ISR_EOBF

#define USART_ISR_EOBF USART_ISR_EOBF_Msk

End Of Block Flag

◆ USART_ISR_EOBF_Msk

#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos)

0x00001000

◆ USART_ISR_EOBF_Pos

#define USART_ISR_EOBF_Pos (12U)

◆ USART_ISR_FE

#define USART_ISR_FE USART_ISR_FE_Msk

Framing Error

◆ USART_ISR_FE_Msk

#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos)

0x00000002

◆ USART_ISR_FE_Pos

#define USART_ISR_FE_Pos (1U)

◆ USART_ISR_IDLE

#define USART_ISR_IDLE USART_ISR_IDLE_Msk

IDLE line detected

◆ USART_ISR_IDLE_Msk

#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos)

0x00000010

◆ USART_ISR_IDLE_Pos

#define USART_ISR_IDLE_Pos (4U)

◆ USART_ISR_LBDF

#define USART_ISR_LBDF USART_ISR_LBDF_Msk

LIN Break Detection Flag

◆ USART_ISR_LBDF_Msk

#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos)

0x00000100

◆ USART_ISR_LBDF_Pos

#define USART_ISR_LBDF_Pos (8U)

◆ USART_ISR_NE

#define USART_ISR_NE USART_ISR_NE_Msk

Noise detected Flag

◆ USART_ISR_NE_Msk

#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos)

0x00000004

◆ USART_ISR_NE_Pos

#define USART_ISR_NE_Pos (2U)

◆ USART_ISR_ORE

#define USART_ISR_ORE USART_ISR_ORE_Msk

OverRun Error

◆ USART_ISR_ORE_Msk

#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos)

0x00000008

◆ USART_ISR_ORE_Pos

#define USART_ISR_ORE_Pos (3U)

◆ USART_ISR_PE

#define USART_ISR_PE USART_ISR_PE_Msk

Parity Error

◆ USART_ISR_PE_Msk

#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos)

0x00000001

◆ USART_ISR_PE_Pos

#define USART_ISR_PE_Pos (0U)

◆ USART_ISR_REACK

#define USART_ISR_REACK USART_ISR_REACK_Msk

Receive Enable Acknowledge Flag

◆ USART_ISR_REACK_Msk

#define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos)

0x00400000

◆ USART_ISR_REACK_Pos

#define USART_ISR_REACK_Pos (22U)

◆ USART_ISR_RTOF

#define USART_ISR_RTOF USART_ISR_RTOF_Msk

Receiver Time Out

◆ USART_ISR_RTOF_Msk

#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos)

0x00000800

◆ USART_ISR_RTOF_Pos

#define USART_ISR_RTOF_Pos (11U)

◆ USART_ISR_RWU

#define USART_ISR_RWU USART_ISR_RWU_Msk

Receive Wake Up from mute mode Flag

◆ USART_ISR_RWU_Msk

#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos)

0x00080000

◆ USART_ISR_RWU_Pos

#define USART_ISR_RWU_Pos (19U)

◆ USART_ISR_RXFF

#define USART_ISR_RXFF USART_ISR_RXFF_Msk

RXFIFO Full Flag

◆ USART_ISR_RXFF_Msk

#define USART_ISR_RXFF_Msk (0x1UL << USART_ISR_RXFF_Pos)

0x01000000

◆ USART_ISR_RXFF_Pos

#define USART_ISR_RXFF_Pos (24U)

◆ USART_ISR_RXFT

#define USART_ISR_RXFT USART_ISR_RXFT_Msk

RXFIFO Threshold Flag

◆ USART_ISR_RXFT_Msk

#define USART_ISR_RXFT_Msk (0x1UL << USART_ISR_RXFT_Pos)

0x04000000

◆ USART_ISR_RXFT_Pos

#define USART_ISR_RXFT_Pos (26U)

◆ USART_ISR_RXNE_RXFNE

#define USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE_Msk

Read Data Register Not Empty/RXFIFO Not Empty

◆ USART_ISR_RXNE_RXFNE_Msk

#define USART_ISR_RXNE_RXFNE_Msk (0x1UL << USART_ISR_RXNE_RXFNE_Pos)

0x00000020

◆ USART_ISR_RXNE_RXFNE_Pos

#define USART_ISR_RXNE_RXFNE_Pos (5U)

◆ USART_ISR_SBKF

#define USART_ISR_SBKF USART_ISR_SBKF_Msk

Send Break Flag

◆ USART_ISR_SBKF_Msk

#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos)

0x00040000

◆ USART_ISR_SBKF_Pos

#define USART_ISR_SBKF_Pos (18U)

◆ USART_ISR_TC

#define USART_ISR_TC USART_ISR_TC_Msk

Transmission Complete

◆ USART_ISR_TC_Msk

#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos)

0x00000040

◆ USART_ISR_TC_Pos

#define USART_ISR_TC_Pos (6U)

◆ USART_ISR_TCBGT

#define USART_ISR_TCBGT USART_ISR_TCBGT_Msk

Transmission Complete Before Guard Time Completion Flag

◆ USART_ISR_TCBGT_Msk

#define USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos)

0x02000000

◆ USART_ISR_TCBGT_Pos

#define USART_ISR_TCBGT_Pos (25U)

◆ USART_ISR_TEACK

#define USART_ISR_TEACK USART_ISR_TEACK_Msk

Transmit Enable Acknowledge Flag

◆ USART_ISR_TEACK_Msk

#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos)

0x00200000

◆ USART_ISR_TEACK_Pos

#define USART_ISR_TEACK_Pos (21U)

◆ USART_ISR_TXE_TXFNF

#define USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF_Msk

Transmit Data Register Empty/TXFIFO Not Full

◆ USART_ISR_TXE_TXFNF_Msk

#define USART_ISR_TXE_TXFNF_Msk (0x1UL << USART_ISR_TXE_TXFNF_Pos)

0x00000080

◆ USART_ISR_TXE_TXFNF_Pos

#define USART_ISR_TXE_TXFNF_Pos (7U)

◆ USART_ISR_TXFE

#define USART_ISR_TXFE USART_ISR_TXFE_Msk

TXFIFO Empty Flag

◆ USART_ISR_TXFE_Msk

#define USART_ISR_TXFE_Msk (0x1UL << USART_ISR_TXFE_Pos)

0x00800000

◆ USART_ISR_TXFE_Pos

#define USART_ISR_TXFE_Pos (23U)

◆ USART_ISR_TXFT

#define USART_ISR_TXFT USART_ISR_TXFT_Msk

TXFIFO Threshold Flag

◆ USART_ISR_TXFT_Msk

#define USART_ISR_TXFT_Msk (0x1UL << USART_ISR_TXFT_Pos)

0x08000000

◆ USART_ISR_TXFT_Pos

#define USART_ISR_TXFT_Pos (27U)

◆ USART_ISR_UDR

#define USART_ISR_UDR USART_ISR_UDR_Msk

SPI Slave Underrun Error Flag

◆ USART_ISR_UDR_Msk

#define USART_ISR_UDR_Msk (0x1UL << USART_ISR_UDR_Pos)

0x00002000

◆ USART_ISR_UDR_Pos

#define USART_ISR_UDR_Pos (13U)

◆ USART_ISR_WUF

#define USART_ISR_WUF USART_ISR_WUF_Msk

Wake Up from stop mode Flag

◆ USART_ISR_WUF_Msk

#define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos)

0x00100000

◆ USART_ISR_WUF_Pos

#define USART_ISR_WUF_Pos (20U)

◆ USART_PRESC_PRESCALER

#define USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk

PRESCALER[3:0] bits (Clock prescaler)

◆ USART_PRESC_PRESCALER_0

#define USART_PRESC_PRESCALER_0 (0x1UL << USART_PRESC_PRESCALER_Pos)

0x00000001

◆ USART_PRESC_PRESCALER_1

#define USART_PRESC_PRESCALER_1 (0x2UL << USART_PRESC_PRESCALER_Pos)

0x00000002

◆ USART_PRESC_PRESCALER_2

#define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos)

0x00000004

◆ USART_PRESC_PRESCALER_3

#define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos)

0x00000008

◆ USART_PRESC_PRESCALER_Msk

#define USART_PRESC_PRESCALER_Msk (0xFUL << USART_PRESC_PRESCALER_Pos)

0x0000000F

◆ USART_PRESC_PRESCALER_Pos

#define USART_PRESC_PRESCALER_Pos (0U)

◆ USART_RDR_RDR

#define USART_RDR_RDR USART_RDR_RDR_Msk

RDR[8:0] bits (Receive Data value)

◆ USART_RDR_RDR_Msk

#define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos)

0x000001FF

◆ USART_RDR_RDR_Pos

#define USART_RDR_RDR_Pos (0U)

◆ USART_RQR_ABRRQ

#define USART_RQR_ABRRQ ((uint16_t)0x0001)

Auto-Baud Rate Request

◆ USART_RQR_MMRQ

#define USART_RQR_MMRQ ((uint16_t)0x0004)

Mute Mode Request

◆ USART_RQR_RXFRQ

#define USART_RQR_RXFRQ ((uint16_t)0x0008)

Receive Data flush Request

◆ USART_RQR_SBKRQ

#define USART_RQR_SBKRQ ((uint16_t)0x0002)

Send Break Request

◆ USART_RQR_TXFRQ

#define USART_RQR_TXFRQ ((uint16_t)0x0010)

Transmit data flush Request

◆ USART_RTOR_BLEN

#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk

Block Length

◆ USART_RTOR_BLEN_Msk

#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos)

0xFF000000

◆ USART_RTOR_BLEN_Pos

#define USART_RTOR_BLEN_Pos (24U)

◆ USART_RTOR_RTO

#define USART_RTOR_RTO USART_RTOR_RTO_Msk

Receiver Time Out Value

◆ USART_RTOR_RTO_Msk

#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos)

0x00FFFFFF

◆ USART_RTOR_RTO_Pos

#define USART_RTOR_RTO_Pos (0U)

◆ USART_TDR_TDR

#define USART_TDR_TDR USART_TDR_TDR_Msk

TDR[8:0] bits (Transmit Data value)

◆ USART_TDR_TDR_Msk

#define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos)

0x000001FF

◆ USART_TDR_TDR_Pos

#define USART_TDR_TDR_Pos (0U)

◆ WWDG_CFR_EWI

#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk

Early Wakeup Interrupt

◆ WWDG_CFR_EWI_Msk

#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos)

0x00000200

◆ WWDG_CFR_EWI_Pos

#define WWDG_CFR_EWI_Pos (9U)

◆ WWDG_CFR_W

#define WWDG_CFR_W WWDG_CFR_W_Msk

W[6:0] bits (7-bit window value)

◆ WWDG_CFR_W_0

#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos)

0x00000001

◆ WWDG_CFR_W_1

#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos)

0x00000002

◆ WWDG_CFR_W_2

#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos)

0x00000004

◆ WWDG_CFR_W_3

#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos)

0x00000008

◆ WWDG_CFR_W_4

#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos)

0x00000010

◆ WWDG_CFR_W_5

#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos)

0x00000020

◆ WWDG_CFR_W_6

#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos)

0x00000040

◆ WWDG_CFR_W_Msk

#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos)

0x0000007F

◆ WWDG_CFR_W_Pos

#define WWDG_CFR_W_Pos (0U)

◆ WWDG_CFR_WDGTB

#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk

WDGTB[2:0] bits (Timer Base)

◆ WWDG_CFR_WDGTB_0

#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos)

0x00000800

◆ WWDG_CFR_WDGTB_1

#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos)

0x00001000

◆ WWDG_CFR_WDGTB_2

#define WWDG_CFR_WDGTB_2 (0x4UL << WWDG_CFR_WDGTB_Pos)

0x00002000

◆ WWDG_CFR_WDGTB_Msk

#define WWDG_CFR_WDGTB_Msk (0x7UL << WWDG_CFR_WDGTB_Pos)

0x00003800

◆ WWDG_CFR_WDGTB_Pos

#define WWDG_CFR_WDGTB_Pos (11U)

◆ WWDG_CR_T

#define WWDG_CR_T WWDG_CR_T_Msk

T[6:0] bits (7-Bit counter (MSB to LSB))

◆ WWDG_CR_T_0

#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos)

0x00000001

◆ WWDG_CR_T_1

#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos)

0x00000002

◆ WWDG_CR_T_2

#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos)

0x00000004

◆ WWDG_CR_T_3

#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos)

0x00000008

◆ WWDG_CR_T_4

#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos)

0x00000010

◆ WWDG_CR_T_5

#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos)

0x00000020

◆ WWDG_CR_T_6

#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos)

0x00000040

◆ WWDG_CR_T_Msk

#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos)

0x0000007F

◆ WWDG_CR_T_Pos

#define WWDG_CR_T_Pos (0U)

◆ WWDG_CR_WDGA

#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk

Activation bit

◆ WWDG_CR_WDGA_Msk

#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos)

0x00000080

◆ WWDG_CR_WDGA_Pos

#define WWDG_CR_WDGA_Pos (7U)

◆ WWDG_SR_EWIF

#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk

Early Wakeup Interrupt Flag

◆ WWDG_SR_EWIF_Msk

#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos)

0x00000001

◆ WWDG_SR_EWIF_Pos

#define WWDG_SR_EWIF_Pos (0U)

Modules

Macros

Detailed Description

Macro Definition Documentation

◆ ADC_AWD1TR_HT1

◆ ADC_AWD1TR_HT1_0

◆ ADC_AWD1TR_HT1_1

◆ ADC_AWD1TR_HT1_10

◆ ADC_AWD1TR_HT1_11

◆ ADC_AWD1TR_HT1_2

◆ ADC_AWD1TR_HT1_3

◆ ADC_AWD1TR_HT1_4

◆ ADC_AWD1TR_HT1_5

◆ ADC_AWD1TR_HT1_6

◆ ADC_AWD1TR_HT1_7

◆ ADC_AWD1TR_HT1_8

◆ ADC_AWD1TR_HT1_9

◆ ADC_AWD1TR_HT1_Msk

◆ ADC_AWD1TR_HT1_Pos

◆ ADC_AWD1TR_LT1

◆ ADC_AWD1TR_LT1_0

◆ ADC_AWD1TR_LT1_1

◆ ADC_AWD1TR_LT1_10

◆ ADC_AWD1TR_LT1_11

◆ ADC_AWD1TR_LT1_2

◆ ADC_AWD1TR_LT1_3

◆ ADC_AWD1TR_LT1_4

◆ ADC_AWD1TR_LT1_5

◆ ADC_AWD1TR_LT1_6

◆ ADC_AWD1TR_LT1_7

◆ ADC_AWD1TR_LT1_8

◆ ADC_AWD1TR_LT1_9

◆ ADC_AWD1TR_LT1_Msk

◆ ADC_AWD1TR_LT1_Pos

◆ ADC_AWD2CR_AWD2CH

◆ ADC_AWD2CR_AWD2CH_0

◆ ADC_AWD2CR_AWD2CH_1

◆ ADC_AWD2CR_AWD2CH_10

◆ ADC_AWD2CR_AWD2CH_11

◆ ADC_AWD2CR_AWD2CH_12

◆ ADC_AWD2CR_AWD2CH_13

◆ ADC_AWD2CR_AWD2CH_14

◆ ADC_AWD2CR_AWD2CH_15

◆ ADC_AWD2CR_AWD2CH_16

◆ ADC_AWD2CR_AWD2CH_17

◆ ADC_AWD2CR_AWD2CH_18

◆ ADC_AWD2CR_AWD2CH_2

◆ ADC_AWD2CR_AWD2CH_3

◆ ADC_AWD2CR_AWD2CH_4

◆ ADC_AWD2CR_AWD2CH_5

◆ ADC_AWD2CR_AWD2CH_6

◆ ADC_AWD2CR_AWD2CH_7

◆ ADC_AWD2CR_AWD2CH_8

◆ ADC_AWD2CR_AWD2CH_9

◆ ADC_AWD2CR_AWD2CH_Msk

◆ ADC_AWD2CR_AWD2CH_Pos

◆ ADC_AWD2TR_HT2

◆ ADC_AWD2TR_HT2_0

◆ ADC_AWD2TR_HT2_1

◆ ADC_AWD2TR_HT2_10

◆ ADC_AWD2TR_HT2_11

◆ ADC_AWD2TR_HT2_2

◆ ADC_AWD2TR_HT2_3

◆ ADC_AWD2TR_HT2_4

◆ ADC_AWD2TR_HT2_5

◆ ADC_AWD2TR_HT2_6

◆ ADC_AWD2TR_HT2_7

◆ ADC_AWD2TR_HT2_8

◆ ADC_AWD2TR_HT2_9

◆ ADC_AWD2TR_HT2_Msk

◆ ADC_AWD2TR_HT2_Pos

◆ ADC_AWD2TR_LT2

◆ ADC_AWD2TR_LT2_0

◆ ADC_AWD2TR_LT2_1

◆ ADC_AWD2TR_LT2_10

◆ ADC_AWD2TR_LT2_11

◆ ADC_AWD2TR_LT2_2

◆ ADC_AWD2TR_LT2_3

◆ ADC_AWD2TR_LT2_4

◆ ADC_AWD2TR_LT2_5